MANIFEST.in
README.md
pyproject.toml
setup.py
frontend-rs/Cargo.lock
frontend-rs/Cargo.toml
frontend-rs/src/decode.rs
frontend-rs/src/dtypes.rs
frontend-rs/src/host_abi.rs
frontend-rs/src/ir_tests.rs
frontend-rs/src/lib.rs
frontend-rs/src/registry.rs
frontend-rs/src/schema.rs
frontend-rs/src/serialization.rs
frontend-rs/src/tables.rs
frontend-rs/src/tvm_compat.rs
frontend-rs/src/analyze/buffers.rs
frontend-rs/src/analyze/cuda_arch.rs
frontend-rs/src/analyze/expression_bindings.rs
frontend-rs/src/analyze/frontend.rs
frontend-rs/src/analyze/layout.rs
frontend-rs/src/analyze/memory.rs
frontend-rs/src/analyze/mod.rs
frontend-rs/src/analyze/pointer_targets.rs
frontend-rs/src/analyze/shapes.rs
frontend-rs/src/analyze/topology.rs
frontend-rs/src/analyze/util.rs
frontend-rs/src/analyze/vector.rs
frontend-rs/src/analyze/tile_forms/coordinates.rs
frontend-rs/src/analyze/tile_forms/copy.rs
frontend-rs/src/analyze/tile_forms/gemm.rs
frontend-rs/src/analyze/tile_forms/mod.rs
frontend-rs/src/analyze/tile_forms/numeric.rs
frontend-rs/src/analyze/tile_forms/parse.rs
frontend-rs/src/analyze/tile_forms/tcgen_layout.rs
frontend-rs/src/decode/pointers.rs
frontend-rs/src/decode/ptx.rs
frontend-rs/src/emit/abi.rs
frontend-rs/src/emit/async_copy.rs
frontend-rs/src/emit/atomic_bulk.rs
frontend-rs/src/emit/calls.rs
frontend-rs/src/emit/clc.rs
frontend-rs/src/emit/control.rs
frontend-rs/src/emit/cuda_helper.rs
frontend-rs/src/emit/diagnostics.rs
frontend-rs/src/emit/expr.rs
frontend-rs/src/emit/layout.rs
frontend-rs/src/emit/matrix.rs
frontend-rs/src/emit/matrix_variants.rs
frontend-rs/src/emit/memory_ops.rs
frontend-rs/src/emit/memory_support.rs
frontend-rs/src/emit/mod.rs
frontend-rs/src/emit/module.rs
frontend-rs/src/emit/module_template.rs
frontend-rs/src/emit/ptx_addr.rs
frontend-rs/src/emit/ptx_address.rs
frontend-rs/src/emit/ptx_arithmetic.rs
frontend-rs/src/emit/ptx_bit_carrier.rs
frontend-rs/src/emit/ptx_bitops.rs
frontend-rs/src/emit/ptx_cache_policy.rs
frontend-rs/src/emit/ptx_clmad.rs
frontend-rs/src/emit/ptx_compare.rs
frontend-rs/src/emit/ptx_cvt.rs
frontend-rs/src/emit/ptx_cvt_pack.rs
frontend-rs/src/emit/ptx_cvt_variants.rs
frontend-rs/src/emit/ptx_integer_arithmetic.rs
frontend-rs/src/emit/ptx_lop3.rs
frontend-rs/src/emit/ptx_minmax.rs
frontend-rs/src/emit/ptx_move.rs
frontend-rs/src/emit/ptx_set_packed.rs
frontend-rs/src/emit/ptx_spdecompress.rs
frontend-rs/src/emit/ptx_unary.rs
frontend-rs/src/emit/ptx_warp.rs
frontend-rs/src/emit/pure.rs
frontend-rs/src/emit/raw_memory.rs
frontend-rs/src/emit/raw_tcgen.rs
frontend-rs/src/emit/raw_tma.rs
frontend-rs/src/emit/register_call.rs
frontend-rs/src/emit/scaffold.rs
frontend-rs/src/emit/shared_blocks.rs
frontend-rs/src/emit/stmt.rs
frontend-rs/src/emit/sync.rs
frontend-rs/src/emit/tcgen05.rs
frontend-rs/src/emit/tcgen_descriptor.rs
frontend-rs/src/emit/tile.rs
frontend-rs/src/emit/tile_async_copy.rs
frontend-rs/src/emit/tile_common.rs
frontend-rs/src/emit/tile_gemm_async.rs
frontend-rs/src/emit/tile_tcgen05.rs
frontend-rs/src/emit/tmem.rs
frontend-rs/src/emit/wait_until.rs
frontend-rs/src/emit/raw_tma/host_prelude.rs
frontend-rs/src/emit/shared_blocks/tests.rs
frontend-rs/tests/architecture.rs
frontend-rs/thirdparty/tvm-rust-ext/Cargo.toml
frontend-rs/thirdparty/tvm-rust-ext/LICENSE
frontend-rs/thirdparty/tvm-rust-ext/NOTICE
frontend-rs/thirdparty/tvm-rust-ext/REVISION
frontend-rs/thirdparty/tvm-rust-ext/build.rs
frontend-rs/thirdparty/tvm-rust-ext/src/analysis.rs
frontend-rs/thirdparty/tvm-rust-ext/src/exports.rs
frontend-rs/thirdparty/tvm-rust-ext/src/ir.rs
frontend-rs/thirdparty/tvm-rust-ext/src/lib.rs
frontend-rs/thirdparty/tvm-rust-ext/src/libinfo.rs
frontend-rs/thirdparty/tvm-rust-ext/src/prim.rs
frontend-rs/thirdparty/tvm-rust-ext/src/target.rs
frontend-rs/thirdparty/tvm-rust-ext/src/te.rs
frontend-rs/thirdparty/tvm-rust-ext/src/tirx.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform.rs
frontend-rs/thirdparty/tvm-rust-ext/src/ir/unique_name_supply.rs
frontend-rs/thirdparty/tvm-rust-ext/src/tirx/buffer.rs
frontend-rs/thirdparty/tvm-rust-ext/src/tirx/index_map.rs
frontend-rs/thirdparty/tvm-rust-ext/src/tirx/iter_var.rs
frontend-rs/thirdparty/tvm-rust-ext/src/tirx/tile_primitive.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/analyzer_constraints.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/annotate_entry_func.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/bind_target.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/common_subexpr_elim.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/convert_ssa.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/decorate_device_scope.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/exec_context.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/filter.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/flatten_buffer.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/force_narrow_index.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/inline_private_functions.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/lower_intrin.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/lower_tirx.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/lower_tirx_cleanup.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/lower_tirx_dedup_tensormap.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/lower_tirx_opaque.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/lower_tvm_builtin.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/lower_warp_memory.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/make_packed_api.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/narrow_data_type.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/pointer_value_type_rewrite.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/remap_thread_axis.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/remove_assume.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/remove_no_op.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/scope_id.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/skip_assert.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/split_host_device.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/stmt_simplify.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/storage_rewrite.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/tile_primitive_dispatch.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/unroll_loop.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/unsupported_dtype_legalize.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/utils.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/vectorize_loop.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/verify_memory.rs
frontend-rs/thirdparty/tvm-rust-ext/src/transform/verify_ssa.rs
src/tirx_harness/__init__.py
src/tirx_harness/_report.py
src/tirx_harness/dump_kernel.py
src/tirx_harness.egg-info/PKG-INFO
src/tirx_harness.egg-info/SOURCES.txt
src/tirx_harness.egg-info/dependency_links.txt
src/tirx_harness.egg-info/requires.txt
src/tirx_harness.egg-info/top_level.txt
src/tirx_harness/numsim/__init__.py
src/tirx_harness/numsim/abi.py
src/tirx_harness/numsim/api.py
src/tirx_harness/numsim/bindings.py
src/tirx_harness/numsim/cases.py
src/tirx_harness/numsim/checker_render.py
src/tirx_harness/numsim/checker_report.py
src/tirx_harness/numsim/checker_runner.py
src/tirx_harness/numsim/checkers.py
src/tirx_harness/numsim/dtype_abi.py
src/tirx_harness/numsim/dtype_registry.json
src/tirx_harness/numsim/errors.py
src/tirx_harness/numsim/host_abi.py
src/tirx_harness/numsim/report.py
src/tirx_harness/numsim/value_analysis.py
src/tirx_harness/numsim/engine-rs/Cargo.lock
src/tirx_harness/numsim/engine-rs/Cargo.toml
src/tirx_harness/numsim/engine-rs/ENGINE_ABI.md
src/tirx_harness/numsim/engine-rs/SUPPORTED_OPS.md
src/tirx_harness/numsim/engine-rs/artifact-template/Cargo.lock
src/tirx_harness/numsim/engine-rs/artifact-template/Cargo.toml
src/tirx_harness/numsim/engine-rs/artifact-template/src/lib.rs
src/tirx_harness/numsim/engine-rs/fp-env/Cargo.toml
src/tirx_harness/numsim/engine-rs/fp-env/src/lib.rs
src/tirx_harness/numsim/engine-rs/host-buffer/Cargo.toml
src/tirx_harness/numsim/engine-rs/host-buffer/src/lib.rs
src/tirx_harness/numsim/engine-rs/src/analysis_search.rs
src/tirx_harness/numsim/engine-rs/src/artifact_support.rs
src/tirx_harness/numsim/engine-rs/src/async_groups.rs
src/tirx_harness/numsim/engine-rs/src/async_token.rs
src/tirx_harness/numsim/engine-rs/src/cluster_barriers.rs
src/tirx_harness/numsim/engine-rs/src/collectives.rs
src/tirx_harness/numsim/engine-rs/src/completion.rs
src/tirx_harness/numsim/engine-rs/src/completion_action_id.rs
src/tirx_harness/numsim/engine-rs/src/context.rs
src/tirx_harness/numsim/engine-rs/src/deferred_drop.rs
src/tirx_harness/numsim/engine-rs/src/deferred_payload.rs
src/tirx_harness/numsim/engine-rs/src/deferred_payload_tests.rs
src/tirx_harness/numsim/engine-rs/src/effect.rs
src/tirx_harness/numsim/engine-rs/src/engine_mode.rs
src/tirx_harness/numsim/engine-rs/src/executor.rs
src/tirx_harness/numsim/engine-rs/src/hardware_barriers.rs
src/tirx_harness/numsim/engine-rs/src/hardware_barriers_tests.rs
src/tirx_harness/numsim/engine-rs/src/instruction_codec.rs
src/tirx_harness/numsim/engine-rs/src/instruction_profile.rs
src/tirx_harness/numsim/engine-rs/src/kernel_engine.rs
src/tirx_harness/numsim/engine-rs/src/lib.rs
src/tirx_harness/numsim/engine-rs/src/mask.rs
src/tirx_harness/numsim/engine-rs/src/memory.rs
src/tirx_harness/numsim/engine-rs/src/mode_completions.rs
src/tirx_harness/numsim/engine-rs/src/numpy_backend.rs
src/tirx_harness/numsim/engine-rs/src/operation.rs
src/tirx_harness/numsim/engine-rs/src/ordering.rs
src/tirx_harness/numsim/engine-rs/src/physical_access.rs
src/tirx_harness/numsim/engine-rs/src/profile.rs
src/tirx_harness/numsim/engine-rs/src/resolved_transition.rs
src/tirx_harness/numsim/engine-rs/src/scalar.rs
src/tirx_harness/numsim/engine-rs/src/scheduling.rs
src/tirx_harness/numsim/engine-rs/src/setmaxnreg.rs
src/tirx_harness/numsim/engine-rs/src/setmaxnreg_tests.rs
src/tirx_harness/numsim/engine-rs/src/spaces.rs
src/tirx_harness/numsim/engine-rs/src/strict_cluster_barrier.rs
src/tirx_harness/numsim/engine-rs/src/strict_named_barrier.rs
src/tirx_harness/numsim/engine-rs/src/tcgen.rs
src/tirx_harness/numsim/engine-rs/src/topology.rs
src/tirx_harness/numsim/engine-rs/src/typed_async.rs
src/tirx_harness/numsim/engine-rs/src/typed_copy.rs
src/tirx_harness/numsim/engine-rs/src/warp_value.rs
src/tirx_harness/numsim/engine-rs/src/worker_affinity.rs
src/tirx_harness/numsim/engine-rs/src/abi/mod.rs
src/tirx_harness/numsim/engine-rs/src/abi/v2/addr.rs
src/tirx_harness/numsim/engine-rs/src/abi/v2/async_copy.rs
src/tirx_harness/numsim/engine-rs/src/abi/v2/collective.rs
src/tirx_harness/numsim/engine-rs/src/abi/v2/control.rs
src/tirx_harness/numsim/engine-rs/src/abi/v2/error.rs
src/tirx_harness/numsim/engine-rs/src/abi/v2/instruction.rs
src/tirx_harness/numsim/engine-rs/src/abi/v2/matrix.rs
src/tirx_harness/numsim/engine-rs/src/abi/v2/mem.rs
src/tirx_harness/numsim/engine-rs/src/abi/v2/mod.rs
src/tirx_harness/numsim/engine-rs/src/abi/v2/reg.rs
src/tirx_harness/numsim/engine-rs/src/abi/v2/sync.rs
src/tirx_harness/numsim/engine-rs/src/abi/v2/tcgen05.rs
src/tirx_harness/numsim/engine-rs/src/abi/v2/tile.rs
src/tirx_harness/numsim/engine-rs/src/abi/v2/tmem.rs
src/tirx_harness/numsim/engine-rs/src/abi/v2/transport.rs
src/tirx_harness/numsim/engine-rs/src/abi/v2/warp.rs
src/tirx_harness/numsim/engine-rs/src/artifact_support/frontend_expr.rs
src/tirx_harness/numsim/engine-rs/src/native_analysis/checker_launch.rs
src/tirx_harness/numsim/engine-rs/src/native_analysis/sync_causality.rs
src/tirx_harness/numsim/engine-rs/src/native_analysis/racecheck/global_race.rs
src/tirx_harness/numsim/engine-rs/src/native_analysis/racecheck/race_check.rs
src/tirx_harness/numsim/engine-rs/src/native_analysis/racecheck/race_check_python.rs
src/tirx_harness/numsim/engine-rs/src/native_analysis/racecheck/race_shadow.rs
src/tirx_harness/numsim/engine-rs/src/native_analysis/racecheck/tcgen_fence.rs
src/tirx_harness/numsim/engine-rs/src/native_analysis/racecheck/transactional_interval_map.rs
src/tirx_harness/numsim/engine-rs/src/native_analysis/synccheck/setmaxnreg_verifier.rs
src/tirx_harness/numsim/engine-rs/src/native_analysis/synccheck/setmaxnreg_verifier_tests.rs
src/tirx_harness/numsim/engine-rs/src/native_analysis/synccheck/strict_mbarrier.rs
src/tirx_harness/numsim/engine-rs/src/native_analysis/synccheck/sync_check.rs
src/tirx_harness/numsim/engine-rs/src/native_analysis/synccheck/sync_check_python.rs
src/tirx_harness/numsim/engine-rs/src/native_analysis/synccheck/sync_fixed_unified.rs
src/tirx_harness/numsim/engine-rs/src/native_analysis/synccheck/sync_fixed_verifier.rs
src/tirx_harness/numsim/engine-rs/src/native_analysis/synccheck/sync_partial_order.rs
src/tirx_harness/numsim/engine-rs/src/runtime/abi_transport.rs
src/tirx_harness/numsim/engine-rs/src/runtime/io.rs
src/tirx_harness/numsim/engine-rs/src/runtime/launch.rs
src/tirx_harness/numsim/engine-rs/src/runtime/matrix_ops.rs
src/tirx_harness/numsim/engine-rs/src/runtime/memory_ops.rs
src/tirx_harness/numsim/engine-rs/src/runtime/mod.rs
src/tirx_harness/numsim/engine-rs/src/runtime/operand.rs
src/tirx_harness/numsim/engine-rs/src/runtime/python.rs
src/tirx_harness/numsim/engine-rs/src/runtime/sync.rs
src/tirx_harness/numsim/engine-rs/src/runtime/tcgen_lifecycle.rs
src/tirx_harness/numsim/engine-rs/src/runtime/tcgen_ops.rs
src/tirx_harness/numsim/engine-rs/src/runtime/tcgen_work.rs
src/tirx_harness/numsim/engine-rs/src/runtime/tensor_map.rs
src/tirx_harness/numsim/engine-rs/src/runtime/tensor_map_registry.rs
src/tirx_harness/numsim/engine-rs/src/runtime/tmem.rs
src/tirx_harness/numsim/engine-rs/src/runtime/warp_ops.rs
src/tirx_harness/numsim/engine-rs/src/runtime/instructions/async_copy.rs
src/tirx_harness/numsim/engine-rs/src/runtime/instructions/collective.rs
src/tirx_harness/numsim/engine-rs/src/runtime/instructions/control.rs
src/tirx_harness/numsim/engine-rs/src/runtime/instructions/matrix.rs
src/tirx_harness/numsim/engine-rs/src/runtime/instructions/mem.rs
src/tirx_harness/numsim/engine-rs/src/runtime/instructions/mod.rs
src/tirx_harness/numsim/engine-rs/src/runtime/instructions/mode_axis.rs
src/tirx_harness/numsim/engine-rs/src/runtime/instructions/mov_unpack.rs
src/tirx_harness/numsim/engine-rs/src/runtime/instructions/packed_fma.rs
src/tirx_harness/numsim/engine-rs/src/runtime/instructions/packed_mul.rs
src/tirx_harness/numsim/engine-rs/src/runtime/instructions/prmt.rs
src/tirx_harness/numsim/engine-rs/src/runtime/instructions/reg.rs
src/tirx_harness/numsim/engine-rs/src/runtime/instructions/reg_compare.rs
src/tirx_harness/numsim/engine-rs/src/runtime/instructions/sparse_compress.rs
src/tirx_harness/numsim/engine-rs/src/runtime/instructions/sync.rs
src/tirx_harness/numsim/engine-rs/src/runtime/instructions/tcgen05.rs
src/tirx_harness/numsim/engine-rs/src/runtime/instructions/tile.rs
src/tirx_harness/numsim/engine-rs/src/runtime/instructions/tmem.rs
src/tirx_harness/numsim/engine-rs/src/runtime/instructions/warp.rs
src/tirx_harness/numsim/engine-rs/src/runtime/tcgen_ops/integer.rs
src/tirx_harness/numsim/transpiler/__init__.py
src/tirx_harness/numsim/transpiler/artifact_template.py
src/tirx_harness/numsim/transpiler/build.py
src/tirx_harness/numsim/transpiler/cache.py
src/tirx_harness/numsim/transpiler/compile_cache.py
src/tirx_harness/numsim/transpiler/frontend.py
src/tirx_harness/numsim/transpiler/host_prelude.py
src/tirx_harness/numsim/transpiler/native_frontend.py
src/tirx_harness/numsim/transpiler/ptx_dialect.py
src/tirx_harness/numsim/transpiler/semantic_ir.py
src/tirx_harness/numsim/transpiler/shared_helpers.py
src/tirx_harness/numsim/transpiler/source_map.py
src/tirx_harness/numsim/transpiler/support_matrix.py
src/tirx_harness/numsim/transpiler/suspend_scaffold.py
tests/test_dump_kernel.py
tests/test_packaging.py