rm -f results.xml
"/usr/bin/make" -f Makefile results.xml
make[1]: Entering directory '/prj/dyumnin_projects/peakrdl/ralgen/tests'
rm -f results.xml
COCOTB_TEST_MODULES=cocotbtest_soc COCOTB_TESTCASE= COCOTB_TEST_FILTER= COCOTB_TOPLEVEL=mkMDMA TOPLEVEL_LANG=verilog \
         /usr/local/bin/vvp -M /prj/dyumnin_projects/peakrdl/ralgen/.venv/lib/python3.12/site-packages/cocotb/libs -m libcocotbvpi_icarus   sim_build/sim.vvp -fst  
     -.--ns INFO     gpi                                ..mbed/gpi_embed.cpp:93   in _embed_init_python              Using Python 3.12.4 interpreter at /prj/dyumnin_projects/peakrdl/ralgen/.venv/bin/python
     -.--ns INFO     gpi                                ../gpi/GpiCommon.cpp:79   in gpi_print_registered_impl       VPI registered
     0.00ns INFO     cocotb                             Running on Icarus Verilog version 13.0 (devel)
     0.00ns INFO     cocotb                             Seeding Python random module with 1772555044
     0.00ns INFO     cocotb                             Initialized cocotb v2.0.1 from /prj/dyumnin_projects/peakrdl/ralgen/.venv/lib/python3.12/site-packages/cocotb
     0.00ns INFO     cocotb                             Running tests
     0.00ns INFO     cocotb.regression                  running cocotbtest_soc.test_ral_reset (1/4)
                                                            Ral test reset.
     0.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master (write)
     0.00ns INFO     cocotb.mkMDMA.csr_axi4             cocotbext-axi version 0.1.26
     0.00ns INFO     cocotb.mkMDMA.csr_axi4             Copyright (c) 2020-2025 Alex Forencich
     0.00ns INFO     cocotb.mkMDMA.csr_axi4             https://github.com/alexforencich/cocotbext-axi
     0.00ns WARNING  py.warnings                        /prj/dyumnin_projects/peakrdl/ralgen/.venv/lib/python3.12/site-packages/cocotbext/axi/stream.py:120: DeprecationWarning: Use `handle.set(Immediate(...))` or `handle.value = Immediate(...)` instead.
                                                          self.valid.setimmediatevalue(self._valid_init)
     0.00ns WARNING  py.warnings                        /prj/dyumnin_projects/peakrdl/ralgen/.venv/lib/python3.12/site-packages/cocotbext/axi/stream.py:133: DeprecationWarning: Use `handle.set(Immediate(...))` or `handle.value = Immediate(...)` instead.
                                                          s.setimmediatevalue(v)
     0.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
     0.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
     0.00ns WARNING  py.warnings                        /prj/dyumnin_projects/peakrdl/ralgen/.venv/lib/python3.12/site-packages/cocotbext/axi/stream.py:115: DeprecationWarning: Use `handle.set(Immediate(...))` or `handle.value = Immediate(...)` instead.
                                                          self.ready.setimmediatevalue(self._ready_init)
     0.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
     0.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master configuration:
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               Address width: 32 bits
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               Byte size: 8 bits
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               Data width: 32 bits (4 bytes)
     0.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master signals:
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               awaddr width: 32 bits
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               awprot width: 3 bits
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               awready width: 1 bits
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               awvalid width: 1 bits
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               wdata width: 32 bits
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               wready width: 1 bits
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               wstrb width: 4 bits
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               wvalid width: 1 bits
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               bready width: 1 bits
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               bresp width: 2 bits
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               bvalid width: 1 bits
     0.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
     0.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master (read)
     0.00ns INFO     cocotb.mkMDMA.csr_axi4             cocotbext-axi version 0.1.26
     0.00ns INFO     cocotb.mkMDMA.csr_axi4             Copyright (c) 2020-2025 Alex Forencich
     0.00ns INFO     cocotb.mkMDMA.csr_axi4             https://github.com/alexforencich/cocotbext-axi
     0.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
     0.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
     0.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master configuration:
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               Address width: 32 bits
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               Byte size: 8 bits
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               Data width: 32 bits (4 bytes)
     0.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master signals:
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               araddr width: 32 bits
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               arprot width: 3 bits
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               arready width: 1 bits
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               arvalid width: 1 bits
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               rdata width: 32 bits
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               rready width: 1 bits
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               rresp width: 2 bits
     0.00ns INFO     cocotb.mkMDMA.csr_axi4               rvalid width: 1 bits
     0.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
     0.00ns INFO     test                               
                                                                Cocotb RALGEN: SystemRDL to RALtest converter.
                                                                Copyright © 2024 Dyumnin Semiconductors.
                                                                https://dyumnin.com
                                                                
     0.00ns WARNING  py.warnings                        /prj/dyumnin_projects/peakrdl/ralgen/.venv/lib/python3.12/site-packages/cocotbext/axi/reset.py:59: DeprecationWarning: Use `signal.value_change` instead.
                                                          await Edge(reset_signal)
     1.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
     1.00ns WARNING  py.warnings                        /prj/dyumnin_projects/peakrdl/ralgen/.venv/lib/python3.12/site-packages/cocotbext/axi/stream.py:156: DeprecationWarning: `task.kill()` is deprecated in favor of `task.cancel()`
                                                          self._run_cr.kill()
     1.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
     1.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
     1.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
     1.00ns WARNING  py.warnings                        /prj/dyumnin_projects/peakrdl/ralgen/.venv/lib/python3.12/site-packages/cocotbext/axi/axil_master.py:214: DeprecationWarning: `task.kill()` is deprecated in favor of `task.cancel()`
                                                          self._process_write_cr.kill()
     1.00ns WARNING  py.warnings                        /prj/dyumnin_projects/peakrdl/ralgen/.venv/lib/python3.12/site-packages/cocotbext/axi/axil_master.py:217: DeprecationWarning: `task.kill()` is deprecated in favor of `task.cancel()`
                                                          self._process_write_resp_cr.kill()
     1.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
     1.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
     1.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
     1.00ns WARNING  py.warnings                        /prj/dyumnin_projects/peakrdl/ralgen/.venv/lib/python3.12/site-packages/cocotbext/axi/axil_master.py:466: DeprecationWarning: `task.kill()` is deprecated in favor of `task.cancel()`
                                                          self._process_read_cr.kill()
     1.00ns WARNING  py.warnings                        /prj/dyumnin_projects/peakrdl/ralgen/.venv/lib/python3.12/site-packages/cocotbext/axi/axil_master.py:469: DeprecationWarning: `task.kill()` is deprecated in favor of `task.cancel()`
                                                          self._process_read_resp_cr.kill()
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma0_Cfg, Value 101
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma0_Ctrl, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma0_Dest_Address, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma0_Interrupt, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma0_Interrupt_Mask, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma0_Interrupt_Test, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma0_Length, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma0_PD_Count, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma0_PacketDescriptor_Address, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma0_Src_Address, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma0_Status, Value 0
   111.00ns ERROR    test                               Reset Read Reg:soc_sdma0_dma0_Version, actual 0 expected 10000
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma0_Version, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma1_Cfg, Value 101
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma1_Ctrl, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma1_Dest_Address, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma1_Interrupt, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma1_Interrupt_Mask, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma1_Interrupt_Test, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma1_Length, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma1_PD_Count, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma1_PacketDescriptor_Address, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma1_Src_Address, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma1_Status, Value 0
   111.00ns ERROR    test                               Reset Read Reg:soc_sdma0_dma1_Version, actual 0 expected 10000
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma1_Version, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma2_Cfg, Value 101
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma2_Ctrl, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma2_Dest_Address, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma2_Interrupt, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma2_Interrupt_Mask, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma2_Interrupt_Test, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma2_Length, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma2_PD_Count, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma2_PacketDescriptor_Address, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma2_Src_Address, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma2_Status, Value 0
   111.00ns ERROR    test                               Reset Read Reg:soc_sdma0_dma2_Version, actual 0 expected 10000
   111.00ns INFO     test                               Reset Read Reg:soc_sdma0_dma2_Version, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma0_Cfg, Value 101
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma0_Ctrl, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma0_Dest_Address, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma0_Interrupt, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma0_Interrupt_Mask, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma0_Interrupt_Test, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma0_Length, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma0_PD_Count, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma0_PacketDescriptor_Address, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma0_Src_Address, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma0_Status, Value 0
   111.00ns ERROR    test                               Reset Read Reg:soc_sdma1_dma0_Version, actual 0 expected 10000
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma0_Version, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma1_Cfg, Value 101
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma1_Ctrl, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma1_Dest_Address, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma1_Interrupt, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma1_Interrupt_Mask, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma1_Interrupt_Test, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma1_Length, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma1_PD_Count, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma1_PacketDescriptor_Address, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma1_Src_Address, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma1_Status, Value 0
   111.00ns ERROR    test                               Reset Read Reg:soc_sdma1_dma1_Version, actual 0 expected 10000
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma1_Version, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma2_Cfg, Value 101
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma2_Ctrl, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma2_Dest_Address, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma2_Interrupt, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma2_Interrupt_Mask, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma2_Interrupt_Test, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma2_Length, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma2_PD_Count, Value 0
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma2_PacketDescriptor_Address, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma2_Src_Address, Value aaaaaaaa
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma2_Status, Value 0
   111.00ns ERROR    test                               Reset Read Reg:soc_sdma1_dma2_Version, actual 0 expected 10000
   111.00ns INFO     test                               Reset Read Reg:soc_sdma1_dma2_Version, Value 0
   111.00ns WARNING  ..st test_ral_reset.test_ral_reset Test exited with 6 Error
                                                        assert 6 == 0
                                                        Traceback (most recent call last):
                                                          File "/prj/dyumnin_projects/peakrdl/ralgen/tests/cocotbtest_soc.py", line 16, in test_ral_reset
                                                            await run_ral_reset_check(env, ral)
                                                          File "/prj/dyumnin_projects/peakrdl/ralgen/tests/cocotbtest_soc.py", line 50, in run_ral_reset_check
                                                            await reset_test.reset_test(ral, verbose=True)
                                                                  ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
                                                          File "/prj/dyumnin_projects/peakrdl/ralgen/src/peakrdl_cocotb_ralgen/testcases/reset_test.py", line 32, in reset_test
                                                            assert error_count == 0, f"Test exited with {error_count} Error"
                                                        AssertionError: Test exited with 6 Error
                                                        assert 6 == 0
   111.00ns WARNING  cocotb.regression                  cocotbtest_soc.test_ral_reset failed
   111.00ns INFO     cocotb.regression                  running cocotbtest_soc.test_ral_fgwr_fgrd (2/4)
                                                            Ral test foreground rd and write.
   111.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master (write)
   111.00ns INFO     cocotb.mkMDMA.csr_axi4             cocotbext-axi version 0.1.26
   111.00ns INFO     cocotb.mkMDMA.csr_axi4             Copyright (c) 2020-2025 Alex Forencich
   111.00ns INFO     cocotb.mkMDMA.csr_axi4             https://github.com/alexforencich/cocotbext-axi
   111.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
   111.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
   111.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
   111.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master configuration:
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               Address width: 32 bits
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               Byte size: 8 bits
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               Data width: 32 bits (4 bytes)
   111.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master signals:
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               awaddr width: 32 bits
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               awprot width: 3 bits
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               awready width: 1 bits
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               awvalid width: 1 bits
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               wdata width: 32 bits
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               wready width: 1 bits
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               wstrb width: 4 bits
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               wvalid width: 1 bits
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               bready width: 1 bits
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               bresp width: 2 bits
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               bvalid width: 1 bits
   111.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
   111.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master (read)
   111.00ns INFO     cocotb.mkMDMA.csr_axi4             cocotbext-axi version 0.1.26
   111.00ns INFO     cocotb.mkMDMA.csr_axi4             Copyright (c) 2020-2025 Alex Forencich
   111.00ns INFO     cocotb.mkMDMA.csr_axi4             https://github.com/alexforencich/cocotbext-axi
   111.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
   111.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
   111.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master configuration:
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               Address width: 32 bits
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               Byte size: 8 bits
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               Data width: 32 bits (4 bytes)
   111.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master signals:
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               araddr width: 32 bits
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               arprot width: 3 bits
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               arready width: 1 bits
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               arvalid width: 1 bits
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               rdata width: 32 bits
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               rready width: 1 bits
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               rresp width: 2 bits
   111.00ns INFO     cocotb.mkMDMA.csr_axi4               rvalid width: 1 bits
   111.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
   111.00ns INFO     test                               
                                                                Cocotb RALGEN: SystemRDL to RALtest converter.
                                                                Copyright © 2024 Dyumnin Semiconductors.
                                                                https://dyumnin.com
                                                                
   112.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
   112.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
   112.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
   112.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
   112.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
   112.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
   112.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
   261.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
   261.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
   261.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
   261.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
   261.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
   261.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
   261.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
   266.00ns INFO     test                               RegWrite, addr=0x10 data=0xa77f1fd4
   266.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00000010 prot: 2 data: d4 1f 7f a7
   326.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00000010 prot: 2 resp: 0 length: 4
   326.00ns WARNING  py.warnings                        /prj/dyumnin_projects/peakrdl/ralgen/.venv/lib/python3.12/site-packages/cocotbext/axi/axil_master.py:336: DeprecationWarning: The data field will be removed in a future release.
                                                          cmd.event.set(write_resp)
   326.00ns WARNING  py.warnings                        /prj/dyumnin_projects/peakrdl/ralgen/.venv/lib/python3.12/site-packages/cocotbext/axi/axil_master.py:205: DeprecationWarning: The data field will be removed in a future release.
                                                          return event.data
   326.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00000010 prot: 2 length: 4
   386.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00000010 prot: 2 resp: 1 data: d4 1f 0f 00
   386.00ns WARNING  py.warnings                        /prj/dyumnin_projects/peakrdl/ralgen/.venv/lib/python3.12/site-packages/cocotbext/axi/axil_master.py:572: DeprecationWarning: The data field will be removed in a future release.
                                                          cmd.event.set(read_resp)
   386.00ns WARNING  py.warnings                        /prj/dyumnin_projects/peakrdl/ralgen/.venv/lib/python3.12/site-packages/cocotbext/axi/axil_master.py:457: DeprecationWarning: The data field will be removed in a future release.
                                                          return event.data
   386.00ns INFO     test                               RegRead addr=10 rdata=0xf1fd4
   386.00ns INFO     test                               Test RW: soc_sdma0_dma0_Cfg wval a77f1fd4 rv f1fd4 expected f1fd4 actual f1fd4
   386.00ns INFO     test                               RegWrite, addr=0x8 data=0xa0ce5f62
   386.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00000008 prot: 2 data: 62 5f ce a0
   446.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00000008 prot: 2 resp: 0 length: 4
   446.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00000008 prot: 2 length: 4
   506.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00000008 prot: 2 resp: 1 data: 22 00 00 00
   506.00ns INFO     test                               RegRead addr=8 rdata=0x22
   506.00ns INFO     test                               Test RW: soc_sdma0_dma0_Ctrl wval a0ce5f62 rv 22 expected 22 actual 22
   506.00ns INFO     test                               RegWrite, addr=0x18 data=0x2cb5689d
   506.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00000018 prot: 2 data: 9d 68 b5 2c
   566.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00000018 prot: 2 resp: 0 length: 4
   566.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00000018 prot: 2 length: 4
   626.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00000018 prot: 2 resp: 1 data: 9d 68 b5 2c
   626.00ns INFO     test                               RegRead addr=18 rdata=0x2cb5689d
   626.00ns INFO     test                               Test RW: soc_sdma0_dma0_Dest_Address wval 2cb5689d rv 2cb5689d expected 2cb5689d actual 2cb5689d
   626.00ns INFO     test                               RegWrite, addr=0x24 data=0x261d0e68
   626.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00000024 prot: 2 data: 68 0e 1d 26
   686.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00000024 prot: 2 resp: 0 length: 4
   686.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00000024 prot: 2 length: 4
   746.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00000024 prot: 2 resp: 1 data: 00 00 00 00
   746.00ns INFO     test                               RegRead addr=24 rdata=0x0
   746.00ns INFO     test                               Test RW: soc_sdma0_dma0_Interrupt wval 261d0e68 rv 0 expected 0 actual 0
   746.00ns INFO     test                               RegWrite, addr=0x28 data=0xe089161f
   746.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00000028 prot: 2 data: 1f 16 89 e0
   806.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00000028 prot: 2 resp: 0 length: 4
   806.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00000028 prot: 2 length: 4
   866.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00000028 prot: 2 resp: 1 data: 07 00 00 00
   866.00ns INFO     test                               RegRead addr=28 rdata=0x7
   866.00ns INFO     test                               Test RW: soc_sdma0_dma0_Interrupt_Mask wval e089161f rv 7 expected 7 actual 7
   866.00ns INFO     test                               RegWrite, addr=0x2c data=0x9601bde0
   866.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000002c prot: 2 data: e0 bd 01 96
   926.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000002c prot: 2 resp: 0 length: 4
   926.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000002c prot: 2 length: 4
   986.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000002c prot: 2 resp: 1 data: 00 00 00 00
   986.00ns INFO     test                               RegRead addr=2c rdata=0x0
   986.00ns INFO     test                               Test RW: soc_sdma0_dma0_Interrupt_Test wval 9601bde0 rv 0 expected 0 actual 0
   986.00ns INFO     test                               RegWrite, addr=0x1c data=0x16700b62
   986.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000001c prot: 2 data: 62 0b 70 16
  1046.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000001c prot: 2 resp: 0 length: 4
  1046.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000001c prot: 2 length: 4
  1106.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000001c prot: 2 resp: 1 data: 62 0b 70 16
  1106.00ns INFO     test                               RegRead addr=1c rdata=0x16700b62
  1106.00ns INFO     test                               Test RW: soc_sdma0_dma0_Length wval 16700b62 rv 16700b62 expected 16700b62 actual 16700b62
  1106.00ns INFO     test                               RegWrite, addr=0xc data=0xc85aafa4
  1106.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000000c prot: 2 data: a4 af 5a c8
  1166.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000000c prot: 2 resp: 0 length: 4
  1166.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000000c prot: 2 length: 4
  1226.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000000c prot: 2 resp: 1 data: 00 00 00 00
  1226.00ns INFO     test                               RegRead addr=c rdata=0x0
  1226.00ns INFO     test                               Test RW: soc_sdma0_dma0_PD_Count wval c85aafa4 rv 0 expected 0 actual 0
  1226.00ns INFO     test                               RegWrite, addr=0x20 data=0x60b35fbf
  1226.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00000020 prot: 2 data: bf 5f b3 60
  1286.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00000020 prot: 2 resp: 0 length: 4
  1286.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00000020 prot: 2 length: 4
  1346.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00000020 prot: 2 resp: 1 data: bf 5f b3 60
  1346.00ns INFO     test                               RegRead addr=20 rdata=0x60b35fbf
  1346.00ns INFO     test                               Test RW: soc_sdma0_dma0_PacketDescriptor_Address wval 60b35fbf rv 60b35fbf expected 60b35fbf actual 60b35fbf
  1346.00ns INFO     test                               RegWrite, addr=0x14 data=0xa07a92d8
  1346.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00000014 prot: 2 data: d8 92 7a a0
  1406.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00000014 prot: 2 resp: 0 length: 4
  1406.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00000014 prot: 2 length: 4
  1466.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00000014 prot: 2 resp: 1 data: d8 92 7a a0
  1466.00ns INFO     test                               RegRead addr=14 rdata=0xa07a92d8
  1466.00ns INFO     test                               Test RW: soc_sdma0_dma0_Src_Address wval a07a92d8 rv a07a92d8 expected a07a92d8 actual a07a92d8
  1466.00ns INFO     test                               RegWrite, addr=0x4 data=0xf7c45290
  1466.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00000004 prot: 2 data: 90 52 c4 f7
  1526.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00000004 prot: 2 resp: 0 length: 4
  1526.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00000004 prot: 2 length: 4
  1586.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00000004 prot: 2 resp: 1 data: 00 00 00 00
  1586.00ns INFO     test                               RegRead addr=4 rdata=0x0
  1586.00ns INFO     test                               Test RW: soc_sdma0_dma0_Status wval f7c45290 rv 0 expected 0 actual 0
  1586.00ns INFO     test                               RegWrite, addr=0x1010 data=0x96acf0c1
  1586.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00001010 prot: 2 data: c1 f0 ac 96
  1646.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00001010 prot: 2 resp: 0 length: 4
  1646.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00001010 prot: 2 length: 4
  1706.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00001010 prot: 2 resp: 1 data: c1 f0 0c 00
  1706.00ns INFO     test                               RegRead addr=1010 rdata=0xcf0c1
  1706.00ns INFO     test                               Test RW: soc_sdma0_dma1_Cfg wval 96acf0c1 rv cf0c1 expected cf0c1 actual cf0c1
  1706.00ns INFO     test                               RegWrite, addr=0x1008 data=0xa5aa8006
  1706.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00001008 prot: 2 data: 06 80 aa a5
  1766.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00001008 prot: 2 resp: 0 length: 4
  1766.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00001008 prot: 2 length: 4
  1826.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00001008 prot: 2 resp: 1 data: 06 00 00 00
  1826.00ns INFO     test                               RegRead addr=1008 rdata=0x6
  1826.00ns INFO     test                               Test RW: soc_sdma0_dma1_Ctrl wval a5aa8006 rv 6 expected 6 actual 6
  1826.00ns INFO     test                               RegWrite, addr=0x1018 data=0xa27c98fa
  1826.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00001018 prot: 2 data: fa 98 7c a2
  1886.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00001018 prot: 2 resp: 0 length: 4
  1886.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00001018 prot: 2 length: 4
  1946.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00001018 prot: 2 resp: 1 data: fa 98 7c a2
  1946.00ns INFO     test                               RegRead addr=1018 rdata=0xa27c98fa
  1946.00ns INFO     test                               Test RW: soc_sdma0_dma1_Dest_Address wval a27c98fa rv a27c98fa expected a27c98fa actual a27c98fa
  1946.00ns INFO     test                               RegWrite, addr=0x1024 data=0x800763b8
  1946.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00001024 prot: 2 data: b8 63 07 80
  2006.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00001024 prot: 2 resp: 0 length: 4
  2006.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00001024 prot: 2 length: 4
  2066.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00001024 prot: 2 resp: 1 data: 00 00 00 00
  2066.00ns INFO     test                               RegRead addr=1024 rdata=0x0
  2066.00ns INFO     test                               Test RW: soc_sdma0_dma1_Interrupt wval 800763b8 rv 0 expected 0 actual 0
  2066.00ns INFO     test                               RegWrite, addr=0x1028 data=0x2f58c8bf
  2066.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00001028 prot: 2 data: bf c8 58 2f
  2126.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00001028 prot: 2 resp: 0 length: 4
  2126.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00001028 prot: 2 length: 4
  2186.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00001028 prot: 2 resp: 1 data: 07 00 00 00
  2186.00ns INFO     test                               RegRead addr=1028 rdata=0x7
  2186.00ns INFO     test                               Test RW: soc_sdma0_dma1_Interrupt_Mask wval 2f58c8bf rv 7 expected 7 actual 7
  2186.00ns INFO     test                               RegWrite, addr=0x102c data=0xe0e9704f
  2186.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000102c prot: 2 data: 4f 70 e9 e0
  2246.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000102c prot: 2 resp: 0 length: 4
  2246.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000102c prot: 2 length: 4
  2306.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000102c prot: 2 resp: 1 data: 07 00 00 00
  2306.00ns INFO     test                               RegRead addr=102c rdata=0x7
  2306.00ns INFO     test                               Test RW: soc_sdma0_dma1_Interrupt_Test wval e0e9704f rv 7 expected 7 actual 7
  2306.00ns INFO     test                               RegWrite, addr=0x101c data=0x30914ee3
  2306.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000101c prot: 2 data: e3 4e 91 30
  2366.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000101c prot: 2 resp: 0 length: 4
  2366.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000101c prot: 2 length: 4
  2426.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000101c prot: 2 resp: 1 data: e3 4e 91 30
  2426.00ns INFO     test                               RegRead addr=101c rdata=0x30914ee3
  2426.00ns INFO     test                               Test RW: soc_sdma0_dma1_Length wval 30914ee3 rv 30914ee3 expected 30914ee3 actual 30914ee3
  2426.00ns INFO     test                               RegWrite, addr=0x100c data=0x776310e
  2426.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000100c prot: 2 data: 0e 31 76 07
  2486.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000100c prot: 2 resp: 0 length: 4
  2486.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000100c prot: 2 length: 4
  2546.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000100c prot: 2 resp: 1 data: 00 00 00 00
  2546.00ns INFO     test                               RegRead addr=100c rdata=0x0
  2546.00ns INFO     test                               Test RW: soc_sdma0_dma1_PD_Count wval 776310e rv 0 expected 0 actual 0
  2546.00ns INFO     test                               RegWrite, addr=0x1020 data=0x6a59bdbd
  2546.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00001020 prot: 2 data: bd bd 59 6a
  2606.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00001020 prot: 2 resp: 0 length: 4
  2606.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00001020 prot: 2 length: 4
  2666.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00001020 prot: 2 resp: 1 data: bd bd 59 6a
  2666.00ns INFO     test                               RegRead addr=1020 rdata=0x6a59bdbd
  2666.00ns INFO     test                               Test RW: soc_sdma0_dma1_PacketDescriptor_Address wval 6a59bdbd rv 6a59bdbd expected 6a59bdbd actual 6a59bdbd
  2666.00ns INFO     test                               RegWrite, addr=0x1014 data=0xb1aa5d9e
  2666.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00001014 prot: 2 data: 9e 5d aa b1
  2726.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00001014 prot: 2 resp: 0 length: 4
  2726.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00001014 prot: 2 length: 4
  2786.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00001014 prot: 2 resp: 1 data: 9e 5d aa b1
  2786.00ns INFO     test                               RegRead addr=1014 rdata=0xb1aa5d9e
  2786.00ns INFO     test                               Test RW: soc_sdma0_dma1_Src_Address wval b1aa5d9e rv b1aa5d9e expected b1aa5d9e actual b1aa5d9e
  2786.00ns INFO     test                               RegWrite, addr=0x1004 data=0xf110ca91
  2786.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00001004 prot: 2 data: 91 ca 10 f1
  2846.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00001004 prot: 2 resp: 0 length: 4
  2846.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00001004 prot: 2 length: 4
  2906.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00001004 prot: 2 resp: 1 data: 00 00 00 00
  2906.00ns INFO     test                               RegRead addr=1004 rdata=0x0
  2906.00ns INFO     test                               Test RW: soc_sdma0_dma1_Status wval f110ca91 rv 0 expected 0 actual 0
  2906.00ns INFO     test                               RegWrite, addr=0x2010 data=0xad80b2b5
  2906.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00002010 prot: 2 data: b5 b2 80 ad
  2966.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00002010 prot: 2 resp: 0 length: 4
  2966.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00002010 prot: 2 length: 4
  3026.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00002010 prot: 2 resp: 1 data: b5 b2 00 00
  3026.00ns INFO     test                               RegRead addr=2010 rdata=0xb2b5
  3026.00ns INFO     test                               Test RW: soc_sdma0_dma2_Cfg wval ad80b2b5 rv b2b5 expected b2b5 actual b2b5
  3026.00ns INFO     test                               RegWrite, addr=0x2008 data=0x74947252
  3026.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00002008 prot: 2 data: 52 72 94 74
  3086.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00002008 prot: 2 resp: 0 length: 4
  3086.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00002008 prot: 2 length: 4
  3146.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00002008 prot: 2 resp: 1 data: 12 00 00 00
  3146.00ns INFO     test                               RegRead addr=2008 rdata=0x12
  3146.00ns INFO     test                               Test RW: soc_sdma0_dma2_Ctrl wval 74947252 rv 12 expected 12 actual 12
  3146.00ns INFO     test                               RegWrite, addr=0x2018 data=0x9c88dafa
  3146.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00002018 prot: 2 data: fa da 88 9c
  3206.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00002018 prot: 2 resp: 0 length: 4
  3206.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00002018 prot: 2 length: 4
  3266.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00002018 prot: 2 resp: 1 data: fa da 88 9c
  3266.00ns INFO     test                               RegRead addr=2018 rdata=0x9c88dafa
  3266.00ns INFO     test                               Test RW: soc_sdma0_dma2_Dest_Address wval 9c88dafa rv 9c88dafa expected 9c88dafa actual 9c88dafa
  3266.00ns INFO     test                               RegWrite, addr=0x2024 data=0x2732e348
  3266.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00002024 prot: 2 data: 48 e3 32 27
  3326.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00002024 prot: 2 resp: 0 length: 4
  3326.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00002024 prot: 2 length: 4
  3386.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00002024 prot: 2 resp: 1 data: 00 00 00 00
  3386.00ns INFO     test                               RegRead addr=2024 rdata=0x0
  3386.00ns INFO     test                               Test RW: soc_sdma0_dma2_Interrupt wval 2732e348 rv 0 expected 0 actual 0
  3386.00ns INFO     test                               RegWrite, addr=0x2028 data=0x6282749b
  3386.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00002028 prot: 2 data: 9b 74 82 62
  3446.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00002028 prot: 2 resp: 0 length: 4
  3446.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00002028 prot: 2 length: 4
  3506.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00002028 prot: 2 resp: 1 data: 03 00 00 00
  3506.00ns INFO     test                               RegRead addr=2028 rdata=0x3
  3506.00ns INFO     test                               Test RW: soc_sdma0_dma2_Interrupt_Mask wval 6282749b rv 3 expected 3 actual 3
  3506.00ns INFO     test                               RegWrite, addr=0x202c data=0x458cc512
  3506.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000202c prot: 2 data: 12 c5 8c 45
  3566.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000202c prot: 2 resp: 0 length: 4
  3566.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000202c prot: 2 length: 4
  3626.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000202c prot: 2 resp: 1 data: 02 00 00 00
  3626.00ns INFO     test                               RegRead addr=202c rdata=0x2
  3626.00ns INFO     test                               Test RW: soc_sdma0_dma2_Interrupt_Test wval 458cc512 rv 2 expected 2 actual 2
  3626.00ns INFO     test                               RegWrite, addr=0x201c data=0xa4224b2
  3626.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000201c prot: 2 data: b2 24 42 0a
  3686.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000201c prot: 2 resp: 0 length: 4
  3686.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000201c prot: 2 length: 4
  3746.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000201c prot: 2 resp: 1 data: b2 24 42 0a
  3746.00ns INFO     test                               RegRead addr=201c rdata=0xa4224b2
  3746.00ns INFO     test                               Test RW: soc_sdma0_dma2_Length wval a4224b2 rv a4224b2 expected a4224b2 actual a4224b2
  3746.00ns INFO     test                               RegWrite, addr=0x200c data=0x73a05bd4
  3746.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000200c prot: 2 data: d4 5b a0 73
  3806.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000200c prot: 2 resp: 0 length: 4
  3806.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000200c prot: 2 length: 4
  3866.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000200c prot: 2 resp: 1 data: 00 00 00 00
  3866.00ns INFO     test                               RegRead addr=200c rdata=0x0
  3866.00ns INFO     test                               Test RW: soc_sdma0_dma2_PD_Count wval 73a05bd4 rv 0 expected 0 actual 0
  3866.00ns INFO     test                               RegWrite, addr=0x2020 data=0x83e5cb2b
  3866.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00002020 prot: 2 data: 2b cb e5 83
  3926.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00002020 prot: 2 resp: 0 length: 4
  3926.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00002020 prot: 2 length: 4
  3986.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00002020 prot: 2 resp: 1 data: 2b cb e5 83
  3986.00ns INFO     test                               RegRead addr=2020 rdata=0x83e5cb2b
  3986.00ns INFO     test                               Test RW: soc_sdma0_dma2_PacketDescriptor_Address wval 83e5cb2b rv 83e5cb2b expected 83e5cb2b actual 83e5cb2b
  3986.00ns INFO     test                               RegWrite, addr=0x2014 data=0x661feb9b
  3986.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00002014 prot: 2 data: 9b eb 1f 66
  4046.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00002014 prot: 2 resp: 0 length: 4
  4046.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00002014 prot: 2 length: 4
  4106.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00002014 prot: 2 resp: 1 data: 9b eb 1f 66
  4106.00ns INFO     test                               RegRead addr=2014 rdata=0x661feb9b
  4106.00ns INFO     test                               Test RW: soc_sdma0_dma2_Src_Address wval 661feb9b rv 661feb9b expected 661feb9b actual 661feb9b
  4106.00ns INFO     test                               RegWrite, addr=0x2004 data=0xf081c540
  4106.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00002004 prot: 2 data: 40 c5 81 f0
  4166.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00002004 prot: 2 resp: 0 length: 4
  4166.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00002004 prot: 2 length: 4
  4226.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00002004 prot: 2 resp: 1 data: 00 00 00 00
  4226.00ns INFO     test                               RegRead addr=2004 rdata=0x0
  4226.00ns INFO     test                               Test RW: soc_sdma0_dma2_Status wval f081c540 rv 0 expected 0 actual 0
  4226.00ns INFO     test                               RegWrite, addr=0x4010 data=0x72a52130
  4226.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00004010 prot: 2 data: 30 21 a5 72
  4286.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00004010 prot: 2 resp: 0 length: 4
  4286.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00004010 prot: 2 length: 4
  4346.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00004010 prot: 2 resp: 1 data: 30 21 05 00
  4346.00ns INFO     test                               RegRead addr=4010 rdata=0x52130
  4346.00ns INFO     test                               Test RW: soc_sdma1_dma0_Cfg wval 72a52130 rv 52130 expected 52130 actual 52130
  4346.00ns INFO     test                               RegWrite, addr=0x4008 data=0xbeed1390
  4346.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00004008 prot: 2 data: 90 13 ed be
  4406.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00004008 prot: 2 resp: 0 length: 4
  4406.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00004008 prot: 2 length: 4
  4466.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00004008 prot: 2 resp: 1 data: 10 00 00 00
  4466.00ns INFO     test                               RegRead addr=4008 rdata=0x10
  4466.00ns INFO     test                               Test RW: soc_sdma1_dma0_Ctrl wval beed1390 rv 10 expected 10 actual 10
  4466.00ns INFO     test                               RegWrite, addr=0x4018 data=0x742ca265
  4466.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00004018 prot: 2 data: 65 a2 2c 74
  4526.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00004018 prot: 2 resp: 0 length: 4
  4526.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00004018 prot: 2 length: 4
  4586.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00004018 prot: 2 resp: 1 data: 65 a2 2c 74
  4586.00ns INFO     test                               RegRead addr=4018 rdata=0x742ca265
  4586.00ns INFO     test                               Test RW: soc_sdma1_dma0_Dest_Address wval 742ca265 rv 742ca265 expected 742ca265 actual 742ca265
  4586.00ns INFO     test                               RegWrite, addr=0x4024 data=0x96a1df8
  4586.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00004024 prot: 2 data: f8 1d 6a 09
  4646.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00004024 prot: 2 resp: 0 length: 4
  4646.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00004024 prot: 2 length: 4
  4706.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00004024 prot: 2 resp: 1 data: 00 00 00 00
  4706.00ns INFO     test                               RegRead addr=4024 rdata=0x0
  4706.00ns INFO     test                               Test RW: soc_sdma1_dma0_Interrupt wval 96a1df8 rv 0 expected 0 actual 0
  4706.00ns INFO     test                               RegWrite, addr=0x4028 data=0xb8ff004f
  4706.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00004028 prot: 2 data: 4f 00 ff b8
  4766.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00004028 prot: 2 resp: 0 length: 4
  4766.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00004028 prot: 2 length: 4
  4826.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00004028 prot: 2 resp: 1 data: 07 00 00 00
  4826.00ns INFO     test                               RegRead addr=4028 rdata=0x7
  4826.00ns INFO     test                               Test RW: soc_sdma1_dma0_Interrupt_Mask wval b8ff004f rv 7 expected 7 actual 7
  4826.00ns INFO     test                               RegWrite, addr=0x402c data=0x1f951efd
  4826.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000402c prot: 2 data: fd 1e 95 1f
  4886.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000402c prot: 2 resp: 0 length: 4
  4886.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000402c prot: 2 length: 4
  4946.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000402c prot: 2 resp: 1 data: 05 00 00 00
  4946.00ns INFO     test                               RegRead addr=402c rdata=0x5
  4946.00ns INFO     test                               Test RW: soc_sdma1_dma0_Interrupt_Test wval 1f951efd rv 5 expected 5 actual 5
  4946.00ns INFO     test                               RegWrite, addr=0x401c data=0xa8ae1f04
  4946.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000401c prot: 2 data: 04 1f ae a8
  5006.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000401c prot: 2 resp: 0 length: 4
  5006.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000401c prot: 2 length: 4
  5066.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000401c prot: 2 resp: 1 data: 04 1f ae a8
  5066.00ns INFO     test                               RegRead addr=401c rdata=0xa8ae1f04
  5066.00ns INFO     test                               Test RW: soc_sdma1_dma0_Length wval a8ae1f04 rv a8ae1f04 expected a8ae1f04 actual a8ae1f04
  5066.00ns INFO     test                               RegWrite, addr=0x400c data=0xd1245f11
  5066.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000400c prot: 2 data: 11 5f 24 d1
  5126.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000400c prot: 2 resp: 0 length: 4
  5126.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000400c prot: 2 length: 4
  5186.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000400c prot: 2 resp: 1 data: 00 00 00 00
  5186.00ns INFO     test                               RegRead addr=400c rdata=0x0
  5186.00ns INFO     test                               Test RW: soc_sdma1_dma0_PD_Count wval d1245f11 rv 0 expected 0 actual 0
  5186.00ns INFO     test                               RegWrite, addr=0x4020 data=0xa5e3553d
  5186.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00004020 prot: 2 data: 3d 55 e3 a5
  5246.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00004020 prot: 2 resp: 0 length: 4
  5246.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00004020 prot: 2 length: 4
  5306.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00004020 prot: 2 resp: 1 data: 3d 55 e3 a5
  5306.00ns INFO     test                               RegRead addr=4020 rdata=0xa5e3553d
  5306.00ns INFO     test                               Test RW: soc_sdma1_dma0_PacketDescriptor_Address wval a5e3553d rv a5e3553d expected a5e3553d actual a5e3553d
  5306.00ns INFO     test                               RegWrite, addr=0x4014 data=0x1ab4aa42
  5306.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00004014 prot: 2 data: 42 aa b4 1a
  5366.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00004014 prot: 2 resp: 0 length: 4
  5366.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00004014 prot: 2 length: 4
  5426.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00004014 prot: 2 resp: 1 data: 42 aa b4 1a
  5426.00ns INFO     test                               RegRead addr=4014 rdata=0x1ab4aa42
  5426.00ns INFO     test                               Test RW: soc_sdma1_dma0_Src_Address wval 1ab4aa42 rv 1ab4aa42 expected 1ab4aa42 actual 1ab4aa42
  5426.00ns INFO     test                               RegWrite, addr=0x4004 data=0x2afe7a19
  5426.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00004004 prot: 2 data: 19 7a fe 2a
  5486.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00004004 prot: 2 resp: 0 length: 4
  5486.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00004004 prot: 2 length: 4
  5546.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00004004 prot: 2 resp: 1 data: 00 00 00 00
  5546.00ns INFO     test                               RegRead addr=4004 rdata=0x0
  5546.00ns INFO     test                               Test RW: soc_sdma1_dma0_Status wval 2afe7a19 rv 0 expected 0 actual 0
  5546.00ns INFO     test                               RegWrite, addr=0x5010 data=0x202c769c
  5546.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00005010 prot: 2 data: 9c 76 2c 20
  5606.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00005010 prot: 2 resp: 0 length: 4
  5606.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00005010 prot: 2 length: 4
  5666.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00005010 prot: 2 resp: 1 data: 9c 76 0c 00
  5666.00ns INFO     test                               RegRead addr=5010 rdata=0xc769c
  5666.00ns INFO     test                               Test RW: soc_sdma1_dma1_Cfg wval 202c769c rv c769c expected c769c actual c769c
  5666.00ns INFO     test                               RegWrite, addr=0x5008 data=0x1249920c
  5666.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00005008 prot: 2 data: 0c 92 49 12
  5726.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00005008 prot: 2 resp: 0 length: 4
  5726.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00005008 prot: 2 length: 4
  5786.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00005008 prot: 2 resp: 1 data: 0c 00 00 00
  5786.00ns INFO     test                               RegRead addr=5008 rdata=0xc
  5786.00ns INFO     test                               Test RW: soc_sdma1_dma1_Ctrl wval 1249920c rv c expected c actual c
  5786.00ns INFO     test                               RegWrite, addr=0x5018 data=0xdc57760c
  5786.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00005018 prot: 2 data: 0c 76 57 dc
  5846.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00005018 prot: 2 resp: 0 length: 4
  5846.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00005018 prot: 2 length: 4
  5906.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00005018 prot: 2 resp: 1 data: 0c 76 57 dc
  5906.00ns INFO     test                               RegRead addr=5018 rdata=0xdc57760c
  5906.00ns INFO     test                               Test RW: soc_sdma1_dma1_Dest_Address wval dc57760c rv dc57760c expected dc57760c actual dc57760c
  5906.00ns INFO     test                               RegWrite, addr=0x5024 data=0xa7300b98
  5906.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00005024 prot: 2 data: 98 0b 30 a7
  5966.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00005024 prot: 2 resp: 0 length: 4
  5966.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00005024 prot: 2 length: 4
  6026.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00005024 prot: 2 resp: 1 data: 00 00 00 00
  6026.00ns INFO     test                               RegRead addr=5024 rdata=0x0
  6026.00ns INFO     test                               Test RW: soc_sdma1_dma1_Interrupt wval a7300b98 rv 0 expected 0 actual 0
  6026.00ns INFO     test                               RegWrite, addr=0x5028 data=0x3a9696f4
  6026.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00005028 prot: 2 data: f4 96 96 3a
  6086.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00005028 prot: 2 resp: 0 length: 4
  6086.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00005028 prot: 2 length: 4
  6146.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00005028 prot: 2 resp: 1 data: 04 00 00 00
  6146.00ns INFO     test                               RegRead addr=5028 rdata=0x4
  6146.00ns INFO     test                               Test RW: soc_sdma1_dma1_Interrupt_Mask wval 3a9696f4 rv 4 expected 4 actual 4
  6146.00ns INFO     test                               RegWrite, addr=0x502c data=0xbff6c509
  6146.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000502c prot: 2 data: 09 c5 f6 bf
  6206.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000502c prot: 2 resp: 0 length: 4
  6206.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000502c prot: 2 length: 4
  6266.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000502c prot: 2 resp: 1 data: 01 00 00 00
  6266.00ns INFO     test                               RegRead addr=502c rdata=0x1
  6266.00ns INFO     test                               Test RW: soc_sdma1_dma1_Interrupt_Test wval bff6c509 rv 1 expected 1 actual 1
  6266.00ns INFO     test                               RegWrite, addr=0x501c data=0xf9a1ffd3
  6266.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000501c prot: 2 data: d3 ff a1 f9
  6326.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000501c prot: 2 resp: 0 length: 4
  6326.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000501c prot: 2 length: 4
  6386.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000501c prot: 2 resp: 1 data: d3 ff a1 f9
  6386.00ns INFO     test                               RegRead addr=501c rdata=0xf9a1ffd3
  6386.00ns INFO     test                               Test RW: soc_sdma1_dma1_Length wval f9a1ffd3 rv f9a1ffd3 expected f9a1ffd3 actual f9a1ffd3
  6386.00ns INFO     test                               RegWrite, addr=0x500c data=0x98cad13e
  6386.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000500c prot: 2 data: 3e d1 ca 98
  6446.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000500c prot: 2 resp: 0 length: 4
  6446.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000500c prot: 2 length: 4
  6506.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000500c prot: 2 resp: 1 data: 00 00 00 00
  6506.00ns INFO     test                               RegRead addr=500c rdata=0x0
  6506.00ns INFO     test                               Test RW: soc_sdma1_dma1_PD_Count wval 98cad13e rv 0 expected 0 actual 0
  6506.00ns INFO     test                               RegWrite, addr=0x5020 data=0x5bb2196d
  6506.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00005020 prot: 2 data: 6d 19 b2 5b
  6566.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00005020 prot: 2 resp: 0 length: 4
  6566.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00005020 prot: 2 length: 4
  6626.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00005020 prot: 2 resp: 1 data: 6d 19 b2 5b
  6626.00ns INFO     test                               RegRead addr=5020 rdata=0x5bb2196d
  6626.00ns INFO     test                               Test RW: soc_sdma1_dma1_PacketDescriptor_Address wval 5bb2196d rv 5bb2196d expected 5bb2196d actual 5bb2196d
  6626.00ns INFO     test                               RegWrite, addr=0x5014 data=0x298414a4
  6626.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00005014 prot: 2 data: a4 14 84 29
  6686.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00005014 prot: 2 resp: 0 length: 4
  6686.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00005014 prot: 2 length: 4
  6746.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00005014 prot: 2 resp: 1 data: a4 14 84 29
  6746.00ns INFO     test                               RegRead addr=5014 rdata=0x298414a4
  6746.00ns INFO     test                               Test RW: soc_sdma1_dma1_Src_Address wval 298414a4 rv 298414a4 expected 298414a4 actual 298414a4
  6746.00ns INFO     test                               RegWrite, addr=0x5004 data=0x6c2ad318
  6746.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00005004 prot: 2 data: 18 d3 2a 6c
  6806.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00005004 prot: 2 resp: 0 length: 4
  6806.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00005004 prot: 2 length: 4
  6866.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00005004 prot: 2 resp: 1 data: 00 00 00 00
  6866.00ns INFO     test                               RegRead addr=5004 rdata=0x0
  6866.00ns INFO     test                               Test RW: soc_sdma1_dma1_Status wval 6c2ad318 rv 0 expected 0 actual 0
  6866.00ns INFO     test                               RegWrite, addr=0x6010 data=0xe5b32e49
  6866.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00006010 prot: 2 data: 49 2e b3 e5
  6926.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00006010 prot: 2 resp: 0 length: 4
  6926.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00006010 prot: 2 length: 4
  6986.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00006010 prot: 2 resp: 1 data: 49 2e 03 00
  6986.00ns INFO     test                               RegRead addr=6010 rdata=0x32e49
  6986.00ns INFO     test                               Test RW: soc_sdma1_dma2_Cfg wval e5b32e49 rv 32e49 expected 32e49 actual 32e49
  6986.00ns INFO     test                               RegWrite, addr=0x6008 data=0xb08a5cac
  6986.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00006008 prot: 2 data: ac 5c 8a b0
  7046.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00006008 prot: 2 resp: 0 length: 4
  7046.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00006008 prot: 2 length: 4
  7106.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00006008 prot: 2 resp: 1 data: 2c 00 00 00
  7106.00ns INFO     test                               RegRead addr=6008 rdata=0x2c
  7106.00ns INFO     test                               Test RW: soc_sdma1_dma2_Ctrl wval b08a5cac rv 2c expected 2c actual 2c
  7106.00ns INFO     test                               RegWrite, addr=0x6018 data=0xd9443a2e
  7106.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00006018 prot: 2 data: 2e 3a 44 d9
  7166.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00006018 prot: 2 resp: 0 length: 4
  7166.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00006018 prot: 2 length: 4
  7226.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00006018 prot: 2 resp: 1 data: 2e 3a 44 d9
  7226.00ns INFO     test                               RegRead addr=6018 rdata=0xd9443a2e
  7226.00ns INFO     test                               Test RW: soc_sdma1_dma2_Dest_Address wval d9443a2e rv d9443a2e expected d9443a2e actual d9443a2e
  7226.00ns INFO     test                               RegWrite, addr=0x6024 data=0x7b37dfe0
  7226.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00006024 prot: 2 data: e0 df 37 7b
  7286.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00006024 prot: 2 resp: 0 length: 4
  7286.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00006024 prot: 2 length: 4
  7346.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00006024 prot: 2 resp: 1 data: 00 00 00 00
  7346.00ns INFO     test                               RegRead addr=6024 rdata=0x0
  7346.00ns INFO     test                               Test RW: soc_sdma1_dma2_Interrupt wval 7b37dfe0 rv 0 expected 0 actual 0
  7346.00ns INFO     test                               RegWrite, addr=0x6028 data=0x1a1eac19
  7346.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00006028 prot: 2 data: 19 ac 1e 1a
  7406.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00006028 prot: 2 resp: 0 length: 4
  7406.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00006028 prot: 2 length: 4
  7466.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00006028 prot: 2 resp: 1 data: 01 00 00 00
  7466.00ns INFO     test                               RegRead addr=6028 rdata=0x1
  7466.00ns INFO     test                               Test RW: soc_sdma1_dma2_Interrupt_Mask wval 1a1eac19 rv 1 expected 1 actual 1
  7466.00ns INFO     test                               RegWrite, addr=0x602c data=0xde646a29
  7466.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000602c prot: 2 data: 29 6a 64 de
  7526.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000602c prot: 2 resp: 0 length: 4
  7526.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000602c prot: 2 length: 4
  7586.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000602c prot: 2 resp: 1 data: 01 00 00 00
  7586.00ns INFO     test                               RegRead addr=602c rdata=0x1
  7586.00ns INFO     test                               Test RW: soc_sdma1_dma2_Interrupt_Test wval de646a29 rv 1 expected 1 actual 1
  7586.00ns INFO     test                               RegWrite, addr=0x601c data=0x1641209b
  7586.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000601c prot: 2 data: 9b 20 41 16
  7646.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000601c prot: 2 resp: 0 length: 4
  7646.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000601c prot: 2 length: 4
  7706.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000601c prot: 2 resp: 1 data: 9b 20 41 16
  7706.00ns INFO     test                               RegRead addr=601c rdata=0x1641209b
  7706.00ns INFO     test                               Test RW: soc_sdma1_dma2_Length wval 1641209b rv 1641209b expected 1641209b actual 1641209b
  7706.00ns INFO     test                               RegWrite, addr=0x600c data=0xe7a6fead
  7706.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000600c prot: 2 data: ad fe a6 e7
  7766.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000600c prot: 2 resp: 0 length: 4
  7766.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000600c prot: 2 length: 4
  7826.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000600c prot: 2 resp: 1 data: 00 00 00 00
  7826.00ns INFO     test                               RegRead addr=600c rdata=0x0
  7826.00ns INFO     test                               Test RW: soc_sdma1_dma2_PD_Count wval e7a6fead rv 0 expected 0 actual 0
  7826.00ns INFO     test                               RegWrite, addr=0x6020 data=0x417be3f9
  7826.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00006020 prot: 2 data: f9 e3 7b 41
  7886.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00006020 prot: 2 resp: 0 length: 4
  7886.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00006020 prot: 2 length: 4
  7946.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00006020 prot: 2 resp: 1 data: f9 e3 7b 41
  7946.00ns INFO     test                               RegRead addr=6020 rdata=0x417be3f9
  7946.00ns INFO     test                               Test RW: soc_sdma1_dma2_PacketDescriptor_Address wval 417be3f9 rv 417be3f9 expected 417be3f9 actual 417be3f9
  7946.00ns INFO     test                               RegWrite, addr=0x6014 data=0x80fe447f
  7946.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00006014 prot: 2 data: 7f 44 fe 80
  8006.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00006014 prot: 2 resp: 0 length: 4
  8006.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00006014 prot: 2 length: 4
  8066.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00006014 prot: 2 resp: 1 data: 7f 44 fe 80
  8066.00ns INFO     test                               RegRead addr=6014 rdata=0x80fe447f
  8066.00ns INFO     test                               Test RW: soc_sdma1_dma2_Src_Address wval 80fe447f rv 80fe447f expected 80fe447f actual 80fe447f
  8066.00ns INFO     test                               RegWrite, addr=0x6004 data=0x59830809
  8066.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00006004 prot: 2 data: 09 08 83 59
  8126.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00006004 prot: 2 resp: 0 length: 4
  8126.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00006004 prot: 2 length: 4
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00006004 prot: 2 resp: 1 data: 00 00 00 00
  8186.00ns INFO     test                               RegRead addr=6004 rdata=0x0
  8186.00ns INFO     test                               Test RW: soc_sdma1_dma2_Status wval 59830809 rv 0 expected 0 actual 0
  8186.00ns INFO     cocotb.regression                  cocotbtest_soc.test_ral_fgwr_fgrd passed
  8186.00ns INFO     cocotb.regression                  running cocotbtest_soc.test_ral_fgwr_bgrd (3/4)
                                                            Ral test foreground write background read.
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master (write)
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4             cocotbext-axi version 0.1.26
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4             Copyright (c) 2020-2025 Alex Forencich
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4             https://github.com/alexforencich/cocotbext-axi
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master configuration:
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               Address width: 32 bits
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               Byte size: 8 bits
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               Data width: 32 bits (4 bytes)
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master signals:
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               awaddr width: 32 bits
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               awprot width: 3 bits
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               awready width: 1 bits
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               awvalid width: 1 bits
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               wdata width: 32 bits
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               wready width: 1 bits
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               wstrb width: 4 bits
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               wvalid width: 1 bits
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               bready width: 1 bits
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               bresp width: 2 bits
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               bvalid width: 1 bits
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master (read)
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4             cocotbext-axi version 0.1.26
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4             Copyright (c) 2020-2025 Alex Forencich
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4             https://github.com/alexforencich/cocotbext-axi
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master configuration:
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               Address width: 32 bits
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               Byte size: 8 bits
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               Data width: 32 bits (4 bytes)
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master signals:
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               araddr width: 32 bits
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               arprot width: 3 bits
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               arready width: 1 bits
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               arvalid width: 1 bits
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               rdata width: 32 bits
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               rready width: 1 bits
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               rresp width: 2 bits
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4               rvalid width: 1 bits
  8186.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
  8186.00ns INFO     test                               
                                                                Cocotb RALGEN: SystemRDL to RALtest converter.
                                                                Copyright © 2024 Dyumnin Semiconductors.
                                                                https://dyumnin.com
                                                                
  8187.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
  8187.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
  8187.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
  8187.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
  8187.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
  8187.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
  8187.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
  8201.00ns INFO     test                               RegWrite, addr=0x10 data=0xd9aeffac
  8336.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
  8336.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
  8336.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
  8336.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
  8336.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
  8336.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
  8336.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
  8336.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00000010 prot: 2 data: ac ff ae d9
  8396.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00000010 prot: 2 resp: 0 length: 4
  8396.00ns INFO     test                               Test RW: soc_sdma0_dma0_Cfg wval d9aeffac rv effac expected effac actual effac
  8396.00ns INFO     test                               RegWrite, addr=0x8 data=0xdd3769dc
  8396.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00000008 prot: 2 data: dc 69 37 dd
  8456.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00000008 prot: 2 resp: 0 length: 4
  8456.00ns INFO     test                               Test RW: soc_sdma0_dma0_Ctrl wval dd3769dc rv 1c expected 1c actual 1c
  8456.00ns INFO     test                               RegWrite, addr=0x18 data=0x8f951be8
  8456.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00000018 prot: 2 data: e8 1b 95 8f
  8516.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00000018 prot: 2 resp: 0 length: 4
  8516.00ns INFO     test                               Test RW: soc_sdma0_dma0_Dest_Address wval 8f951be8 rv 8f951be8 expected 8f951be8 actual 8f951be8
  8516.00ns INFO     test                               RegWrite, addr=0x24 data=0xa2fb5890
  8516.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00000024 prot: 2 data: 90 58 fb a2
  8576.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00000024 prot: 2 resp: 0 length: 4
  8576.00ns INFO     test                               Test RW: soc_sdma0_dma0_Interrupt wval a2fb5890 rv 0 expected 0 actual 0
  8576.00ns INFO     test                               RegWrite, addr=0x28 data=0x7ae30964
  8576.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00000028 prot: 2 data: 64 09 e3 7a
  8636.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00000028 prot: 2 resp: 0 length: 4
  8636.00ns INFO     test                               Test RW: soc_sdma0_dma0_Interrupt_Mask wval 7ae30964 rv 4 expected 4 actual 4
  8636.00ns INFO     test                               RegWrite, addr=0x2c data=0xc736c369
  8636.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000002c prot: 2 data: 69 c3 36 c7
  8696.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000002c prot: 2 resp: 0 length: 4
  8696.00ns INFO     test                               Test RW: soc_sdma0_dma0_Interrupt_Test wval c736c369 rv 1 expected 1 actual 1
  8696.00ns INFO     test                               RegWrite, addr=0x1c data=0x8ce365d4
  8696.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000001c prot: 2 data: d4 65 e3 8c
  8756.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000001c prot: 2 resp: 0 length: 4
  8756.00ns INFO     test                               Test RW: soc_sdma0_dma0_Length wval 8ce365d4 rv 8ce365d4 expected 8ce365d4 actual 8ce365d4
  8756.00ns INFO     test                               RegWrite, addr=0xc data=0x14287426
  8756.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000000c prot: 2 data: 26 74 28 14
  8816.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000000c prot: 2 resp: 0 length: 4
  8816.00ns INFO     test                               Test RW: soc_sdma0_dma0_PD_Count wval 14287426 rv 0 expected 0 actual 0
  8816.00ns INFO     test                               RegWrite, addr=0x20 data=0x712d9268
  8816.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00000020 prot: 2 data: 68 92 2d 71
  8876.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00000020 prot: 2 resp: 0 length: 4
  8876.00ns INFO     test                               Test RW: soc_sdma0_dma0_PacketDescriptor_Address wval 712d9268 rv 712d9268 expected 712d9268 actual 712d9268
  8876.00ns INFO     test                               RegWrite, addr=0x14 data=0xfac8770a
  8876.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00000014 prot: 2 data: 0a 77 c8 fa
  8936.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00000014 prot: 2 resp: 0 length: 4
  8936.00ns INFO     test                               Test RW: soc_sdma0_dma0_Src_Address wval fac8770a rv fac8770a expected fac8770a actual fac8770a
  8936.00ns INFO     test                               RegWrite, addr=0x4 data=0xea0557c1
  8936.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00000004 prot: 2 data: c1 57 05 ea
  8996.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00000004 prot: 2 resp: 0 length: 4
  8996.00ns INFO     test                               Test RW: soc_sdma0_dma0_Status wval ea0557c1 rv 0 expected 0 actual 0
  8996.00ns INFO     test                               RegWrite, addr=0x1010 data=0x1734d3f6
  8996.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00001010 prot: 2 data: f6 d3 34 17
  9056.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00001010 prot: 2 resp: 0 length: 4
  9056.00ns INFO     test                               Test RW: soc_sdma0_dma1_Cfg wval 1734d3f6 rv 4d3f6 expected 4d3f6 actual 4d3f6
  9056.00ns INFO     test                               RegWrite, addr=0x1008 data=0xcbaac22e
  9056.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00001008 prot: 2 data: 2e c2 aa cb
  9116.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00001008 prot: 2 resp: 0 length: 4
  9116.00ns INFO     test                               Test RW: soc_sdma0_dma1_Ctrl wval cbaac22e rv 2e expected 2e actual 2e
  9116.00ns INFO     test                               RegWrite, addr=0x1018 data=0x2bdc8370
  9116.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00001018 prot: 2 data: 70 83 dc 2b
  9176.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00001018 prot: 2 resp: 0 length: 4
  9176.00ns INFO     test                               Test RW: soc_sdma0_dma1_Dest_Address wval 2bdc8370 rv 2bdc8370 expected 2bdc8370 actual 2bdc8370
  9176.00ns INFO     test                               RegWrite, addr=0x1024 data=0x3c4831d0
  9176.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00001024 prot: 2 data: d0 31 48 3c
  9236.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00001024 prot: 2 resp: 0 length: 4
  9236.00ns INFO     test                               Test RW: soc_sdma0_dma1_Interrupt wval 3c4831d0 rv 0 expected 0 actual 0
  9236.00ns INFO     test                               RegWrite, addr=0x1028 data=0x9d617208
  9236.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00001028 prot: 2 data: 08 72 61 9d
  9296.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00001028 prot: 2 resp: 0 length: 4
  9296.00ns INFO     test                               Test RW: soc_sdma0_dma1_Interrupt_Mask wval 9d617208 rv 0 expected 0 actual 0
  9296.00ns INFO     test                               RegWrite, addr=0x102c data=0xebe64a26
  9296.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000102c prot: 2 data: 26 4a e6 eb
  9356.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000102c prot: 2 resp: 0 length: 4
  9356.00ns INFO     test                               Test RW: soc_sdma0_dma1_Interrupt_Test wval ebe64a26 rv 6 expected 6 actual 6
  9356.00ns INFO     test                               RegWrite, addr=0x101c data=0x58350c6b
  9356.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000101c prot: 2 data: 6b 0c 35 58
  9416.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000101c prot: 2 resp: 0 length: 4
  9416.00ns INFO     test                               Test RW: soc_sdma0_dma1_Length wval 58350c6b rv 58350c6b expected 58350c6b actual 58350c6b
  9416.00ns INFO     test                               RegWrite, addr=0x100c data=0xa4c07458
  9416.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000100c prot: 2 data: 58 74 c0 a4
  9476.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000100c prot: 2 resp: 0 length: 4
  9476.00ns INFO     test                               Test RW: soc_sdma0_dma1_PD_Count wval a4c07458 rv 0 expected 0 actual 0
  9476.00ns INFO     test                               RegWrite, addr=0x1020 data=0x47779290
  9476.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00001020 prot: 2 data: 90 92 77 47
  9536.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00001020 prot: 2 resp: 0 length: 4
  9536.00ns INFO     test                               Test RW: soc_sdma0_dma1_PacketDescriptor_Address wval 47779290 rv 47779290 expected 47779290 actual 47779290
  9536.00ns INFO     test                               RegWrite, addr=0x1014 data=0xe6b75bf4
  9536.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00001014 prot: 2 data: f4 5b b7 e6
  9596.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00001014 prot: 2 resp: 0 length: 4
  9596.00ns INFO     test                               Test RW: soc_sdma0_dma1_Src_Address wval e6b75bf4 rv e6b75bf4 expected e6b75bf4 actual e6b75bf4
  9596.00ns INFO     test                               RegWrite, addr=0x1004 data=0x4eb3b691
  9596.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00001004 prot: 2 data: 91 b6 b3 4e
  9656.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00001004 prot: 2 resp: 0 length: 4
  9656.00ns INFO     test                               Test RW: soc_sdma0_dma1_Status wval 4eb3b691 rv 0 expected 0 actual 0
  9656.00ns INFO     test                               RegWrite, addr=0x2010 data=0x4c3f7c1d
  9656.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00002010 prot: 2 data: 1d 7c 3f 4c
  9716.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00002010 prot: 2 resp: 0 length: 4
  9716.00ns INFO     test                               Test RW: soc_sdma0_dma2_Cfg wval 4c3f7c1d rv f7c1d expected f7c1d actual f7c1d
  9716.00ns INFO     test                               RegWrite, addr=0x2008 data=0x9de47d5c
  9716.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00002008 prot: 2 data: 5c 7d e4 9d
  9776.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00002008 prot: 2 resp: 0 length: 4
  9776.00ns INFO     test                               Test RW: soc_sdma0_dma2_Ctrl wval 9de47d5c rv 1c expected 1c actual 1c
  9776.00ns INFO     test                               RegWrite, addr=0x2018 data=0x762cd07d
  9776.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00002018 prot: 2 data: 7d d0 2c 76
  9836.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00002018 prot: 2 resp: 0 length: 4
  9836.00ns INFO     test                               Test RW: soc_sdma0_dma2_Dest_Address wval 762cd07d rv 762cd07d expected 762cd07d actual 762cd07d
  9836.00ns INFO     test                               RegWrite, addr=0x2024 data=0xcc157458
  9836.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00002024 prot: 2 data: 58 74 15 cc
  9896.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00002024 prot: 2 resp: 0 length: 4
  9896.00ns INFO     test                               Test RW: soc_sdma0_dma2_Interrupt wval cc157458 rv 0 expected 0 actual 0
  9896.00ns INFO     test                               RegWrite, addr=0x2028 data=0x23b04ce1
  9896.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00002028 prot: 2 data: e1 4c b0 23
  9956.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00002028 prot: 2 resp: 0 length: 4
  9956.00ns INFO     test                               Test RW: soc_sdma0_dma2_Interrupt_Mask wval 23b04ce1 rv 1 expected 1 actual 1
  9956.00ns INFO     test                               RegWrite, addr=0x202c data=0xe2b6caa0
  9956.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000202c prot: 2 data: a0 ca b6 e2
 10016.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000202c prot: 2 resp: 0 length: 4
 10016.00ns INFO     test                               Test RW: soc_sdma0_dma2_Interrupt_Test wval e2b6caa0 rv 0 expected 0 actual 0
 10016.00ns INFO     test                               RegWrite, addr=0x201c data=0x7a509040
 10016.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000201c prot: 2 data: 40 90 50 7a
 10076.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000201c prot: 2 resp: 0 length: 4
 10076.00ns INFO     test                               Test RW: soc_sdma0_dma2_Length wval 7a509040 rv 7a509040 expected 7a509040 actual 7a509040
 10076.00ns INFO     test                               RegWrite, addr=0x200c data=0x8efa5efd
 10076.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000200c prot: 2 data: fd 5e fa 8e
 10136.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000200c prot: 2 resp: 0 length: 4
 10136.00ns INFO     test                               Test RW: soc_sdma0_dma2_PD_Count wval 8efa5efd rv 0 expected 0 actual 0
 10136.00ns INFO     test                               RegWrite, addr=0x2020 data=0xf04f0861
 10136.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00002020 prot: 2 data: 61 08 4f f0
 10196.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00002020 prot: 2 resp: 0 length: 4
 10196.00ns INFO     test                               Test RW: soc_sdma0_dma2_PacketDescriptor_Address wval f04f0861 rv f04f0861 expected f04f0861 actual f04f0861
 10196.00ns INFO     test                               RegWrite, addr=0x2014 data=0x127414b5
 10196.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00002014 prot: 2 data: b5 14 74 12
 10256.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00002014 prot: 2 resp: 0 length: 4
 10256.00ns INFO     test                               Test RW: soc_sdma0_dma2_Src_Address wval 127414b5 rv 127414b5 expected 127414b5 actual 127414b5
 10256.00ns INFO     test                               RegWrite, addr=0x2004 data=0x1ce5af79
 10256.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00002004 prot: 2 data: 79 af e5 1c
 10316.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00002004 prot: 2 resp: 0 length: 4
 10316.00ns INFO     test                               Test RW: soc_sdma0_dma2_Status wval 1ce5af79 rv 0 expected 0 actual 0
 10316.00ns INFO     test                               RegWrite, addr=0x4010 data=0xae31ae69
 10316.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00004010 prot: 2 data: 69 ae 31 ae
 10376.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00004010 prot: 2 resp: 0 length: 4
 10376.00ns INFO     test                               Test RW: soc_sdma1_dma0_Cfg wval ae31ae69 rv 1ae69 expected 1ae69 actual 1ae69
 10376.00ns INFO     test                               RegWrite, addr=0x4008 data=0x8bf4dc4a
 10376.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00004008 prot: 2 data: 4a dc f4 8b
 10436.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00004008 prot: 2 resp: 0 length: 4
 10436.00ns INFO     test                               Test RW: soc_sdma1_dma0_Ctrl wval 8bf4dc4a rv a expected a actual a
 10436.00ns INFO     test                               RegWrite, addr=0x4018 data=0xffa3b3a6
 10436.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00004018 prot: 2 data: a6 b3 a3 ff
 10496.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00004018 prot: 2 resp: 0 length: 4
 10496.00ns INFO     test                               Test RW: soc_sdma1_dma0_Dest_Address wval ffa3b3a6 rv ffa3b3a6 expected ffa3b3a6 actual ffa3b3a6
 10496.00ns INFO     test                               RegWrite, addr=0x4024 data=0xffd93bd0
 10496.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00004024 prot: 2 data: d0 3b d9 ff
 10556.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00004024 prot: 2 resp: 0 length: 4
 10556.00ns INFO     test                               Test RW: soc_sdma1_dma0_Interrupt wval ffd93bd0 rv 0 expected 0 actual 0
 10556.00ns INFO     test                               RegWrite, addr=0x4028 data=0x588908e
 10556.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00004028 prot: 2 data: 8e 90 88 05
 10616.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00004028 prot: 2 resp: 0 length: 4
 10616.00ns INFO     test                               Test RW: soc_sdma1_dma0_Interrupt_Mask wval 588908e rv 6 expected 6 actual 6
 10616.00ns INFO     test                               RegWrite, addr=0x402c data=0xe76567b3
 10616.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000402c prot: 2 data: b3 67 65 e7
 10676.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000402c prot: 2 resp: 0 length: 4
 10676.00ns INFO     test                               Test RW: soc_sdma1_dma0_Interrupt_Test wval e76567b3 rv 3 expected 3 actual 3
 10676.00ns INFO     test                               RegWrite, addr=0x401c data=0xd512aa37
 10676.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000401c prot: 2 data: 37 aa 12 d5
 10736.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000401c prot: 2 resp: 0 length: 4
 10736.00ns INFO     test                               Test RW: soc_sdma1_dma0_Length wval d512aa37 rv d512aa37 expected d512aa37 actual d512aa37
 10736.00ns INFO     test                               RegWrite, addr=0x400c data=0xedd668c8
 10736.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000400c prot: 2 data: c8 68 d6 ed
 10796.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000400c prot: 2 resp: 0 length: 4
 10796.00ns INFO     test                               Test RW: soc_sdma1_dma0_PD_Count wval edd668c8 rv 0 expected 0 actual 0
 10796.00ns INFO     test                               RegWrite, addr=0x4020 data=0xf9c2b9ae
 10796.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00004020 prot: 2 data: ae b9 c2 f9
 10856.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00004020 prot: 2 resp: 0 length: 4
 10856.00ns INFO     test                               Test RW: soc_sdma1_dma0_PacketDescriptor_Address wval f9c2b9ae rv f9c2b9ae expected f9c2b9ae actual f9c2b9ae
 10856.00ns INFO     test                               RegWrite, addr=0x4014 data=0xbb4ae78
 10856.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00004014 prot: 2 data: 78 ae b4 0b
 10916.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00004014 prot: 2 resp: 0 length: 4
 10916.00ns INFO     test                               Test RW: soc_sdma1_dma0_Src_Address wval bb4ae78 rv bb4ae78 expected bb4ae78 actual bb4ae78
 10916.00ns INFO     test                               RegWrite, addr=0x4004 data=0x8c147e51
 10916.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00004004 prot: 2 data: 51 7e 14 8c
 10976.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00004004 prot: 2 resp: 0 length: 4
 10976.00ns INFO     test                               Test RW: soc_sdma1_dma0_Status wval 8c147e51 rv 0 expected 0 actual 0
 10976.00ns INFO     test                               RegWrite, addr=0x5010 data=0x20df5e4b
 10976.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00005010 prot: 2 data: 4b 5e df 20
 11036.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00005010 prot: 2 resp: 0 length: 4
 11036.00ns INFO     test                               Test RW: soc_sdma1_dma1_Cfg wval 20df5e4b rv f5e4b expected f5e4b actual f5e4b
 11036.00ns INFO     test                               RegWrite, addr=0x5008 data=0xc6f6376c
 11036.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00005008 prot: 2 data: 6c 37 f6 c6
 11096.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00005008 prot: 2 resp: 0 length: 4
 11096.00ns INFO     test                               Test RW: soc_sdma1_dma1_Ctrl wval c6f6376c rv 2c expected 2c actual 2c
 11096.00ns INFO     test                               RegWrite, addr=0x5018 data=0x29c11d8d
 11096.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00005018 prot: 2 data: 8d 1d c1 29
 11156.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00005018 prot: 2 resp: 0 length: 4
 11156.00ns INFO     test                               Test RW: soc_sdma1_dma1_Dest_Address wval 29c11d8d rv 29c11d8d expected 29c11d8d actual 29c11d8d
 11156.00ns INFO     test                               RegWrite, addr=0x5024 data=0x79ce9038
 11156.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00005024 prot: 2 data: 38 90 ce 79
 11216.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00005024 prot: 2 resp: 0 length: 4
 11216.00ns INFO     test                               Test RW: soc_sdma1_dma1_Interrupt wval 79ce9038 rv 0 expected 0 actual 0
 11216.00ns INFO     test                               RegWrite, addr=0x5028 data=0xa0a76eb4
 11216.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00005028 prot: 2 data: b4 6e a7 a0
 11276.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00005028 prot: 2 resp: 0 length: 4
 11276.00ns INFO     test                               Test RW: soc_sdma1_dma1_Interrupt_Mask wval a0a76eb4 rv 4 expected 4 actual 4
 11276.00ns INFO     test                               RegWrite, addr=0x502c data=0x2cc747d2
 11276.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000502c prot: 2 data: d2 47 c7 2c
 11336.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000502c prot: 2 resp: 0 length: 4
 11336.00ns INFO     test                               Test RW: soc_sdma1_dma1_Interrupt_Test wval 2cc747d2 rv 2 expected 2 actual 2
 11336.00ns INFO     test                               RegWrite, addr=0x501c data=0x60fc3252
 11336.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000501c prot: 2 data: 52 32 fc 60
 11396.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000501c prot: 2 resp: 0 length: 4
 11396.00ns INFO     test                               Test RW: soc_sdma1_dma1_Length wval 60fc3252 rv 60fc3252 expected 60fc3252 actual 60fc3252
 11396.00ns INFO     test                               RegWrite, addr=0x500c data=0x290ef148
 11396.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000500c prot: 2 data: 48 f1 0e 29
 11456.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000500c prot: 2 resp: 0 length: 4
 11456.00ns INFO     test                               Test RW: soc_sdma1_dma1_PD_Count wval 290ef148 rv 0 expected 0 actual 0
 11456.00ns INFO     test                               RegWrite, addr=0x5020 data=0x2bf2c862
 11456.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00005020 prot: 2 data: 62 c8 f2 2b
 11516.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00005020 prot: 2 resp: 0 length: 4
 11516.00ns INFO     test                               Test RW: soc_sdma1_dma1_PacketDescriptor_Address wval 2bf2c862 rv 2bf2c862 expected 2bf2c862 actual 2bf2c862
 11516.00ns INFO     test                               RegWrite, addr=0x5014 data=0xd53f217c
 11516.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00005014 prot: 2 data: 7c 21 3f d5
 11576.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00005014 prot: 2 resp: 0 length: 4
 11576.00ns INFO     test                               Test RW: soc_sdma1_dma1_Src_Address wval d53f217c rv d53f217c expected d53f217c actual d53f217c
 11576.00ns INFO     test                               RegWrite, addr=0x5004 data=0x9a4dc391
 11576.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00005004 prot: 2 data: 91 c3 4d 9a
 11636.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00005004 prot: 2 resp: 0 length: 4
 11636.00ns INFO     test                               Test RW: soc_sdma1_dma1_Status wval 9a4dc391 rv 0 expected 0 actual 0
 11636.00ns INFO     test                               RegWrite, addr=0x6010 data=0xc8493b42
 11636.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00006010 prot: 2 data: 42 3b 49 c8
 11696.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00006010 prot: 2 resp: 0 length: 4
 11696.00ns INFO     test                               Test RW: soc_sdma1_dma2_Cfg wval c8493b42 rv 93b42 expected 93b42 actual 93b42
 11696.00ns INFO     test                               RegWrite, addr=0x6008 data=0xb67438d4
 11696.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00006008 prot: 2 data: d4 38 74 b6
 11756.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00006008 prot: 2 resp: 0 length: 4
 11756.00ns INFO     test                               Test RW: soc_sdma1_dma2_Ctrl wval b67438d4 rv 14 expected 14 actual 14
 11756.00ns INFO     test                               RegWrite, addr=0x6018 data=0x5ad6e62d
 11756.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00006018 prot: 2 data: 2d e6 d6 5a
 11816.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00006018 prot: 2 resp: 0 length: 4
 11816.00ns INFO     test                               Test RW: soc_sdma1_dma2_Dest_Address wval 5ad6e62d rv 5ad6e62d expected 5ad6e62d actual 5ad6e62d
 11816.00ns INFO     test                               RegWrite, addr=0x6024 data=0xa3c0c160
 11816.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00006024 prot: 2 data: 60 c1 c0 a3
 11876.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00006024 prot: 2 resp: 0 length: 4
 11876.00ns INFO     test                               Test RW: soc_sdma1_dma2_Interrupt wval a3c0c160 rv 0 expected 0 actual 0
 11876.00ns INFO     test                               RegWrite, addr=0x6028 data=0xffe7511b
 11876.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00006028 prot: 2 data: 1b 51 e7 ff
 11936.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00006028 prot: 2 resp: 0 length: 4
 11936.00ns INFO     test                               Test RW: soc_sdma1_dma2_Interrupt_Mask wval ffe7511b rv 3 expected 3 actual 3
 11936.00ns INFO     test                               RegWrite, addr=0x602c data=0x2e34ef02
 11936.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000602c prot: 2 data: 02 ef 34 2e
 11996.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000602c prot: 2 resp: 0 length: 4
 11996.00ns INFO     test                               Test RW: soc_sdma1_dma2_Interrupt_Test wval 2e34ef02 rv 2 expected 2 actual 2
 11996.00ns INFO     test                               RegWrite, addr=0x601c data=0xb1af3d40
 11996.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000601c prot: 2 data: 40 3d af b1
 12056.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000601c prot: 2 resp: 0 length: 4
 12056.00ns INFO     test                               Test RW: soc_sdma1_dma2_Length wval b1af3d40 rv b1af3d40 expected b1af3d40 actual b1af3d40
 12056.00ns INFO     test                               RegWrite, addr=0x600c data=0x63c89d6c
 12056.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x0000600c prot: 2 data: 6c 9d c8 63
 12116.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x0000600c prot: 2 resp: 0 length: 4
 12116.00ns INFO     test                               Test RW: soc_sdma1_dma2_PD_Count wval 63c89d6c rv 0 expected 0 actual 0
 12116.00ns INFO     test                               RegWrite, addr=0x6020 data=0x44f215e0
 12116.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00006020 prot: 2 data: e0 15 f2 44
 12176.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00006020 prot: 2 resp: 0 length: 4
 12176.00ns INFO     test                               Test RW: soc_sdma1_dma2_PacketDescriptor_Address wval 44f215e0 rv 44f215e0 expected 44f215e0 actual 44f215e0
 12176.00ns INFO     test                               RegWrite, addr=0x6014 data=0xf7a488f6
 12176.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00006014 prot: 2 data: f6 88 a4 f7
 12236.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00006014 prot: 2 resp: 0 length: 4
 12236.00ns INFO     test                               Test RW: soc_sdma1_dma2_Src_Address wval f7a488f6 rv f7a488f6 expected f7a488f6 actual f7a488f6
 12236.00ns INFO     test                               RegWrite, addr=0x6004 data=0xb631d549
 12236.00ns INFO     cocotb.mkMDMA.csr_axi4             Write start addr: 0x00006004 prot: 2 data: 49 d5 31 b6
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4             Write complete addr: 0x00006004 prot: 2 resp: 0 length: 4
 12296.00ns INFO     test                               Test RW: soc_sdma1_dma2_Status wval b631d549 rv 0 expected 0 actual 0
 12296.00ns INFO     cocotb.regression                  cocotbtest_soc.test_ral_fgwr_bgrd passed
 12296.00ns INFO     cocotb.regression                  running cocotbtest_soc.test_ral_bgwr_fgrd (4/4)
                                                            Ral test Background wr foreground read.
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master (write)
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4             cocotbext-axi version 0.1.26
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4             Copyright (c) 2020-2025 Alex Forencich
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4             https://github.com/alexforencich/cocotbext-axi
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master configuration:
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               Address width: 32 bits
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               Byte size: 8 bits
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               Data width: 32 bits (4 bytes)
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master signals:
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               awaddr width: 32 bits
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               awprot width: 3 bits
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               awready width: 1 bits
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               awvalid width: 1 bits
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               wdata width: 32 bits
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               wready width: 1 bits
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               wstrb width: 4 bits
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               wvalid width: 1 bits
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               bready width: 1 bits
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               bresp width: 2 bits
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               bvalid width: 1 bits
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master (read)
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4             cocotbext-axi version 0.1.26
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4             Copyright (c) 2020-2025 Alex Forencich
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4             https://github.com/alexforencich/cocotbext-axi
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master configuration:
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               Address width: 32 bits
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               Byte size: 8 bits
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               Data width: 32 bits (4 bytes)
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4             AXI lite master signals:
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               araddr width: 32 bits
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               arprot width: 3 bits
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               arready width: 1 bits
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               arvalid width: 1 bits
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               rdata width: 32 bits
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               rready width: 1 bits
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               rresp width: 2 bits
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4               rvalid width: 1 bits
 12296.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
 12296.00ns INFO     test                               
                                                                Cocotb RALGEN: SystemRDL to RALtest converter.
                                                                Copyright © 2024 Dyumnin Semiconductors.
                                                                https://dyumnin.com
                                                                
 12297.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
 12297.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
 12297.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
 12297.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
 12297.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
 12297.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
 12297.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset asserted
 12446.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
 12446.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
 12446.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
 12446.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
 12446.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
 12446.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
 12446.00ns INFO     cocotb.mkMDMA.csr_axi4             Reset de-asserted
 12446.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00000010 prot: 2 length: 4
 12506.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00000010 prot: 2 resp: 1 data: e2 28 0c 00
 12506.00ns INFO     test                               RegRead addr=10 rdata=0xc28e2
 12506.00ns INFO     test                               Test RW: soc_sdma0_dma0_Cfg wval bc7c28e2 rv c28e2 expected c28e2 actual c28e2
 12506.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00000008 prot: 2 length: 4
 12566.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00000008 prot: 2 resp: 1 data: 2a 00 00 00
 12566.00ns INFO     test                               RegRead addr=8 rdata=0x2a
 12566.00ns INFO     test                               Test RW: soc_sdma0_dma0_Ctrl wval b480742a rv 2a expected 2a actual 2a
 12566.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00000018 prot: 2 length: 4
 12626.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00000018 prot: 2 resp: 1 data: cc f5 96 c2
 12626.00ns INFO     test                               RegRead addr=18 rdata=0xc296f5cc
 12626.00ns INFO     test                               Test RW: soc_sdma0_dma0_Dest_Address wval c296f5cc rv c296f5cc expected c296f5cc actual c296f5cc
 12626.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00000024 prot: 2 length: 4
 12686.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00000024 prot: 2 resp: 1 data: 00 00 00 00
 12686.00ns INFO     test                               RegRead addr=24 rdata=0x0
 12686.00ns INFO     test                               Test RW: soc_sdma0_dma0_Interrupt wval b5c9ed50 rv 0 expected 0 actual 0
 12686.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00000028 prot: 2 length: 4
 12746.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00000028 prot: 2 resp: 1 data: 04 00 00 00
 12746.00ns INFO     test                               RegRead addr=28 rdata=0x4
 12746.00ns INFO     test                               Test RW: soc_sdma0_dma0_Interrupt_Mask wval 4425c944 rv 4 expected 4 actual 4
 12746.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000002c prot: 2 length: 4
 12806.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000002c prot: 2 resp: 1 data: 01 00 00 00
 12806.00ns INFO     test                               RegRead addr=2c rdata=0x1
 12806.00ns INFO     test                               Test RW: soc_sdma0_dma0_Interrupt_Test wval c6833f91 rv 1 expected 1 actual 1
 12806.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000001c prot: 2 length: 4
 12866.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000001c prot: 2 resp: 1 data: ac ef 5a be
 12866.00ns INFO     test                               RegRead addr=1c rdata=0xbe5aefac
 12866.00ns INFO     test                               Test RW: soc_sdma0_dma0_Length wval be5aefac rv be5aefac expected be5aefac actual be5aefac
 12866.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000000c prot: 2 length: 4
 12926.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000000c prot: 2 resp: 1 data: ca 79 00 00
 12926.00ns INFO     test                               RegRead addr=c rdata=0x79ca
 12926.00ns INFO     test                               Test RW: soc_sdma0_dma0_PD_Count wval 32079ca rv 79ca expected 0 actual 0
 12926.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00000020 prot: 2 length: 4
 12986.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00000020 prot: 2 resp: 1 data: 72 d2 ae eb
 12986.00ns INFO     test                               RegRead addr=20 rdata=0xebaed272
 12986.00ns INFO     test                               Test RW: soc_sdma0_dma0_PacketDescriptor_Address wval ebaed272 rv ebaed272 expected ebaed272 actual ebaed272
 12986.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00000014 prot: 2 length: 4
 13046.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00000014 prot: 2 resp: 1 data: c0 25 8d d3
 13046.00ns INFO     test                               RegRead addr=14 rdata=0xd38d25c0
 13046.00ns INFO     test                               Test RW: soc_sdma0_dma0_Src_Address wval d38d25c0 rv d38d25c0 expected d38d25c0 actual d38d25c0
 13046.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00000004 prot: 2 length: 4
 13106.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00000004 prot: 2 resp: 1 data: 00 00 00 00
 13106.00ns INFO     test                               RegRead addr=4 rdata=0x0
 13106.00ns INFO     test                               Test RW: soc_sdma0_dma0_Status wval 25c02ee9 rv 0 expected 0 actual 0
 13106.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00001010 prot: 2 length: 4
 13166.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00001010 prot: 2 resp: 1 data: da ec 0d 00
 13166.00ns INFO     test                               RegRead addr=1010 rdata=0xdecda
 13166.00ns INFO     test                               Test RW: soc_sdma0_dma1_Cfg wval 341decda rv decda expected decda actual decda
 13166.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00001008 prot: 2 length: 4
 13226.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00001008 prot: 2 resp: 1 data: 26 00 00 00
 13226.00ns INFO     test                               RegRead addr=1008 rdata=0x26
 13226.00ns INFO     test                               Test RW: soc_sdma0_dma1_Ctrl wval 87ce5266 rv 26 expected 26 actual 26
 13226.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00001018 prot: 2 length: 4
 13286.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00001018 prot: 2 resp: 1 data: ec 4c 41 05
 13286.00ns INFO     test                               RegRead addr=1018 rdata=0x5414cec
 13286.00ns INFO     test                               Test RW: soc_sdma0_dma1_Dest_Address wval 5414cec rv 5414cec expected 5414cec actual 5414cec
 13286.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00001024 prot: 2 length: 4
 13346.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00001024 prot: 2 resp: 1 data: 00 00 00 00
 13346.00ns INFO     test                               RegRead addr=1024 rdata=0x0
 13346.00ns INFO     test                               Test RW: soc_sdma0_dma1_Interrupt wval 5daafbc0 rv 0 expected 0 actual 0
 13346.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00001028 prot: 2 length: 4
 13406.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00001028 prot: 2 resp: 1 data: 05 00 00 00
 13406.00ns INFO     test                               RegRead addr=1028 rdata=0x5
 13406.00ns INFO     test                               Test RW: soc_sdma0_dma1_Interrupt_Mask wval 35049ff5 rv 5 expected 5 actual 5
 13406.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000102c prot: 2 length: 4
 13466.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000102c prot: 2 resp: 1 data: 02 00 00 00
 13466.00ns INFO     test                               RegRead addr=102c rdata=0x2
 13466.00ns INFO     test                               Test RW: soc_sdma0_dma1_Interrupt_Test wval 31e6a2da rv 2 expected 2 actual 2
 13466.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000101c prot: 2 length: 4
 13526.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000101c prot: 2 resp: 1 data: 47 0a 44 95
 13526.00ns INFO     test                               RegRead addr=101c rdata=0x95440a47
 13526.00ns INFO     test                               Test RW: soc_sdma0_dma1_Length wval 95440a47 rv 95440a47 expected 95440a47 actual 95440a47
 13526.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000100c prot: 2 length: 4
 13586.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000100c prot: 2 resp: 1 data: bd b3 00 00
 13586.00ns INFO     test                               RegRead addr=100c rdata=0xb3bd
 13586.00ns INFO     test                               Test RW: soc_sdma0_dma1_PD_Count wval c13ab3bd rv b3bd expected 0 actual 0
 13586.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00001020 prot: 2 length: 4
 13646.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00001020 prot: 2 resp: 1 data: 0c d0 5c 5d
 13646.00ns INFO     test                               RegRead addr=1020 rdata=0x5d5cd00c
 13646.00ns INFO     test                               Test RW: soc_sdma0_dma1_PacketDescriptor_Address wval 5d5cd00c rv 5d5cd00c expected 5d5cd00c actual 5d5cd00c
 13646.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00001014 prot: 2 length: 4
 13706.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00001014 prot: 2 resp: 1 data: 4b 4f 78 55
 13706.00ns INFO     test                               RegRead addr=1014 rdata=0x55784f4b
 13706.00ns INFO     test                               Test RW: soc_sdma0_dma1_Src_Address wval 55784f4b rv 55784f4b expected 55784f4b actual 55784f4b
 13706.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00001004 prot: 2 length: 4
 13766.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00001004 prot: 2 resp: 1 data: 00 00 00 00
 13766.00ns INFO     test                               RegRead addr=1004 rdata=0x0
 13766.00ns INFO     test                               Test RW: soc_sdma0_dma1_Status wval 6953b1f0 rv 0 expected 0 actual 0
 13766.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00002010 prot: 2 length: 4
 13826.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00002010 prot: 2 resp: 1 data: c6 06 00 00
 13826.00ns INFO     test                               RegRead addr=2010 rdata=0x6c6
 13826.00ns INFO     test                               Test RW: soc_sdma0_dma2_Cfg wval de5006c6 rv 6c6 expected 6c6 actual 6c6
 13826.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00002008 prot: 2 length: 4
 13886.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00002008 prot: 2 resp: 1 data: 10 00 00 00
 13886.00ns INFO     test                               RegRead addr=2008 rdata=0x10
 13886.00ns INFO     test                               Test RW: soc_sdma0_dma2_Ctrl wval e351ba10 rv 10 expected 10 actual 10
 13886.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00002018 prot: 2 length: 4
 13946.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00002018 prot: 2 resp: 1 data: 49 d5 0d 97
 13946.00ns INFO     test                               RegRead addr=2018 rdata=0x970dd549
 13946.00ns INFO     test                               Test RW: soc_sdma0_dma2_Dest_Address wval 970dd549 rv 970dd549 expected 970dd549 actual 970dd549
 13946.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00002024 prot: 2 length: 4
 14006.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00002024 prot: 2 resp: 1 data: 00 00 00 00
 14006.00ns INFO     test                               RegRead addr=2024 rdata=0x0
 14006.00ns INFO     test                               Test RW: soc_sdma0_dma2_Interrupt wval b8db25b8 rv 0 expected 0 actual 0
 14006.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00002028 prot: 2 length: 4
 14066.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00002028 prot: 2 resp: 1 data: 03 00 00 00
 14066.00ns INFO     test                               RegRead addr=2028 rdata=0x3
 14066.00ns INFO     test                               Test RW: soc_sdma0_dma2_Interrupt_Mask wval b4bd382b rv 3 expected 3 actual 3
 14066.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000202c prot: 2 length: 4
 14126.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000202c prot: 2 resp: 1 data: 03 00 00 00
 14126.00ns INFO     test                               RegRead addr=202c rdata=0x3
 14126.00ns INFO     test                               Test RW: soc_sdma0_dma2_Interrupt_Test wval e30b19b3 rv 3 expected 3 actual 3
 14126.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000201c prot: 2 length: 4
 14186.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000201c prot: 2 resp: 1 data: 1f 38 96 85
 14186.00ns INFO     test                               RegRead addr=201c rdata=0x8596381f
 14186.00ns INFO     test                               Test RW: soc_sdma0_dma2_Length wval 8596381f rv 8596381f expected 8596381f actual 8596381f
 14186.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000200c prot: 2 length: 4
 14246.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000200c prot: 2 resp: 1 data: d8 ce 00 00
 14246.00ns INFO     test                               RegRead addr=200c rdata=0xced8
 14246.00ns INFO     test                               Test RW: soc_sdma0_dma2_PD_Count wval 478aced8 rv ced8 expected 0 actual 0
 14246.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00002020 prot: 2 length: 4
 14306.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00002020 prot: 2 resp: 1 data: 3e 57 e3 e2
 14306.00ns INFO     test                               RegRead addr=2020 rdata=0xe2e3573e
 14306.00ns INFO     test                               Test RW: soc_sdma0_dma2_PacketDescriptor_Address wval e2e3573e rv e2e3573e expected e2e3573e actual e2e3573e
 14306.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00002014 prot: 2 length: 4
 14366.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00002014 prot: 2 resp: 1 data: b4 6b ae 6b
 14366.00ns INFO     test                               RegRead addr=2014 rdata=0x6bae6bb4
 14366.00ns INFO     test                               Test RW: soc_sdma0_dma2_Src_Address wval 6bae6bb4 rv 6bae6bb4 expected 6bae6bb4 actual 6bae6bb4
 14366.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00002004 prot: 2 length: 4
 14426.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00002004 prot: 2 resp: 1 data: 00 00 00 00
 14426.00ns INFO     test                               RegRead addr=2004 rdata=0x0
 14426.00ns INFO     test                               Test RW: soc_sdma0_dma2_Status wval 5abe8e00 rv 0 expected 0 actual 0
 14426.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00004010 prot: 2 length: 4
 14486.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00004010 prot: 2 resp: 1 data: e3 19 0a 00
 14486.00ns INFO     test                               RegRead addr=4010 rdata=0xa19e3
 14486.00ns INFO     test                               Test RW: soc_sdma1_dma0_Cfg wval 5d1a19e3 rv a19e3 expected a19e3 actual a19e3
 14486.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00004008 prot: 2 length: 4
 14546.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00004008 prot: 2 resp: 1 data: 36 00 00 00
 14546.00ns INFO     test                               RegRead addr=4008 rdata=0x36
 14546.00ns INFO     test                               Test RW: soc_sdma1_dma0_Ctrl wval 24dae4b6 rv 36 expected 36 actual 36
 14546.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00004018 prot: 2 length: 4
 14606.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00004018 prot: 2 resp: 1 data: 56 bd a2 91
 14606.00ns INFO     test                               RegRead addr=4018 rdata=0x91a2bd56
 14606.00ns INFO     test                               Test RW: soc_sdma1_dma0_Dest_Address wval 91a2bd56 rv 91a2bd56 expected 91a2bd56 actual 91a2bd56
 14606.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00004024 prot: 2 length: 4
 14666.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00004024 prot: 2 resp: 1 data: 00 00 00 00
 14666.00ns INFO     test                               RegRead addr=4024 rdata=0x0
 14666.00ns INFO     test                               Test RW: soc_sdma1_dma0_Interrupt wval 3547230 rv 0 expected 0 actual 0
 14666.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00004028 prot: 2 length: 4
 14726.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00004028 prot: 2 resp: 1 data: 03 00 00 00
 14726.00ns INFO     test                               RegRead addr=4028 rdata=0x3
 14726.00ns INFO     test                               Test RW: soc_sdma1_dma0_Interrupt_Mask wval de61139b rv 3 expected 3 actual 3
 14726.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000402c prot: 2 length: 4
 14786.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000402c prot: 2 resp: 1 data: 00 00 00 00
 14786.00ns INFO     test                               RegRead addr=402c rdata=0x0
 14786.00ns INFO     test                               Test RW: soc_sdma1_dma0_Interrupt_Test wval dd544980 rv 0 expected 0 actual 0
 14786.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000401c prot: 2 length: 4
 14846.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000401c prot: 2 resp: 1 data: 2f 01 a4 5e
 14846.00ns INFO     test                               RegRead addr=401c rdata=0x5ea4012f
 14846.00ns INFO     test                               Test RW: soc_sdma1_dma0_Length wval 5ea4012f rv 5ea4012f expected 5ea4012f actual 5ea4012f
 14846.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000400c prot: 2 length: 4
 14906.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000400c prot: 2 resp: 1 data: 44 ff 00 00
 14906.00ns INFO     test                               RegRead addr=400c rdata=0xff44
 14906.00ns INFO     test                               Test RW: soc_sdma1_dma0_PD_Count wval e938ff44 rv ff44 expected 0 actual 0
 14906.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00004020 prot: 2 length: 4
 14966.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00004020 prot: 2 resp: 1 data: a3 c9 0a 3d
 14966.00ns INFO     test                               RegRead addr=4020 rdata=0x3d0ac9a3
 14966.00ns INFO     test                               Test RW: soc_sdma1_dma0_PacketDescriptor_Address wval 3d0ac9a3 rv 3d0ac9a3 expected 3d0ac9a3 actual 3d0ac9a3
 14966.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00004014 prot: 2 length: 4
 15026.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00004014 prot: 2 resp: 1 data: 5d fb 72 62
 15026.00ns INFO     test                               RegRead addr=4014 rdata=0x6272fb5d
 15026.00ns INFO     test                               Test RW: soc_sdma1_dma0_Src_Address wval 6272fb5d rv 6272fb5d expected 6272fb5d actual 6272fb5d
 15026.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00004004 prot: 2 length: 4
 15086.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00004004 prot: 2 resp: 1 data: 00 00 00 00
 15086.00ns INFO     test                               RegRead addr=4004 rdata=0x0
 15086.00ns INFO     test                               Test RW: soc_sdma1_dma0_Status wval 8da3a199 rv 0 expected 0 actual 0
 15086.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00005010 prot: 2 length: 4
 15146.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00005010 prot: 2 resp: 1 data: 32 b3 0f 00
 15146.00ns INFO     test                               RegRead addr=5010 rdata=0xfb332
 15146.00ns INFO     test                               Test RW: soc_sdma1_dma1_Cfg wval 48bfb332 rv fb332 expected fb332 actual fb332
 15146.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00005008 prot: 2 length: 4
 15206.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00005008 prot: 2 resp: 1 data: 04 00 00 00
 15206.00ns INFO     test                               RegRead addr=5008 rdata=0x4
 15206.00ns INFO     test                               Test RW: soc_sdma1_dma1_Ctrl wval aa6e1544 rv 4 expected 4 actual 4
 15206.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00005018 prot: 2 length: 4
 15266.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00005018 prot: 2 resp: 1 data: df 9f ee 06
 15266.00ns INFO     test                               RegRead addr=5018 rdata=0x6ee9fdf
 15266.00ns INFO     test                               Test RW: soc_sdma1_dma1_Dest_Address wval 6ee9fdf rv 6ee9fdf expected 6ee9fdf actual 6ee9fdf
 15266.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00005024 prot: 2 length: 4
 15326.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00005024 prot: 2 resp: 1 data: 00 00 00 00
 15326.00ns INFO     test                               RegRead addr=5024 rdata=0x0
 15326.00ns INFO     test                               Test RW: soc_sdma1_dma1_Interrupt wval edce0680 rv 0 expected 0 actual 0
 15326.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00005028 prot: 2 length: 4
 15386.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00005028 prot: 2 resp: 1 data: 01 00 00 00
 15386.00ns INFO     test                               RegRead addr=5028 rdata=0x1
 15386.00ns INFO     test                               Test RW: soc_sdma1_dma1_Interrupt_Mask wval b9f6871 rv 1 expected 1 actual 1
 15386.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000502c prot: 2 length: 4
 15446.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000502c prot: 2 resp: 1 data: 03 00 00 00
 15446.00ns INFO     test                               RegRead addr=502c rdata=0x3
 15446.00ns INFO     test                               Test RW: soc_sdma1_dma1_Interrupt_Test wval fc58d833 rv 3 expected 3 actual 3
 15446.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000501c prot: 2 length: 4
 15506.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000501c prot: 2 resp: 1 data: e5 f3 4d df
 15506.00ns INFO     test                               RegRead addr=501c rdata=0xdf4df3e5
 15506.00ns INFO     test                               Test RW: soc_sdma1_dma1_Length wval df4df3e5 rv df4df3e5 expected df4df3e5 actual df4df3e5
 15506.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000500c prot: 2 length: 4
 15566.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000500c prot: 2 resp: 1 data: c9 0f 00 00
 15566.00ns INFO     test                               RegRead addr=500c rdata=0xfc9
 15566.00ns INFO     test                               Test RW: soc_sdma1_dma1_PD_Count wval b1840fc9 rv fc9 expected 0 actual 0
 15566.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00005020 prot: 2 length: 4
 15626.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00005020 prot: 2 resp: 1 data: 2b 18 87 ed
 15626.00ns INFO     test                               RegRead addr=5020 rdata=0xed87182b
 15626.00ns INFO     test                               Test RW: soc_sdma1_dma1_PacketDescriptor_Address wval ed87182b rv ed87182b expected ed87182b actual ed87182b
 15626.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00005014 prot: 2 length: 4
 15686.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00005014 prot: 2 resp: 1 data: f1 af f3 1a
 15686.00ns INFO     test                               RegRead addr=5014 rdata=0x1af3aff1
 15686.00ns INFO     test                               Test RW: soc_sdma1_dma1_Src_Address wval 1af3aff1 rv 1af3aff1 expected 1af3aff1 actual 1af3aff1
 15686.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00005004 prot: 2 length: 4
 15746.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00005004 prot: 2 resp: 1 data: 00 00 00 00
 15746.00ns INFO     test                               RegRead addr=5004 rdata=0x0
 15746.00ns INFO     test                               Test RW: soc_sdma1_dma1_Status wval a0d54068 rv 0 expected 0 actual 0
 15746.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00006010 prot: 2 length: 4
 15806.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00006010 prot: 2 resp: 1 data: 4b 80 05 00
 15806.00ns INFO     test                               RegRead addr=6010 rdata=0x5804b
 15806.00ns INFO     test                               Test RW: soc_sdma1_dma2_Cfg wval 8615804b rv 5804b expected 5804b actual 5804b
 15806.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00006008 prot: 2 length: 4
 15866.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00006008 prot: 2 resp: 1 data: 36 00 00 00
 15866.00ns INFO     test                               RegRead addr=6008 rdata=0x36
 15866.00ns INFO     test                               Test RW: soc_sdma1_dma2_Ctrl wval 58419af6 rv 36 expected 36 actual 36
 15866.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00006018 prot: 2 length: 4
 15926.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00006018 prot: 2 resp: 1 data: 5f 16 46 ce
 15926.00ns INFO     test                               RegRead addr=6018 rdata=0xce46165f
 15926.00ns INFO     test                               Test RW: soc_sdma1_dma2_Dest_Address wval ce46165f rv ce46165f expected ce46165f actual ce46165f
 15926.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00006024 prot: 2 length: 4
 15986.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00006024 prot: 2 resp: 1 data: 00 00 00 00
 15986.00ns INFO     test                               RegRead addr=6024 rdata=0x0
 15986.00ns INFO     test                               Test RW: soc_sdma1_dma2_Interrupt wval ca581480 rv 0 expected 0 actual 0
 15986.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00006028 prot: 2 length: 4
 16046.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00006028 prot: 2 resp: 1 data: 00 00 00 00
 16046.00ns INFO     test                               RegRead addr=6028 rdata=0x0
 16046.00ns INFO     test                               Test RW: soc_sdma1_dma2_Interrupt_Mask wval bc74dc88 rv 0 expected 0 actual 0
 16046.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000602c prot: 2 length: 4
 16106.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000602c prot: 2 resp: 1 data: 00 00 00 00
 16106.00ns INFO     test                               RegRead addr=602c rdata=0x0
 16106.00ns INFO     test                               Test RW: soc_sdma1_dma2_Interrupt_Test wval 61040b28 rv 0 expected 0 actual 0
 16106.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000601c prot: 2 length: 4
 16166.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000601c prot: 2 resp: 1 data: 1f 4b 3e 32
 16166.00ns INFO     test                               RegRead addr=601c rdata=0x323e4b1f
 16166.00ns INFO     test                               Test RW: soc_sdma1_dma2_Length wval 323e4b1f rv 323e4b1f expected 323e4b1f actual 323e4b1f
 16166.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x0000600c prot: 2 length: 4
 16226.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x0000600c prot: 2 resp: 1 data: 57 97 00 00
 16226.00ns INFO     test                               RegRead addr=600c rdata=0x9757
 16226.00ns INFO     test                               Test RW: soc_sdma1_dma2_PD_Count wval cbc09757 rv 9757 expected 0 actual 0
 16226.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00006020 prot: 2 length: 4
 16286.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00006020 prot: 2 resp: 1 data: f3 f6 5f 4f
 16286.00ns INFO     test                               RegRead addr=6020 rdata=0x4f5ff6f3
 16286.00ns INFO     test                               Test RW: soc_sdma1_dma2_PacketDescriptor_Address wval 4f5ff6f3 rv 4f5ff6f3 expected 4f5ff6f3 actual 4f5ff6f3
 16286.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00006014 prot: 2 length: 4
 16346.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00006014 prot: 2 resp: 1 data: 83 c8 23 fe
 16346.00ns INFO     test                               RegRead addr=6014 rdata=0xfe23c883
 16346.00ns INFO     test                               Test RW: soc_sdma1_dma2_Src_Address wval fe23c883 rv fe23c883 expected fe23c883 actual fe23c883
 16346.00ns INFO     cocotb.mkMDMA.csr_axi4             Read start addr: 0x00006004 prot: 2 length: 4
 16406.00ns INFO     cocotb.mkMDMA.csr_axi4             Read complete addr: 0x00006004 prot: 2 resp: 1 data: 00 00 00 00
 16406.00ns INFO     test                               RegRead addr=6004 rdata=0x0
 16406.00ns INFO     test                               Test RW: soc_sdma1_dma2_Status wval 52468de8 rv 0 expected 0 actual 0
 16406.00ns INFO     cocotb.regression                  cocotbtest_soc.test_ral_bgwr_fgrd passed
 16406.00ns INFO     cocotb.regression                  *******************************************************************************************
                                                        ** TEST                               STATUS  SIM TIME (ns)  REAL TIME (s)  RATIO (ns/s) **
                                                        *******************************************************************************************
                                                        ** cocotbtest_soc.test_ral_reset       FAIL         111.00           0.03       4010.16  **
                                                        ** cocotbtest_soc.test_ral_fgwr_fgrd   PASS        8075.00           0.65      12427.47  **
                                                        ** cocotbtest_soc.test_ral_fgwr_bgrd   PASS        4110.00           0.34      12211.17  **
                                                        ** cocotbtest_soc.test_ral_bgwr_fgrd   PASS        4110.00           0.33      12444.86  **
                                                        *******************************************************************************************
                                                        ** TESTS=4 PASS=3 FAIL=1 SKIP=0                   16406.00           1.35      12125.07  **
                                                        *******************************************************************************************
FST info: dumpfile sim_build/mkMDMA.fst opened for output.
26: AXI4_Lite_Fabric.rl_reset
26: AXI4_Lite_Fabric.rl_reset
26: AXI4_Lite_Fabric.rl_reset
833: AXI4_Lite_Fabric.rl_reset
833: AXI4_Lite_Fabric.rl_reset
833: AXI4_Lite_Fabric.rl_reset
1244: AXI4_Lite_Fabric.rl_reset
1244: AXI4_Lite_Fabric.rl_reset
1244: AXI4_Lite_Fabric.rl_reset
make[1]: Leaving directory '/prj/dyumnin_projects/peakrdl/ralgen/tests'
