Metadata-Version: 2.4
Name: khdl
Version: 0.1.0
Classifier: Development Status :: 2 - Pre-Alpha
Classifier: Programming Language :: Rust
Classifier: Programming Language :: Python :: Implementation :: CPython
Classifier: Programming Language :: Python :: 3
Classifier: Programming Language :: Python :: 3 :: Only
Classifier: Programming Language :: Python :: 3.10
Classifier: Programming Language :: Python :: 3.11
Classifier: Programming Language :: Python :: 3.12
Classifier: Programming Language :: Python :: 3.13
Classifier: Programming Language :: Python :: 3.14
Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
Classifier: Typing :: Typed
License-File: LICENCE.txt
Summary: Python bindings for KHDL, an experimental new language for hardware design.
Keywords: hardware,hdl,fpga,verilog,compiler
Home-Page: https://khdl-lang.org/
Author: Karel Peeters
License-Expression: MIT
Requires-Python: >=3.10
Description-Content-Type: text/markdown; charset=UTF-8; variant=GFM
Project-URL: Homepage, https://khdl-lang.org/
Project-URL: Issues, https://github.com/khdl-lang/khdl/issues
Project-URL: Repository, https://github.com/khdl-lang/khdl

# khdl

Python bindings for [KHDL](https://github.com/khdl-lang/khdl), an experimental new language for hardware design.
A webdemo of the language is available at https://khdl-lang.org/.

The bindings expose the compiler to Python, which allows parsing and compiling KHDL projects, calling functions,
instantiating modules, generating Verilog and simulating modules through [Verilator](https://www.veripool.org/verilator/).

```python
import khdl

source = khdl.Source.new_from_manifest_path("path/to/khdl.toml")
compiled = source.parse().compile()

top = compiled.resolve_module("top.top")
print(top.as_verilog().source)
```

Simulation through Verilator requires `verilator`, `make` and a C++ compiler to be available on the `PATH`.

See the [main repository](https://github.com/khdl-lang/khdl) for more information about the language itself.

