pcb-svg

Usage

altium-cruncher pcb-svg board.PcbDoc --views top,bottom,layers -o output/pcb-svg
altium-cruncher pcb-svg project.PrjPcb --config pcb.svg.config

Arguments

file accepts .PcbDoc or .PrjPcb. The command uses pcb.svg.config by default, or a file passed with --config. --views filters configured view names plus layers, all, or none. --layers filters individual layer outputs without changing composed view definitions.

A0 Config

The default file is pcb.svg.config and the root schema is pcb.svg.config.a0. User config files may use JSONC comments and trailing commas; checked-in contract examples remain strict JSON. global.canvas controls SVG viewBox normalization. The default board_outline mode fits the visual canvas to the board profile plus margin_mm; all_geometry keeps the legacy all-primitive bounds. Component metadata remains in source Altium mils and includes origin-relative fields for placement consumers. layer_outputs controls generated per-layer SVG files. views[] is explicit: each view names its output SVG pattern, durable group_id, mirror setting, per-view style overrides, assembly_hlr_mode, and a draw-ordered layers array. Synthetic layer names include BOARD_OUTLINE, BOARD_CUTOUTS, DRILLS, SLOTS, ASSEMBLY_HLR_TOP, ASSEMBLY_HLR_BOTTOM, ASSEMBLY_DESIGNATORS_TOP, ASSEMBLY_DESIGNATORS_BOTTOM, PIN1_TOP, and PIN1_BOTTOM.

Draw Order

The configured layers array is the view draw order, with two enforced exceptions: HLR projection renders last, and DRILLS/SLOTS render immediately before HLR. Copper internals render tracks/arcs first, then vias, polygon/region/fill copper, pads, and finally the synthetic drill/slot groups.

Styles

Global styles live under global.styles and each view can override any style object. Copper can style traces/arcs, vias, polygon copper, SMD pads, and through-hole pads independently. Silkscreen can separately enable component graphics, component designators, and board-level graphics/text. drills and slots are separate style buckets with plated and non-plated colors.

Assembly HLR

Status: initial A0 implementation. Views opt into HLR by including ASSEMBLY_HLR_TOP or ASSEMBLY_HLR_BOTTOM. Each view chooses assembly_hlr_mode as simple, detail, bounding_box, or none. Component overrides can set components.<designator>.projection to the same mode names, including suppressing a part with none or forcing a pad-bounds rectangle with bounding_box. The default config includes top and bottom HLR bounding-box views. The bounding_box mode uses component-owned pad geometry and does not invoke Geometer. The simple and detail modes use Geometer STEP projection when a component has an embedded model, then fall back to component pad bounds when no STEP projection can be emitted.

Projection styling is controlled by global.styles.assembly_hlr with optional per-view overrides and per-component components.<designator>.assembly_hlr overrides. Per-component settings merge over the active view style, so individual parts can force a different color, line width, curve policy, or Geometer tolerance without changing the rest of the view. Supported pass-through settings include color, line_width_mm, projection_algorithm, curve_mode, samples_per_curve, round_digits, include_visible, include_outline, union_polygons, mesh_linear_deflection, mesh_angular_deflection, mesh_relative, hlr_angle_tolerance, and Geometer edge flags such as edge_v_sharp or edge_h_outline.

Virtual Assembly Layers

Status: PIN1_TOP and PIN1_BOTTOM have an initial A0 implementation. The default config includes top and bottom pin-1 inspection views over copper and board outline with simple HLR outlines on top. Pin-1 markers use a dot for normal SMD pad 1, whole-pad highlighting for through-hole pads while preserving visible drill/slot openings, and whole-pad highlighting for BGA/LGA letter-number pads. Pin-1 selection uses a manual components.<designator>.pin1_pad override first, then pad 1, then A1, then letter-number pads sorted by smallest numeric column and smallest row label so packages without A1, such as Cricket Node U5, resolve to B1. Global pin1.exclude_designator_prefixes suppresses markers by alphabetic reference-designator prefix, such as R, C, and L; a component override with pin1_enabled=true re-enables a specific component after the global exclusion. Components with only one owned pad designator are not highlighted because they have no meaningful pin-1 distinction, and free pads are ignored because they are not component-owned. Planned designator layers ASSEMBLY_DESIGNATORS_TOP and ASSEMBLY_DESIGNATORS_BOTTOM are reserved for labels linked to component projection bounds with stable per-component group ids and are not implemented in A0.

Component Overrides

The generated JSONC config includes comments listing discovered designators and component side when the selected PcbDoc can be inspected. The A0 parser accepts optional assembly, dnp, diodes, and components sections; default generated JSON omits those no-op sections until a user adds overrides. Initial A0 rendering uses component overrides for HLR projection mode/style and pin-1 selection/enabling. DNP visual behavior, diode line art, cathode-specific markers, and designator display overrides are planned but not implemented.

Diodes

Status: planned, not implemented as rendered diode overlays in A0. The config and generated comments can identify candidate diodes for later override work. Planned behavior: detection first checks designator prefixes such as D or LED, then case-insensitive component parameter text such as value, description, and comment for diode terms. Explicit pad names such as K or C identify the cathode; numeric 1/2 footprints use a global default mapping with per-component overrides. Two-pin diodes should draw configurable diode line art plus a cathode marker by default; three-pin and four-pin diodes should fall back to standard pin-1 marking unless overridden.

Metadata

Status: initial A0 metadata exists for SVG canvas, view, layer, and component placement fields. Richer SVG metadata is planned but not implemented. The planned richer payload should reuse the existing AltiumDesign.to_json() serialization whenever project context is available. SVG-specific metadata should layer on generated view ids, group ids, canvas transform, source-to-SVG coordinate policy, projection decisions, diode decisions, DNP state, and virtual-layer decisions instead of creating a parallel project/component/netlist schema.

Board Cutouts

BOARD_CUTOUTS renders board-profile interior cutouts with configurable hatch spacing, hatch angle, hatch line width, solid or dashed outline, and outline width. A0 intentionally omits generated cutout text labels so SVGs stay geometry-focused.

Durable Groups

Every composed view is wrapped in a durable <g> using the configured group_id. When the target SVG already exists, the command replaces that group and preserves other user-authored SVG content in the file.

Output

The command writes per-layer SVGs under the configured layer output directory, composed view SVGs at each view's output_svg pattern, and a pcb.svg.manifest.a0 sidecar manifest.

Tests

L3 verifies Hydroscope layer output, geometer-backed HLR assembly views, and the cutout fixture. Unit tests cover schema rejection, default config generation, CLI view/layer selection, style merge behavior, cutout style validation, pin-1 overlay rendering, and HLR bounding-box mode without constructing the Geometer-backed HLR renderer.