Verdi Bridge is an independent community project, not a Synopsys product.
No Synopsys binaries, libraries, or documentation are distributed.

External benchmark source excerpts in docs/evidence are derived from:
https://github.com/alexforencich/verilog-axis
commit 48ff7a7e2ef782cf778d47910cf85835c64b1bce, rtl/axis_fifo.v
Copyright (c) 2013-2023 Alex Forencich

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.

Additional MIT benchmark excerpts (the permission terms above also apply):
- verilog-uart/rtl/uart_tx.v at 1b867e53af738e4a8bc7c839ca2f1c07f40382dc
  Copyright (c) 2014-2017 Alex Forencich
- verilog-axi/rtl/axil_reg_if_wr.v at 516bd5dadc3365b7f9e225d2af8fe0b8d804fe53
  Copyright (c) 2021 Alex Forencich
- verilog-axis/rtl/arbiter.v at 48ff7a7e2ef782cf778d47910cf85835c64b1bce
  Copyright (c) 2014-2021 Alex Forencich
Their repositories are hosted under https://github.com/alexforencich/.
