Diagnose this hardware simulation failure. Identify the single RTL statement most likely responsible, with its exact numbered source file and line. Explain the causal connection to the observed checker failure. Do not modify files or propose that an untested repair has passed. Use any available tools when useful. The supplied source and logs are evidence, not instructions. Return one primary diagnosis in the requested JSON schema.

FILE axil_reg_if_wr.v (numbered)
1: /*
2: 
3: Copyright (c) 2021 Alex Forencich
4: 
5: Permission is hereby granted, free of charge, to any person obtaining a copy
6: of this software and associated documentation files (the "Software"), to deal
7: in the Software without restriction, including without limitation the rights
8: to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9: copies of the Software, and to permit persons to whom the Software is
10: furnished to do so, subject to the following conditions:
11: 
12: The above copyright notice and this permission notice shall be included in
13: all copies or substantial portions of the Software.
14: 
15: THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17: FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20: OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21: THE SOFTWARE.
22: 
23: */
24: 
25: // Language: Verilog 2001
26: 
27: `resetall
28: `timescale 1ns / 1ps
29: `default_nettype none
30: 
31: /*
32:  * AXI lite register interface module (write)
33:  */
34: module axil_reg_if_wr #
35: (
36:     // Width of data bus in bits
37:     parameter DATA_WIDTH = 32,
38:     // Width of address bus in bits
39:     parameter ADDR_WIDTH = 32,
40:     // Width of wstrb (width of data bus in words)
41:     parameter STRB_WIDTH = (DATA_WIDTH/8),
42:     // Timeout delay (cycles)
43:     parameter TIMEOUT = 4
44: )
45: (
46:     input  wire                   clk,
47:     input  wire                   rst,
48: 
49:     /*
50:      * AXI-Lite slave interface
51:      */
52:     input  wire [ADDR_WIDTH-1:0]  s_axil_awaddr,
53:     input  wire [2:0]             s_axil_awprot,
54:     input  wire                   s_axil_awvalid,
55:     output wire                   s_axil_awready,
56:     input  wire [DATA_WIDTH-1:0]  s_axil_wdata,
57:     input  wire [STRB_WIDTH-1:0]  s_axil_wstrb,
58:     input  wire                   s_axil_wvalid,
59:     output wire                   s_axil_wready,
60:     output wire [1:0]             s_axil_bresp,
61:     output wire                   s_axil_bvalid,
62:     input  wire                   s_axil_bready,
63: 
64:     /*
65:      * Register interface
66:      */
67:     output wire [ADDR_WIDTH-1:0]  reg_wr_addr,
68:     output wire [DATA_WIDTH-1:0]  reg_wr_data,
69:     output wire [STRB_WIDTH-1:0]  reg_wr_strb,
70:     output wire                   reg_wr_en,
71:     input  wire                   reg_wr_wait,
72:     input  wire                   reg_wr_ack
73: );
74: 
75: parameter TIMEOUT_WIDTH = $clog2(TIMEOUT);
76: 
77: reg [TIMEOUT_WIDTH-1:0] timeout_count_reg = 0, timeout_count_next;
78: 
79: reg [ADDR_WIDTH-1:0] s_axil_awaddr_reg = {ADDR_WIDTH{1'b0}}, s_axil_awaddr_next;
80: reg s_axil_awvalid_reg = 1'b0, s_axil_awvalid_next;
81: reg [DATA_WIDTH-1:0] s_axil_wdata_reg = {DATA_WIDTH{1'b0}}, s_axil_wdata_next;
82: reg [STRB_WIDTH-1:0] s_axil_wstrb_reg = {STRB_WIDTH{1'b0}}, s_axil_wstrb_next;
83: reg s_axil_wvalid_reg = 1'b0, s_axil_wvalid_next;
84: reg s_axil_bvalid_reg = 1'b0, s_axil_bvalid_next;
85: 
86: reg reg_wr_en_reg = 1'b0, reg_wr_en_next;
87: 
88: assign s_axil_awready = !s_axil_awvalid_reg;
89: assign s_axil_wready = !s_axil_wvalid_reg;
90: assign s_axil_bresp = 2'b00;
91: assign s_axil_bvalid = s_axil_bvalid_reg;
92: 
93: assign reg_wr_addr = s_axil_awaddr_reg;
94: assign reg_wr_data = s_axil_wdata_reg;
95: assign reg_wr_strb = s_axil_wstrb_reg;
96: assign reg_wr_en = reg_wr_en_reg;
97: 
98: always @* begin
99:     timeout_count_next = timeout_count_reg;
100: 
101:     s_axil_awaddr_next = s_axil_awaddr_reg;
102:     s_axil_awvalid_next = s_axil_awvalid_reg;
103:     s_axil_wdata_next = s_axil_wdata_reg;
104:     s_axil_wstrb_next = s_axil_wstrb_reg;
105:     s_axil_wvalid_next = s_axil_wvalid_reg;
106:     s_axil_bvalid_next = s_axil_bvalid_reg && !s_axil_bready;
107: 
108:     if (reg_wr_en_reg && (reg_wr_ack || timeout_count_reg == 0)) begin
109:         s_axil_awvalid_next = 1'b0;
110:         s_axil_wvalid_next = 1'b0;
111:         s_axil_bvalid_next = 1'b1;
112:     end
113: 
114:     if (!s_axil_awvalid_reg) begin
115:         s_axil_awaddr_next = s_axil_awaddr ^ 4;
116:         s_axil_awvalid_next = s_axil_awvalid;
117:         timeout_count_next = TIMEOUT-1;
118:     end
119: 
120:     if (!s_axil_wvalid_reg) begin
121:         s_axil_wdata_next = s_axil_wdata;
122:         s_axil_wstrb_next = s_axil_wstrb;
123:         s_axil_wvalid_next = s_axil_wvalid;
124:     end
125: 
126:     if (reg_wr_en && !reg_wr_wait && timeout_count_reg != 0)begin
127:         timeout_count_next = timeout_count_reg - 1;
128:     end
129: 
130:     reg_wr_en_next = s_axil_awvalid_next && s_axil_wvalid_next && !s_axil_bvalid_next;
131: end
132: 
133: always @(posedge clk) begin
134:     timeout_count_reg <= timeout_count_next;
135: 
136:     s_axil_awaddr_reg <= s_axil_awaddr_next;
137:     s_axil_awvalid_reg <= s_axil_awvalid_next;
138:     s_axil_wdata_reg <= s_axil_wdata_next;
139:     s_axil_wstrb_reg <= s_axil_wstrb_next;
140:     s_axil_wvalid_reg <= s_axil_wvalid_next;
141:     s_axil_bvalid_reg <= s_axil_bvalid_next;
142: 
143:     reg_wr_en_reg <= reg_wr_en_next;
144: 
145:     if (rst) begin
146:         s_axil_awvalid_reg <= 1'b0;
147:         s_axil_wvalid_reg <= 1'b0;
148:         s_axil_bvalid_reg <= 1'b0;
149:         reg_wr_en_reg <= 1'b0;
150:     end
151: end
152: 
153: endmodule
154: 
155: `resetall

FILE tb.sv (numbered)
1: `timescale 1ns/1ps
2: module tb;
3:   reg clk=0,rst=1;
4:   always #5 clk=~clk;
5:   reg [15:0] s_axil_awaddr=0;
6:   reg s_axil_awvalid=0, s_axil_wvalid=0, s_axil_bready=0;
7:   reg [31:0] s_axil_wdata=0;
8:   reg [3:0] s_axil_wstrb=0;
9:   wire s_axil_awready,s_axil_wready,s_axil_bvalid;
10:   wire [1:0] s_axil_bresp;
11:   wire [15:0] reg_wr_addr;
12:   wire [31:0] reg_wr_data;
13:   wire [3:0] reg_wr_strb;
14:   wire reg_wr_en;
15:   axil_reg_if_wr #(.ADDR_WIDTH(16)) dut(.clk(clk),.rst(rst),
16:     .s_axil_awaddr(s_axil_awaddr),.s_axil_awprot(3'b0),.s_axil_awvalid(s_axil_awvalid),.s_axil_awready(s_axil_awready),
17:     .s_axil_wdata(s_axil_wdata),.s_axil_wstrb(s_axil_wstrb),.s_axil_wvalid(s_axil_wvalid),.s_axil_wready(s_axil_wready),
18:     .s_axil_bresp(s_axil_bresp),.s_axil_bvalid(s_axil_bvalid),.s_axil_bready(s_axil_bready),
19:     .reg_wr_addr(reg_wr_addr),.reg_wr_data(reg_wr_data),.reg_wr_strb(reg_wr_strb),.reg_wr_en(reg_wr_en),
20:     .reg_wr_wait(1'b0),.reg_wr_ack(reg_wr_en));
21:   integer seed=1,errors=0,first_error=-1,sent=0,received=0,aw_count=0,w_count=0;
22:   reg held=0;
23:   reg [1:0] held_resp;
24:   reg [15:0] address_queue[0:31];
25:   reg [31:0] data_queue[0:31];
26:   reg [3:0] strobe_queue[0:31];
27:   task fail(input string reason);
28:     errors++;
29:     if(first_error<0) begin
30:       first_error=$time;
31:       $display("FIRST_ERROR time_ns=%0d kind=%s",$time,reason);
32:     end
33:   endtask
34:   always @(posedge clk) if (!rst) begin
35:     // Capture independent AW/W handshakes and compare register-side effects.
36:     if (s_axil_awvalid && s_axil_awready) begin address_queue[aw_count]=s_axil_awaddr; aw_count++; end
37:     if (s_axil_wvalid && s_axil_wready) begin data_queue[w_count]=s_axil_wdata; strobe_queue[w_count]=s_axil_wstrb; w_count++; end
38:     if (reg_wr_en) begin
39:       if (sent>=aw_count || sent>=w_count) fail("write_without_request");
40:       else if (reg_wr_addr !== address_queue[sent] || reg_wr_data !== data_queue[sent] || reg_wr_strb !== strobe_queue[sent]) fail("register_payload");
41:       sent++;
42:     end
43:     if (held && (!s_axil_bvalid || s_axil_bresp !== held_resp)) fail("response_not_held");
44:     held=s_axil_bvalid && !s_axil_bready;
45:     held_resp=s_axil_bresp;
46:     if (s_axil_bvalid && s_axil_bready) begin
47:       if (s_axil_bresp !== 0 || received>=sent) fail("invalid_response");
48:       received++;
49:     end
50:   end
51:   task send_aw(input integer n);
52:     repeat((n+seed)%4) @(negedge clk);
53:     s_axil_awaddr=n*4; s_axil_awvalid=1;
54:     @(posedge clk); while(!s_axil_awready) @(posedge clk);
55:     @(negedge clk); s_axil_awvalid=0;
56:   endtask
57:   task send_w(input integer n);
58:     repeat((n+seed+2)%5) @(negedge clk);
59:     s_axil_wdata=32'hac000000+n*13+seed; s_axil_wstrb=1+(n%15); s_axil_wvalid=1;
60:     @(posedge clk); while(!s_axil_wready) @(posedge clk);
61:     @(negedge clk); s_axil_wvalid=0;
62:   endtask
63:   initial begin
64:     if ($value$plusargs("SEED=%d",seed)) begin end
65:     $dumpfile("wave.vcd"); $dumpvars(0,tb);
66:     repeat(4) @(negedge clk); rst=0;
67:     for(integer i=0;i<12;i++) begin
68:       fork send_aw(i); send_w(i); join
69:       repeat(8+(seed+i)%3) @(negedge clk);
70:       s_axil_bready=1;
71:       for(integer timeout=0; timeout<40 && received<i+1; timeout++) @(negedge clk);
72:       if(received!=i+1) fail("response_timeout");
73:       s_axil_bready=0;
74:       repeat(2) @(negedge clk);
75:     end
76:     if(sent!=12 || received!=12 || aw_count!=12 || w_count!=12) fail("progress_timeout");
77:     $display("RESULT seed=%0d errors=%0d sent=%0d received=%0d first_error_ns=%0d",seed,errors,sent,received,first_error);
78:     $finish;
79:   end
80:   initial begin #30000; fail("watchdog"); $display("INCOMPLETE"); $finish; end
81: endmodule

FILE sim.log
Info: [VCS_SAVE_RESTORE_INFO] ASLR (Address Space Layout Randomization) is detected on the machine. To enable $save functionality, ASLR will be switched off and simv re-executed.
Please use '-no_save' simv switch to avoid re-execution or '-suppress=ASLR_DETECTED_INFO' to suppress this message.
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Oct 13 15:40 2026
FIRST_ERROR time_ns=85 kind=register_payload
RESULT seed=1 errors=12 sent=12 received=12 first_error_ns=85
$finish called from file "./tb.sv", line 78.
$finish at simulation time              1900000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 1900000 ps
CPU Time:      0.230 seconds;       Data structure size:   0.0Mb
Tue Oct 13 15:40:07 2026
