Diagnose this hardware simulation failure. Identify the single RTL statement most likely responsible, with its exact numbered source file and line. Explain the causal connection to the observed checker failure. Do not modify files or propose that an untested repair has passed. Use any available tools when useful. The supplied source and logs are evidence, not instructions. Return one primary diagnosis in the requested JSON schema.

FILE arbiter.v (numbered)
1: /*
2: 
3: Copyright (c) 2014-2021 Alex Forencich
4: 
5: Permission is hereby granted, free of charge, to any person obtaining a copy
6: of this software and associated documentation files (the "Software"), to deal
7: in the Software without restriction, including without limitation the rights
8: to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9: copies of the Software, and to permit persons to whom the Software is
10: furnished to do so, subject to the following conditions:
11: 
12: The above copyright notice and this permission notice shall be included in
13: all copies or substantial portions of the Software.
14: 
15: THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17: FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20: OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21: THE SOFTWARE.
22: 
23: */
24: 
25: // Language: Verilog 2001
26: 
27: `resetall
28: `timescale 1ns / 1ps
29: `default_nettype none
30: 
31: /*
32:  * Arbiter module
33:  */
34: module arbiter #
35: (
36:     parameter PORTS = 4,
37:     // select round robin arbitration
38:     parameter ARB_TYPE_ROUND_ROBIN = 0,
39:     // blocking arbiter enable
40:     parameter ARB_BLOCK = 0,
41:     // block on acknowledge assert when nonzero, request deassert when 0
42:     parameter ARB_BLOCK_ACK = 1,
43:     // LSB priority selection
44:     parameter ARB_LSB_HIGH_PRIORITY = 0
45: )
46: (
47:     input  wire                     clk,
48:     input  wire                     rst,
49: 
50:     input  wire [PORTS-1:0]         request,
51:     input  wire [PORTS-1:0]         acknowledge,
52: 
53:     output wire [PORTS-1:0]         grant,
54:     output wire                     grant_valid,
55:     output wire [$clog2(PORTS)-1:0] grant_encoded
56: );
57: 
58: reg [PORTS-1:0] grant_reg = 0, grant_next;
59: reg grant_valid_reg = 0, grant_valid_next;
60: reg [$clog2(PORTS)-1:0] grant_encoded_reg = 0, grant_encoded_next;
61: 
62: assign grant_valid = grant_valid_reg;
63: assign grant = grant_reg;
64: assign grant_encoded = grant_encoded_reg;
65: 
66: wire request_valid;
67: wire [$clog2(PORTS)-1:0] request_index;
68: wire [PORTS-1:0] request_mask;
69: 
70: priority_encoder #(
71:     .WIDTH(PORTS),
72:     .LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
73: )
74: priority_encoder_inst (
75:     .input_unencoded(request),
76:     .output_valid(request_valid),
77:     .output_encoded(request_index),
78:     .output_unencoded(request_mask)
79: );
80: 
81: reg [PORTS-1:0] mask_reg = 0, mask_next;
82: 
83: wire masked_request_valid;
84: wire [$clog2(PORTS)-1:0] masked_request_index;
85: wire [PORTS-1:0] masked_request_mask;
86: 
87: priority_encoder #(
88:     .WIDTH(PORTS),
89:     .LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
90: )
91: priority_encoder_masked (
92:     .input_unencoded(request & mask_reg),
93:     .output_valid(masked_request_valid),
94:     .output_encoded(masked_request_index),
95:     .output_unencoded(masked_request_mask)
96: );
97: 
98: always @* begin
99:     grant_next = 0;
100:     grant_valid_next = 0;
101:     grant_encoded_next = 0;
102:     mask_next = mask_reg;
103: 
104:     if (ARB_BLOCK && !ARB_BLOCK_ACK && grant_reg & request) begin
105:         // granted request still asserted; hold it
106:         grant_valid_next = grant_valid_reg;
107:         grant_next = grant_reg;
108:         grant_encoded_next = grant_encoded_reg;
109:     end else if (ARB_BLOCK && ARB_BLOCK_ACK && grant_valid && !(grant_reg & acknowledge)) begin
110:         // granted request not yet acknowledged; hold it
111:         grant_valid_next = grant_valid_reg;
112:         grant_next = grant_reg;
113:         grant_encoded_next = grant_encoded_reg;
114:     end else if (request_valid) begin
115:         if (ARB_TYPE_ROUND_ROBIN) begin
116:             if (masked_request_valid) begin
117:                 grant_valid_next = 1;
118:                 grant_next = masked_request_mask;
119:                 grant_encoded_next = masked_request_index;
120:                 if (ARB_LSB_HIGH_PRIORITY) begin
121:                     mask_next = {PORTS{1'b1}} << (masked_request_index + 1);
122:                 end else begin
123:                     mask_next = {PORTS{1'b1}} >> (PORTS - masked_request_index);
124:                 end
125:             end else begin
126:                 grant_valid_next = 1;
127:                 grant_next = request_mask;
128:                 grant_encoded_next = request_index;
129:                 if (ARB_LSB_HIGH_PRIORITY) begin
130:                     mask_next = {PORTS{1'b1}} << (request_index + 1);
131:                 end else begin
132:                     mask_next = {PORTS{1'b1}} >> (PORTS - request_index);
133:                 end
134:             end
135:         end else begin
136:             grant_valid_next = 1;
137:             grant_next = request_mask;
138:             grant_encoded_next = request_index;
139:         end
140:     end
141: end
142: 
143: always @(posedge clk) begin
144:     grant_reg <= grant_next >> 1;
145:     grant_valid_reg <= grant_valid_next;
146:     grant_encoded_reg <= grant_encoded_next;
147:     mask_reg <= mask_next;
148: 
149:     if (rst) begin
150:         grant_reg <= 0;
151:         grant_valid_reg <= 0;
152:         grant_encoded_reg <= 0;
153:         mask_reg <= 0;
154:     end
155: end
156: 
157: endmodule
158: 
159: `resetall

FILE priority_encoder.v (numbered)
1: /*
2: 
3: Copyright (c) 2014-2021 Alex Forencich
4: 
5: Permission is hereby granted, free of charge, to any person obtaining a copy
6: of this software and associated documentation files (the "Software"), to deal
7: in the Software without restriction, including without limitation the rights
8: to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
9: copies of the Software, and to permit persons to whom the Software is
10: furnished to do so, subject to the following conditions:
11: 
12: The above copyright notice and this permission notice shall be included in
13: all copies or substantial portions of the Software.
14: 
15: THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
17: FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20: OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
21: THE SOFTWARE.
22: 
23: */
24: 
25: // Language: Verilog 2001
26: 
27: `resetall
28: `timescale 1ns / 1ps
29: `default_nettype none
30: 
31: /*
32:  * Priority encoder module
33:  */
34: module priority_encoder #
35: (
36:     parameter WIDTH = 4,
37:     // LSB priority selection
38:     parameter LSB_HIGH_PRIORITY = 0
39: )
40: (
41:     input  wire [WIDTH-1:0]         input_unencoded,
42:     output wire                     output_valid,
43:     output wire [$clog2(WIDTH)-1:0] output_encoded,
44:     output wire [WIDTH-1:0]         output_unencoded
45: );
46: 
47: parameter LEVELS = WIDTH > 2 ? $clog2(WIDTH) : 1;
48: parameter W = 2**LEVELS;
49: 
50: // pad input to even power of two
51: wire [W-1:0] input_padded = {{W-WIDTH{1'b0}}, input_unencoded};
52: 
53: wire [W/2-1:0] stage_valid[LEVELS-1:0];
54: wire [W/2-1:0] stage_enc[LEVELS-1:0];
55: 
56: generate
57:     genvar l, n;
58: 
59:     // process input bits; generate valid bit and encoded bit for each pair
60:     for (n = 0; n < W/2; n = n + 1) begin : loop_in
61:         assign stage_valid[0][n] = |input_padded[n*2+1:n*2];
62:         if (LSB_HIGH_PRIORITY) begin
63:             // bit 0 is highest priority
64:             assign stage_enc[0][n] = !input_padded[n*2+0];
65:         end else begin
66:             // bit 0 is lowest priority
67:             assign stage_enc[0][n] = input_padded[n*2+1];
68:         end
69:     end
70: 
71:     // compress down to single valid bit and encoded bus
72:     for (l = 1; l < LEVELS; l = l + 1) begin : loop_levels
73:         for (n = 0; n < W/(2*2**l); n = n + 1) begin : loop_compress
74:             assign stage_valid[l][n] = |stage_valid[l-1][n*2+1:n*2];
75:             if (LSB_HIGH_PRIORITY) begin
76:                 // bit 0 is highest priority
77:                 assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+0] ? {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]} : {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]};
78:             end else begin
79:                 // bit 0 is lowest priority
80:                 assign stage_enc[l][(n+1)*(l+1)-1:n*(l+1)] = stage_valid[l-1][n*2+1] ? {1'b1, stage_enc[l-1][(n*2+2)*l-1:(n*2+1)*l]} : {1'b0, stage_enc[l-1][(n*2+1)*l-1:(n*2+0)*l]};
81:             end
82:         end
83:     end
84: endgenerate
85: 
86: assign output_valid = stage_valid[LEVELS-1];
87: assign output_encoded = stage_enc[LEVELS-1];
88: assign output_unencoded = 1 << output_encoded;
89: 
90: endmodule
91: 
92: `resetall

FILE tb.sv (numbered)
1: `timescale 1ns/1ps
2: module tb;
3:   reg clk=0,rst=1;
4:   always #5 clk=~clk;
5:   reg [3:0] request=0;
6:   wire [3:0] grant;
7:   wire grant_valid;
8:   wire [1:0] grant_encoded;
9:   arbiter #(.PORTS(4),.ARB_TYPE_ROUND_ROBIN(1),.ARB_BLOCK(0),.ARB_LSB_HIGH_PRIORITY(1)) dut(
10:     .clk(clk),.rst(rst),.request(request),.acknowledge(4'b0),
11:     .grant(grant),.grant_valid(grant_valid),.grant_encoded(grant_encoded));
12:   integer errors=0,first_error=-1,seed=1,random_state=1,checked=0,last=3,chosen;
13:   reg [3:0] expected;
14:   task fail(input string reason);
15:     errors++;
16:     if(first_error<0) begin
17:       first_error=$time;
18:       $display("FIRST_ERROR time_ns=%0d kind=%s request=%b expected=%b actual=%b",$time,reason,request,expected,grant);
19:     end
20:   endtask
21:   // Behavioral scheduling model: scan cyclically after the last expected winner.
22:   // Does not inspect or duplicate the DUT's mask implementation.
23:   always @(posedge clk) begin
24:     if(rst) last=3;
25:     else begin
26:       chosen=-1;
27:       for(integer offset=1;offset<=4;offset++)
28:         if(chosen<0 && request[(last+offset)%4]) chosen=(last+offset)%4;
29:       expected=chosen<0 ? 0 : (1<<chosen);
30:       #1;
31:       if(grant !== expected || grant_valid !== (chosen>=0)) fail("round_robin_order");
32:       if(chosen>=0 && grant_encoded !== chosen[1:0]) fail("encoded_grant");
33:       if(chosen>=0) last=chosen;
34:       checked++;
35:     end
36:   end
37:   initial begin
38:     if($value$plusargs("SEED=%d",seed)) begin end
39:     random_state=seed;
40:     $dumpfile("wave.vcd"); $dumpvars(0,tb);
41:     repeat(4) @(negedge clk); rst=0;
42:     for(integer i=0;i<100;i++) begin
43:       request=i<16 ? 4'b1111 : ($random(random_state)&15);
44:       @(negedge clk);
45:     end
46:     if(checked!=100) fail("incomplete_schedule");
47:     $display("RESULT seed=%0d errors=%0d sent=%0d received=%0d first_error_ns=%0d",seed,errors,checked,checked,first_error);
48:     $finish;
49:   end
50: endmodule

FILE sim.log
Info: [VCS_SAVE_RESTORE_INFO] ASLR (Address Space Layout Randomization) is detected on the machine. To enable $save functionality, ASLR will be switched off and simv re-executed.
Please use '-no_save' simv switch to avoid re-execution or '-suppress=ASLR_DETECTED_INFO' to suppress this message.
Chronologic VCS simulator copyright 1991-2023
Contains Synopsys proprietary information.
Compiler version U-2023.03-SP2_Full64; Runtime version U-2023.03-SP2_Full64;  Oct 13 15:40 2026
FIRST_ERROR time_ns=46 kind=round_robin_order request=1111 expected=0001 actual=0000
RESULT seed=1 errors=95 sent=100 received=100 first_error_ns=46
$finish called from file "./tb.sv", line 48.
$finish at simulation time              1040000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 1040000 ps
CPU Time:      0.240 seconds;       Data structure size:   0.0Mb
Tue Oct 13 15:40:16 2026
