framework,version,device,op_name,kernel_source,bmm_dtype,num_tokens,num_heads,latency
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1,32,0.0048767998814582825
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1,8,0.004687999933958053
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1,4,0.004527999833226204
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1,2,0.004479999840259552
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1,1,0.0044511999934911724
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,2,128,0.006572800129652024
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,2,64,0.004646399989724159
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,2,32,0.004464000090956688
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,2,16,0.004588799923658371
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,2,8,0.004534399881958961
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,2,4,0.004515200108289719
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,2,2,0.004428799822926521
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,2,1,0.004560000076889992
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,4,128,0.00658240020275116
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,4,64,0.005497600138187409
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,4,32,0.0047391999512910845
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,4,16,0.004595199972391129
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,4,8,0.004508800059556961
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,4,4,0.004623999819159508
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1,64,0.00480320006608963
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,4,2,0.004630399867892265
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,8,128,0.006764800101518631
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,4,1,0.004521600157022476
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,8,64,0.005142400041222572
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,8,16,0.00448639988899231
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,8,32,0.004412800073623657
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,8,8,0.0045855998992919925
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,8,4,0.004534399881958961
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,8,2,0.004572800174355507
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,8,1,0.004476799815893173
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,16,128,0.006636799871921539
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,16,64,0.0047807998955249785
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,16,32,0.004479999840259552
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,16,16,0.004476799815893173
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,16,8,0.004556800052523613
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,16,4,0.004726399853825569
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,16,2,0.004681599885225296
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,16,1,0.004556800052523613
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,32,128,0.006585600227117539
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,32,64,0.006505600363016129
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,32,32,0.004620800167322159
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,32,16,0.0044511999934911724
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,32,8,0.004553600028157234
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,32,4,0.005033599957823753
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,32,2,0.0044895999133586885
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,32,1,0.0046016000211238865
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,48,128,0.008755200356245042
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,48,64,0.006553599983453751
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,48,32,0.00451200008392334
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,48,16,0.004524800181388855
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,48,4,0.004579199850559235
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,48,8,0.004495999962091446
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,48,2,0.004428799822926521
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,48,1,0.004492799937725067
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,64,128,0.008140800148248672
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,64,64,0.006467200070619583
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,64,16,0.004569600149989128
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,64,32,0.004646399989724159
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,64,4,0.00445760004222393
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,64,8,0.004588799923658371
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,64,2,0.004447999969124794
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,64,1,0.0044351998716592785
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,80,128,0.007939200103282928
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,80,64,0.006428799778223038
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,80,32,0.005782400071620941
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,80,16,0.004502400010824204
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,80,8,0.0044319998472929
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,80,4,0.004380799829959869
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,80,1,0.004659200087189674
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,80,2,0.004524800181388855
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,96,128,0.008563199639320373
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,96,64,0.006553599983453751
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,96,32,0.005670399963855743
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,96,16,0.004630399867892265
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,96,8,0.004422400146722794
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,96,4,0.004566400125622749
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,96,1,0.004608000069856644
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,96,2,0.004460800066590309
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,128,128,0.008585599809885025
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,128,64,0.006543999910354615
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,128,32,0.006371200084686279
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,128,16,0.004566400125622749
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,128,4,0.004374400153756142
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,128,8,0.005273599922657013
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,128,2,0.004608000069856644
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,128,1,0.004447999969124794
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,160,128,0.008752000331878663
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,160,64,0.00663359984755516
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1,128,0.006956800073385239
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,160,32,0.006441599875688553
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,160,16,0.005753599852323532
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,160,8,0.004758400097489357
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,160,4,0.0044895999133586885
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,160,2,0.004560000076889992
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,160,1,0.004745600000023842
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,192,64,0.008495999872684479
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,192,128,0.01071999967098236
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,192,32,0.006604799628257751
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,192,16,0.0063391998410224915
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,192,8,0.004700800031423568
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,192,2,0.004556800052523613
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,192,4,0.004707200080156326
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,192,1,0.00448639988899231
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,256,128,0.010943999886512757
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,256,64,0.00843520015478134
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,256,32,0.006809599697589874
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,256,16,0.0063391998410224915
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,256,8,0.005894400179386139
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,256,4,0.004748800024390221
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,256,1,0.004390399903059006
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,256,2,0.004995200037956238
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,320,128,0.012943999469280243
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,320,64,0.008876799792051315
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,320,16,0.00628800019621849
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,320,32,0.006585600227117539
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,320,8,0.006329599767923355
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,320,4,0.004732799902558327
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,320,1,0.004476799815893173
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,320,2,0.004707200080156326
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,384,128,0.014662399888038635
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,384,64,0.010547199845314026
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1,16,0.0049727998673915865
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,384,16,0.006752000004053116
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,384,32,0.007823999971151352
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,384,8,0.0061471998691558834
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,384,4,0.006060799956321717
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,384,2,0.004623999819159508
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,384,1,0.004761600121855736
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,512,128,0.01879359930753708
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,512,64,0.012751999497413635
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,512,32,0.008918400108814239
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,512,8,0.006140799820423126
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,512,16,0.006675200164318084
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,512,2,0.004550400003790855
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,512,4,0.005772799998521805
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,512,1,0.0047231998294591905
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,768,128,0.027011200785636902
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,768,64,0.014790399372577668
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,768,32,0.010943999886512757
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,768,16,0.00843840017914772
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,768,8,0.006707199662923813
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,768,4,0.006198399886488915
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,768,2,0.005584000051021576
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,768,1,0.004774399846792221
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1024,128,0.03574079871177673
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1024,64,0.01682240068912506
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1024,32,0.010793600231409073
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1024,16,0.008934400230646133
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1024,8,0.006636799871921539
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1024,4,0.006380800157785416
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1024,1,0.004732799902558327
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1024,2,0.006022400036454201
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1536,64,0.025910401344299318
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1536,32,0.014841599762439728
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1536,128,0.04696640074253082
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1536,16,0.010639999806880952
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1536,8,0.008342400193214417
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1536,4,0.006844799965620041
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1536,2,0.006499200314283371
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,1536,1,0.006355199962854385
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,2048,32,0.01686079949140549
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,2048,128,0.06052799820899964
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,2048,64,0.03310079872608185
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,2048,16,0.01085119992494583
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,2048,8,0.008787199854850769
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,2048,4,0.0065151996910572055
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,2048,2,0.00631679967045784
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,2048,1,0.006233600154519081
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,3072,128,0.0843999981880188
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,3072,32,0.025472000241279602
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,3072,64,0.04534400105476379
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,3072,16,0.014771200716495514
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,3072,8,0.010790400207042694
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,3072,4,0.008620800077915191
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,3072,1,0.006252799928188324
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,3072,2,0.006518399715423584
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,4096,32,0.03313280045986176
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,4096,64,0.06115520000457764
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,4096,128,0.11192320585250855
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,4096,16,0.01682240068912506
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,4096,8,0.010943999886512757
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,4096,4,0.008822400122880936
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,4096,2,0.0065311998128890995
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,4096,1,0.006390400230884552
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,6144,32,0.04593600034713745
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,6144,64,0.08624320030212403
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,6144,128,0.16035200357437135
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,6144,16,0.025900799036026
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,6144,8,0.014697599411010741
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,6144,2,0.008422400057315826
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,6144,1,0.006470400094985962
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,6144,4,0.010835199803113937
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,8192,32,0.062745600938797
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,8192,64,0.11074240207672119
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,8192,16,0.03321279883384705
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,8192,8,0.016899199783802034
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,8192,4,0.010777600109577179
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,8192,128,0.2138592004776001
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,8192,2,0.008511999994516373
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_pre,default,float16,8192,1,0.006803199648857117
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1,128,0.006534399837255478
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1,64,0.00448639988899231
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1,32,0.0064191997051239015
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1,16,0.006335999816656113
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1,8,0.005654399842023849
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1,4,0.004659200087189674
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1,2,0.004543999955058098
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1,1,0.0047775998711586
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,2,128,0.006499200314283371
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,2,64,0.006291200220584869
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,2,32,0.006518399715423584
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,2,16,0.0065151996910572055
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,2,8,0.0064640000462532045
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,2,4,0.004636799916625023
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,2,2,0.004659200087189674
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,2,1,0.004639999940991402
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,4,128,0.006441599875688553
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,4,64,0.006204799935221672
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,4,32,0.006380800157785416
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,4,16,0.0064351998269557955
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,4,8,0.006444799900054932
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,4,4,0.00451200008392334
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,4,2,0.004515200108289719
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,4,1,0.004499199986457825
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,8,128,0.0064800001680850984
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,8,64,0.004467200115323066
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,8,32,0.006297600269317627
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,8,16,0.005711999908089638
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,8,8,0.004515200108289719
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,8,4,0.004403200000524521
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,8,2,0.004614400118589402
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,8,1,0.0045471999794244765
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,16,128,0.006489600241184235
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,16,64,0.0058848001062870026
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,16,32,0.004665600135922432
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,16,16,0.004614400118589402
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,16,8,0.006441599875688553
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,16,4,0.004492799937725067
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,16,2,0.0044895999133586885
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,16,1,0.004729599878191948
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,32,128,0.006611199676990509
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,32,64,0.005321599915623665
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,32,32,0.004556800052523613
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,32,16,0.004479999840259552
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,32,8,0.004614400118589402
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,32,4,0.0057183999568223955
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,32,2,0.004588799923658371
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,32,1,0.004492799937725067
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,48,128,0.006518399715423584
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,48,64,0.006377600133419037
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,48,32,0.005033599957823753
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,48,16,0.00483199991285801
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,48,8,0.00459199994802475
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,48,4,0.004812800139188766
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,48,2,0.0045471999794244765
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,48,1,0.0046847999095916745
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,64,128,0.006656000018119812
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,64,64,0.006425599753856659
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,64,32,0.0060095999389886854
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,64,16,0.005542400106787681
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,64,8,0.0046431999653577805
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,64,4,0.004745600000023842
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,64,2,0.004604800045490265
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,64,1,0.004639999940991402
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,80,128,0.00650240033864975
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,80,64,0.006454399973154068
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,80,32,0.006304000318050384
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,80,16,0.005827200040221215
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,80,8,0.006345599889755249
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,80,4,0.004800000041723251
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,80,2,0.0046431999653577805
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,80,1,0.0046431999653577805
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,96,128,0.006611199676990509
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,96,64,0.006553599983453751
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,96,32,0.006239999830722809
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,96,16,0.004720000177621841
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,96,8,0.005212799832224846
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,96,4,0.004700800031423568
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,96,2,0.004524800181388855
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,96,1,0.004716800153255462
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,128,128,0.006604799628257751
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,128,64,0.006508799642324448
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,128,32,0.0059424001723527905
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,128,16,0.004681599885225296
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,128,8,0.004560000076889992
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,128,4,0.00469760000705719
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,128,2,0.004479999840259552
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,128,1,0.0045056000351905824
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,160,128,0.00859839990735054
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,160,64,0.0065600000321865085
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,160,32,0.006390400230884552
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,160,16,0.006387200206518173
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,160,8,0.00618240013718605
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,160,4,0.004502400010824204
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,160,2,0.004687999933958053
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,160,1,0.004416000097990036
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,192,128,0.008556800335645676
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,192,64,0.00628800019621849
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,192,32,0.00650240033864975
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,192,16,0.006227200105786324
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,192,2,0.006377600133419037
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,192,1,0.004620800167322159
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,256,128,0.008656000345945358
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,256,64,0.006492800265550614
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,256,32,0.006489600241184235
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,256,16,0.006268800050020218
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,256,8,0.00560000017285347
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,192,8,0.004735999926924706
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,256,4,0.004937599971890449
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,256,2,0.004726399853825569
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,256,1,0.0046271998435258865
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,320,128,0.009859199821949004
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,320,64,0.006691200286149978
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,320,16,0.006224000081419945
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,320,32,0.006518399715423584
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,320,4,0.004678399860858917
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,320,8,0.006319999694824219
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,320,1,0.004550400003790855
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,320,2,0.004707200080156326
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,384,64,0.008640000224113464
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,384,128,0.01071999967098236
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,384,16,0.006390400230884552
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,384,32,0.006499200314283371
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,384,8,0.006473600119352341
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,384,4,0.006169600039720535
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,384,2,0.004476799815893173
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,384,1,0.004704000055789947
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,512,128,0.014931200444698334
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,512,32,0.00660799965262413
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,512,64,0.008595199882984161
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,512,16,0.006496000289916992
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,512,4,0.006543999910354615
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,512,2,0.004681599885225296
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,512,1,0.004687999933958053
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,768,128,0.026134398579597474
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,768,64,0.010601600259542465
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,768,32,0.008563199639320373
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,768,16,0.0064800001680850984
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,768,8,0.006150399893522262
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,768,2,0.0046720001846551895
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,768,4,0.006358399987220764
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,768,1,0.004575999826192856
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1024,128,0.033206400275230405
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1024,64,0.01263359934091568
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1024,32,0.008582399785518646
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1024,16,0.006543999910354615
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1024,4,0.005859199911355972
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1024,8,0.0065760001540184024
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1024,2,0.0047807998955249785
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1024,1,0.005721599981188774
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1536,128,0.04635519981384277
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1536,64,0.025171199440956117
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1536,32,0.010576000064611435
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1536,16,0.00843840017914772
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1536,8,0.006406400352716446
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1536,4,0.006473600119352341
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1536,2,0.0060479998588562015
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,1536,1,0.006387200206518173
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,2048,64,0.03298560082912445
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,2048,128,0.06167680025100708
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,2048,32,0.012800000607967377
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,2048,16,0.008595199882984161
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,2048,4,0.0065151996910572055
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,2048,8,0.00679360032081604
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,2048,2,0.006326399743556976
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,2048,1,0.004499199986457825
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,3072,128,0.08407999873161316
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,3072,64,0.0455839991569519
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,3072,32,0.02502399981021881
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,3072,16,0.010623999685049058
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,3072,8,0.008620800077915191
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,3072,4,0.006454399973154068
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,3072,2,0.006496000289916992
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,3072,1,0.006400000303983688
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,4096,128,0.11484800577163697
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,4096,64,0.06068159937858582
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,4096,16,0.012700800597667695
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,4096,32,0.03320319950580597
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,4096,8,0.008502399921417237
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,4096,2,0.006579200178384781
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,4096,4,0.00658240020275116
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,4096,1,0.006400000303983688
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,6144,128,0.164902400970459
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,6144,64,0.08503360152244568
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,6144,16,0.023552000522613525
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,6144,32,0.045747199654579164
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,6144,8,0.010713600367307664
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,6144,4,0.008448000252246856
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,6144,2,0.006508799642324448
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,6144,1,0.006454399973154068
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,8192,64,0.11730560064315795
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,192,4,0.005238400027155876
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,8192,32,0.06449599862098694
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,8192,128,0.22063679695129396
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,8192,16,0.031206399202346802
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,8192,4,0.00856959968805313
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,8192,8,0.012707200646400452
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,8192,1,0.006496000289916992
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,8192,2,0.006719999760389328
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,12288,64,0.15666240453720093
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,12288,32,0.08670079708099365
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,12288,16,0.04408319890499115
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,12288,128,0.3218015909194946
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,12288,8,0.023695999383926393
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,12288,4,0.010662399977445603
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,12288,1,0.0065760001540184024
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,12288,2,0.008495999872684479
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,16384,64,0.218556809425354
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,16384,128,0.42862401008605955
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,16384,32,0.11917760372161865
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,16384,8,0.03027839958667755
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,16384,16,0.05858880281448364
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,16384,2,0.008575999736785888
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,16384,4,0.01279039978981018
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,16384,1,0.006470400094985962
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,20480,64,0.271014404296875
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,20480,32,0.14164799451828003
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,20480,128,0.5308224201202393
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,20480,16,0.07084800004959106
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,20480,4,0.016684800386428833
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,20480,8,0.03751679956912994
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,20480,2,0.008752000331878663
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,20480,1,0.00828159973025322
TRTLLM,1.2.0rc6.post3,NVIDIA GB300,mla_gen_post,default,float16,512,8,0.006499200314283371
