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Welcome to the MyHDL documentation
¶
The MyHDL manual
Overview
Background information
Introduction to MyHDL
Hardware-oriented types
Structural modeling
RTL modeling
High level modeling
Unit testing
Co-simulation with Verilog
Conversion to Verilog and VHDL
Conversion examples
Reference
What’s new in MyHDL 0.8
Modular bit vector types
always_seq
decorator
Other improvements
Acknowledgments
What’s new in MyHDL 0.7
Conversion to VHDL/Verilog rewritten with the
ast
module
Shadow signals
Using
Signal
and
intbv
objects as indices
New configuration attributes for conversion file headers
Conversion propagates docstrings
New method to specify user-defined code
More powerful mapping to case statements
Small changes
Python version
Acknowledgments
What’s new in MyHDL 0.6
Conversion to VHDL
Conversion of lists of signals
Conversion of test benches
Conversion output verification
New modeling features
Backwards incompatible changes
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MyHDL 0.8 documentation
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