THIRD-PARTY NOTICES
===================

This project (distribution name `causal_abstraction_eval`, import name `causal_abstraction`)
is licensed under the MIT License (see LICENSE). Some benchmark systems build
on, link against, and/or redistribute third-party code and data, which remain
under their own licenses. Those components are enumerated below.

The bridge sources committed in this repository
(systems/10_cpu_6502_libs/{isa_bridge.c, gate_bridge.cpp, transistor_bridge.c}
and the *.version linker scripts) are original code authored for this project
and covered by this project's MIT LICENSE. build_libs.sh compiles them together
with the upstream sources listed below; the resulting .so libraries and the
generated Decoder6502.bin therefore embed third-party code/data.

The pinned commit hashes below are those observed in the build environment used
to produce the committed/compiled artifacts.

==============================================================================
1. fake6502: ISA-level 6502 model (systems/10_cpu_6502.py: ISASimulator)
==============================================================================
Upstream:    https://github.com/ivop/fake6502
Commit:      b52676f840983219b0b9baa13f1d0ebc07aac9f9 (2024-05-17)
Files used:  fake6502.c, fake6502.h  (compiled into libisa6502.so)
License:     BSD 2-Clause
A bug-fixed, extended continuation of the original Fake6502 by Mike Chambers.

  BSD 2-Clause License

  Copyright (c) 2011-2013 Mike Chambers
  Copyright (c) 2024 Ivo van poorten
  All rights reserved.

  Redistribution and use in source and binary forms, with or without
  modification, are permitted provided that the following conditions are met:

  1. Redistributions of source code must retain the above copyright notice, this
     list of conditions and the following disclaimer.

  2. Redistributions in binary form must reproduce the above copyright notice,
     this list of conditions and the following disclaimer in the documentation
     and/or other materials provided with the distribution.

  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

==============================================================================
2. break6502 / M6502Core: gate-level 6502 model
   (systems/10_cpu_6502.py: GateSimulator); also the source of Decoder6502.bin
==============================================================================
Upstream:    https://github.com/ivop/break6502
Commit:      922af6496a2fa3b0a999e24419b5f8187f0ee98e (2024-02-16)
Files used:  Common/BaseLogicLib/*, Common/BaseBoardLib/*, Chips/M6502Core/*
             (compiled into libgate6502.so)
License:     UNKNOWN  ⚠  (the upstream repository contains no LICENSE file).

Per the break6502 README, its core code was lifted from
https://github.com/emu-russia/breaknes (itself based on
https://github.com/emu-russia/break, "the 6502 Core book"). This repository
redistributes none of those artifacts, and no break6502 / M6502Core source is
vendored here. The provenance is recorded here for transparency.

Decoder6502.bin:
  A ~272 MB lookup table for the 6502 decode PLA, generated by break6502's
  M6502Core on first construction (HLE mode; "first call generates
  Decoder6502.bin"). build_libs.sh stages a single canonical copy next to
  libgate6502.so (systems/10_cpu_6502_libs/), and GateSimulator loads it from
  there at runtime. It embeds break6502 / breaknes decode data and inherits the
  licensing status above.

==============================================================================
3. perfect6502: transistor-level 6502 model
   (systems/10_cpu_6502.py: TransistorSimulator)
==============================================================================
Upstream:    https://github.com/mist64/perfect6502
Commit:      09fc542877a84318291aa42dab143a3e2c3db974
Files used:  perfect6502.c, netlist_sim.c, netlist_6502.h, perfect6502.h,
             types.h  (compiled into libtransistor6502.so)
License:     MIT
Derived from the visual6502 netlist (https://github.com/trebonian/visual6502)
by Greg James, Brian Silverman, and Barry Silverman.

  MIT License

  Copyright (c) 2010-2020 Michael Steil, Brian Silverman, Barry Silverman

  Permission is hereby granted, free of charge, to any person obtaining a copy
  of this software and associated documentation files (the "Software"), to deal
  in the Software without restriction, including without limitation the rights
  to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  copies of the Software, and to permit persons to whom the Software is
  furnished to do so, subject to the following conditions:

  The above copyright notice and this permission notice shall be included in all
  copies or substantial portions of the Software.

  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  SOFTWARE.

==============================================================================
4. GINsim segment-polarity model: gene regulatory network
   (systems/09_grn/regulatoryGraph.ginml)
==============================================================================
Source:      GINsim project / model repository
             https://ginsim.github.io/models/2008-drosophila-segment-polarity/
             (project home: http://ginsim.org)
Format:      GINML (GINsim regulatory graph; DTD GINML_2_1), dated 2008
Model:       Drosophila segment-polarity gene network (6-cell ring), as used by
             systems/09_grn/grn.py.
Reference:   Sánchez, L., Chaouiya, C., & Thieffry, D. (2008). Segmenting the fly
             embryo: logical analysis of the role of the segment polarity
             cross-regulatory module. International Journal of Developmental
             Biology, 52(8), 1059-1075. https://doi.org/10.1387/ijdb.072439ls
License:     Not stated. This model is redistributed from the academic GINsim
             model repository on the basis of the peer-reviewed publication above.