Metadata-Version: 2.4
Name: axion-hdl
Version: 0.6.3
Summary: Automated AXI4-Lite Register Interface Generator for VHDL modules
Home-page: https://github.com/bugratufan/axion-hdl
Author: Bugra Tufan
Author-email: Bugra Tufan <bugratufan97@gmail.com>
Maintainer-email: Bugra Tufan <bugratufan97@gmail.com>
License: MIT
Project-URL: Homepage, https://github.com/bugratufan/axion-hdl
Project-URL: Documentation, https://github.com/bugratufan/axion-hdl#readme
Project-URL: Repository, https://github.com/bugratufan/axion-hdl
Project-URL: Bug Tracker, https://github.com/bugratufan/axion-hdl/issues
Keywords: vhdl,axi,axi4-lite,fpga,hdl,register,generator,hardware,eda,rtl,code-generation,automation
Classifier: Development Status :: 4 - Beta
Classifier: Intended Audience :: Developers
Classifier: Intended Audience :: Science/Research
Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
Classifier: Topic :: Software Development :: Code Generators
Classifier: Programming Language :: Python :: 3
Classifier: Programming Language :: Python :: 3.7
Classifier: Programming Language :: Python :: 3.8
Classifier: Programming Language :: Python :: 3.9
Classifier: Programming Language :: Python :: 3.10
Classifier: Programming Language :: Python :: 3.11
Classifier: Programming Language :: Python :: 3.12
Classifier: Programming Language :: Python :: 3.13
Classifier: Operating System :: OS Independent
Classifier: Environment :: Console
Classifier: Natural Language :: English
Requires-Python: >=3.7
Description-Content-Type: text/markdown
License-File: LICENSE
Requires-Dist: PyYAML>=6.0
Provides-Extra: dev
Requires-Dist: pytest>=6.0; extra == "dev"
Requires-Dist: pytest-cov>=2.0; extra == "dev"
Requires-Dist: black>=21.0; extra == "dev"
Requires-Dist: flake8>=3.9; extra == "dev"
Requires-Dist: build>=0.7; extra == "dev"
Requires-Dist: twine>=3.4; extra == "dev"
Provides-Extra: docs
Requires-Dist: sphinx>=7.0; extra == "docs"
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Requires-Dist: myst-parser>=2.0; extra == "docs"
Dynamic: author
Dynamic: home-page
Dynamic: license-file
Dynamic: requires-python

# Axion-HDL

**AXI4-Lite register interfaces from VHDL, YAML, XML, or JSON. One command.**

[![PyPI](https://img.shields.io/pypi/v/axion-hdl.svg)](https://pypi.org/project/axion-hdl/)
[![Tests](https://github.com/bugratufan/axion-hdl/actions/workflows/tests.yml/badge.svg)](https://github.com/bugratufan/axion-hdl/actions/workflows/tests.yml)
[![Docs](https://readthedocs.org/projects/axion-hdl/badge/?version=stable)](https://axion-hdl.readthedocs.io/en/stable/)
[![License: MIT](https://img.shields.io/badge/License-MIT-blue.svg)](LICENSE)

---

## Install

```bash
pip install axion-hdl
```

## Use

```bash
# From VHDL with @axion annotations
axion-hdl -s my_module.vhd -o output/

# From YAML/XML/JSON
axion-hdl -s registers.yaml -o output/
```

**Output:** VHDL module, C header, documentation, XML/YAML/JSON exports.

## Define Registers

**VHDL** — embed in your code:
```vhdl
-- @axion_def BASE_ADDR=0x1000 CDC_EN
signal status  : std_logic_vector(31 downto 0); -- @axion RO
signal control : std_logic_vector(31 downto 0); -- @axion RW W_STROBE
```

**YAML** — standalone file:
```yaml
module: my_module
base_addr: "0x1000"
config:
  cdc_en: true
registers:
  - name: status
    access: RO
  - name: control
    access: RW
    w_strobe: true
```

## Features

- **Multi-format input** — VHDL annotations, YAML, XML, JSON
- **CDC support** — built-in clock domain crossing synchronizers
- **Subregisters** — pack multiple fields into one address
- **Wide signals** — auto-split 64-bit+ signals across addresses
- **Tested** — 230+ tests, GHDL simulation verified

## Documentation

📖 **[axion-hdl.readthedocs.io](https://axion-hdl.readthedocs.io/en/stable/)**

## Contributing

```bash
git checkout develop
git checkout -b feature/your-feature
make test
# PR to develop
```

## License

MIT — [Bugra Tufan](mailto:bugratufan97@gmail.com)
