design

Usage

altium-cruncher design project.PrjPcb -o output/design_review
altium-cruncher design-review project.PrjPcb
altium-cruncher dr schematic.SchDoc

Arguments

file accepts .SchDoc or .PrjPcb. When omitted, the command attempts project auto-detection in the current directory. -o selects the output directory. --no-indexes omits optional lookup indexes from the design JSON. design-review and dr are aliases for the same command and output contract.

Output

The command defaults to output/design_review and writes design_review_manifest.json with breaking schema altium_cruncher.design_review_manifest.b0, README.md, design/<input>_design.json from AltiumDesign.to_json(), notes/<input>_notes.jsonc, serialized SchDoc/PcbDoc JSON under json/schdoc/ and json/pcbdoc/, schematic SVGs under sch/, and PCB copper-layer review SVGs under pcb/layers/ for project inputs with boards. Design b0 is the primary semantic model: its required compiled_schematic_graph owns realized pages, hierarchy, components, local nets, terminals, bindings, and scoped drawing links; physical_page_metadata carries only Altium channel/room presentation facts. SchDoc and PrjPcb schematic manifest and SVG roots record page_occurrence_ref plus artifact_key="sch.dwg_scene"; source groups join through element_id. Compiled SVG metadata uses the Cruncher-owned breaking altium_cruncher.schematic.svg.enrichment.b0 contract and schematic-enrichment-b0 metadata id. The SVG metadata does not duplicate the graph. The generated README explains how schematic SVG metadata, PCB SVG metadata, design JSON, and json-dump document snapshots relate, and includes power-tree review hints for following selected two-pin series parts. Each PCB review SVG follows the default pcb-svg layer-output contract but limits physical layers to copper layers, including inner copper layers when present; board outline, board cutouts, drills, and slots are included. Layer classification is V7-aware when the installed altium-monkey exposes the V7-aware layer API: copper detection is layer-family based (including StackUpX-backed extended signal layers and via layer_start/layer_end spans), and primitives on Mechanical17+ layers classify under their real layer identity instead of degrading to unknown. Composed PCB views and assembly/HLR virtual layers are intentionally omitted from dr; use pcb-svg when those heavier views are needed. The command logs each generated SVG and JSON artifact as it is written. The notes artifact uses the default review filter and suppresses title-block/sheet-template owned text.

Review identity and compiler evidence

DR explicitly requests include_compile_metadata=True, preserving the released Design b0 compile and diagnostics sections even with --no-indexes. Compiler diagnostics and graph terminal resolution diagnostics describe compiler health and evidence limits; they are not automatically electrical-design defects. Unresolved evidence does not prove an open circuit, and absence of diagnostics does not certify the circuit. Warnings alone do not fail bundle generation. The full beta raw compiler model is not exported.

Component labels are not identities. SVG enrichment uses the physical IR's physical_page.page_occurrence_ref and physical_page.id to bind a canonical graph page to the raw physical document. Within that document, graph component source_identity["sch.source_key.source_uuid"] matches a unique Design row's source_unique_id and physical_sheet_id. Duplicate or missing candidates retain graph identity and labels without borrowed value or variant attributes. Some multipart bodies have no matching aggregate source UID in Design b0; their missing enrichment does not imply missing value or not-fitted state. Opaque IDs are not parsed, and raw compiler IDs are not equated to graph IDs.

The generated README explains that classification.pin_count is the combined compiled schematic count for the complete component. Do not multiply by part count, divide it to infer body counts, or use it as proof of physical package-pad completeness. Per-body inspection must respect the source body's selected part, display mode, and pin visibility. Power-tree review follows scoped graph connectivity; optional indexes and non-unique aliases only aid navigation. These instructions target Monkey 2026.9.12 and its current contracts, without anticipating future cardinality fields.

Tests

L0 verifies help and aliases. Unit workflow tests synthesize SchDoc and PcbDoc inputs, then verify the dr alias writes design JSON, notes JSONC, document JSON, schematic SVG, copper-only PCB review SVGs, manifest, and README artifacts while omitting composed assembly views. Identity regressions in tests/test_design_review_identity.py cover duplicate labels, repeated-source page scope, multipart bodies, and missing or ambiguous evidence. Bundle tests verify compiler context and optional-index behavior. L3 continues to verify Hydroscope design JSON contents through the same command.