# file: /Users/mfwolffe/GithubOrgs/tenseleyFlow/DocumentLanguageModel/src/dlm/hardware/plan.py
# hypothesis_version: 6.152.1

[0.5, 0.7, 0.85, 1.8, 2.2, ', ', 'auto', 'bf16', 'dpo', 'eager', 'flash_attention_2', 'fp16', 'grad_ckpt=on', 'phase=dpo', 'qlora', 'qlora=4bit-nf4', 'qlora=off', 'sdpa', 'sft']