YOUR LOCAL DESIGN WORKSPACE

Bring your design to life.

Test your RTL, build a netlist, and generate a physical layout — one step at a time.

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New here? Start with a working design.

The counter example has a self-checking testbench. Try a simulation to see how everything fits together.

LEARN BY RUNNING REAL TOOLS

Your first RTL-to-GDS journey

Start with a counter that includes a testbench. Simulation only needs Icarus Verilog.

Every step saves a new run. Physical steps include their prerequisites; they do not resume an earlier run.

    VLSI terms in plain language

    Start a design run

    Choose a saved project, or create one using the guided form.

    Design runs 0

    Select two runs to compare

    Loading your runs…

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    Your results will appear here

    Start a simulation above, or select a previous run to explore its results.

    GUIDED SETUP

    Create a project

    Point Chipflow to your local design files. No YAML editing needed.

    1. Your design

    2. Simulation optional

    Add a testbench to check that your design behaves as expected.

    3. Clock & technology

    Advanced settings Constraints, physical design, Tcl hooks & native ORFS settings

    Tcl hooks and native flow settings

    Keep scripts and helper files together. Chipflow copies the bundle into each run; hooks execute in the native Yosys/OpenROAD processes.

    Tcl executes with your user permissions. A script override replaces the corresponding native policy.

    Saved locally as a new project configuration.
    GETTING STARTED

    A clear path from code to layout

    01

    Test your RTL

    Choose “Simulate RTL.” Chipflow runs your testbench and looks for its success message. Download the waveform to inspect signals in a local viewer.

    02

    Build the gates

    Choose “Create a gate-level netlist.” Synthesis maps your RTL to cells in the selected technology library. Gate simulation can test this netlist with compatible cell models.

    03

    Create the layout

    Choose “Generate the final layout.” Chipflow runs synthesis, floorplanning, placement, the clock tree, routing, and finishing in order.

    04

    Review the results

    Completion means the requested tools finished. Timing and router checks are shown separately. Full physical signoff is not established by this application.

    Working with your own design

    Use Create project and enter paths to files on this computer. Files inside an existing YAML configuration resolve relative to that configuration. The project form uses the workspace folder for relative paths.

    If a run fails

    Its inputs and logs are saved. Open Live logs for the tool’s error, then fix your project and start a new run. “Run again” uses the saved inputs from the selected run.
    EXPERT CONFIGURATION

    Edit the complete project YAML

    All supported clocks, constraints, Tcl hooks, native variables, library files, and timeouts are editable here. Saving creates a new project copy.

    Existing paths are resolved for the new copy. New relative paths start in the workspace folder. Script contents are edited in your local Tcl files.

    Source configurations and previous runs are preserved.
    LOCAL ENVIRONMENT

    Installed tools

    Availability on the server’s PATH. Compatibility is verified when a flow runs.