{
  "path": "$PRJ/tests/svfiles_examples/param_module.sv",
  "modules": [
    {
      "name": "param_module",
      "params": [
        {
          "name": "WIDTH",
          "comment": [
            "// Width of the input data\n"
          ]
        },
        {
          "name": "DEPTH"
        },
        {
          "name": "INIT_VAL",
          "width": "[7:0]"
        },
        {
          "ptype": "logic",
          "name": "ENABLE_FEATURE"
        }
      ],
      "ports": [
        {
          "direction": "input",
          "ptype": "wire",
          "name": "clk"
        },
        {
          "direction": "input",
          "ptype": "wire",
          "name": "rst_n",
          "comment": [
            "// active-low reset\n"
          ]
        },
        {
          "direction": "input",
          "ptype": "wire",
          "name": "data_in",
          "width": "[WIDTH-1:0]",
          "comment": [
            "// Input data\n"
          ]
        },
        {
          "direction": "output",
          "ptype": "reg",
          "name": "data_out",
          "width": "[WIDTH-1:0]"
        },
        {
          "direction": "inout",
          "ptype": "wire",
          "name": "bidir_bus",
          "width": "[DEPTH-1:0]"
        }
      ],
      "insts": [
        {
          "name": "u_sub_module",
          "module": "sub_module"
        },
        {
          "name": "u_sub_module2",
          "module": "sub_module"
        }
      ]
    },
    {
      "name": "sub_module",
      "params": [
        {
          "name": "DATA_WIDTH"
        },
        {
          "name": "INIT_VALUE",
          "width": "[7:0]"
        }
      ],
      "ports": [
        {
          "direction": "input",
          "ptype": "wire",
          "name": "clk"
        },
        {
          "direction": "input",
          "ptype": "wire",
          "name": "reset"
        },
        {
          "direction": "input",
          "ptype": "wire",
          "name": "input_data",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "output",
          "ptype": "wire",
          "name": "output_data",
          "width": "[DATA_WIDTH-1:0]"
        },
        {
          "direction": "inout",
          "ptype": "wire",
          "name": "config_bus",
          "width": "[DATA_WIDTH/2-1:0]"
        }
      ]
    }
  ]
}