5 #ifndef IRQ_API_C_HEADER_FILE 6 #define IRQ_API_C_HEADER_FILE 8 #ifndef DOXYGEN_SHOULD_SKIP_THIS 10 extern unsigned int flag;
13 void HK_IRQ0_Handler(
void){flag = 1;}
14 void HK_IRQ1_Handler(
void){flag = 1;}
15 void HK_IRQ2_Handler(
void){flag = 1;}
16 void TMR0_Handler(
void){flag = 1;clear_TMR0_Handler();}
17 void UART0_Handler(
void){flag = 1;clear_UART0_Handler();}
18 void clear_TMR0_Handler(){
21 void clear_UART0_Handler(){
54 irq_setmask(irq_getmask() | (1 << USER_IRQ_4_INTERRUPT));
57 NVIC_EnableIRQ(HK_IRQ1);
64 irq_setmask(irq_getmask() & ~(1 << USER_IRQ_4_INTERRUPT));
66 user_irq_4_ev_pending_i0_write(1);
68 NVIC_DisableIRQ(HK_IRQ1);
85 irq_setmask(irq_getmask() | (1 << USER_IRQ_5_INTERRUPT));
88 NVIC_EnableIRQ(HK_IRQ2);
95 irq_setmask(irq_getmask() & ~(1 << USER_IRQ_5_INTERRUPT));
97 user_irq_5_ev_pending_i0_write(1);
99 NVIC_DisableIRQ(HK_IRQ2);
115 irq_setmask(irq_getmask() | (1 << USER_IRQ_0_INTERRUPT));
117 reg_user_irq_enable |=0x1;
119 NVIC_EnableIRQ(HK_IRQ2);
126 irq_setmask(irq_getmask() & ~(0 << USER_IRQ_0_INTERRUPT));
128 reg_user_irq_enable &=0x6;
129 user_irq_0_ev_pending_i0_write(1);
131 NVIC_DisableIRQ(HK_IRQ2);
147 irq_setmask(irq_getmask() | (1 << USER_IRQ_1_INTERRUPT));
149 reg_user_irq_enable |=0x2;
151 NVIC_EnableIRQ(HK_IRQ2);
158 irq_setmask(irq_getmask() & ~(1 << USER_IRQ_1_INTERRUPT));
160 reg_user_irq_enable &=0x5;
161 user_irq_1_ev_pending_i0_write(1);
163 NVIC_DisableIRQ(HK_IRQ2);
180 irq_setmask(irq_getmask() | (1 << USER_IRQ_2_INTERRUPT));
182 reg_user_irq_enable |=0x4;
184 NVIC_EnableIRQ(HK_IRQ2);
191 irq_setmask(irq_getmask() & ~(1 << USER_IRQ_2_INTERRUPT));
193 reg_user_irq_enable &=0x3;
194 user_irq_2_ev_pending_i0_write(1);
196 NVIC_DisableIRQ(HK_IRQ2);
212 irq_setmask(irq_getmask() | (1 << TIMER0_INTERRUPT));
213 reg_timer0_irq_en = 1;
215 NVIC_EnableIRQ(TMR0_IRQn);
216 reg_timer0_config = reg_timer0_config | 0x8;
223 irq_setmask(irq_getmask() & ~(1 << TIMER0_INTERRUPT));
224 reg_timer0_irq_en = 0;
225 timer0_ev_pending_zero_write(1);
227 NVIC_DisableIRQ(TMR0_IRQn);
228 reg_timer0_config = reg_timer0_config | 0x8;
246 irq_setmask(irq_getmask() | (1 << UART_INTERRUPT));
248 NVIC_EnableIRQ(UART0_IRQn);
249 reg_uart_ctrl = reg_uart_ctrl | 0x5;
257 irq_setmask(irq_getmask() & ~(1 << UART_INTERRUPT));
258 uart_ev_pending_tx_write(1);
260 NVIC_DisableIRQ(UART0_IRQn);
261 reg_uart_ctrl = reg_uart_ctrl | 0x5;
279 irq_setmask(irq_getmask() | (1 << UART_INTERRUPT));
281 NVIC_EnableIRQ(UART0_IRQn);
282 reg_uart_ctrl = reg_uart_ctrl | 0xA;
291 irq_setmask(irq_getmask() & ~(1 << UART_INTERRUPT));
292 uart_ev_pending_rx_write(1);
294 reg_uart_ctrl = reg_uart_ctrl & 0xF7;
311 irq_setmask(irq_getmask() | (1 << USER_IRQ_3_INTERRUPT));
313 NVIC_EnableIRQ(HK_IRQ0);
320 irq_setmask(irq_getmask() & ~(1 << USER_IRQ_3_INTERRUPT));
322 user_irq_3_ev_pending_i0_write(1);
324 NVIC_DisableIRQ(HK_IRQ0);
330 #endif // IRQ_API_C_HEADER_FILE void IRQ_enableUser1(bool is_enable)
Definition: irq_api.h:142
void IRQ_enableExternal1(bool is_enable)
Definition: irq_api.h:49
void IRQ_enableUser2(bool is_enable)
Definition: irq_api.h:175
void IRQ_enableUartRx(bool is_enable)
Definition: irq_api.h:272
void dummyDelay(int num)
Definition: common.h:115
void IRQ_enableExternal2(bool is_enable)
Definition: irq_api.h:80
void IRQ_enableTimer(bool is_enable)
Definition: irq_api.h:207
void IRQ_hkSpi(bool is_enable)
Definition: irq_api.h:305
void IRQ_enableUartTx(bool is_enable)
Definition: irq_api.h:239
void IRQ_enableUser0(bool is_enable)
Definition: irq_api.h:110