INFO: [Timing 38-91] UpdateTimingParams: No interconnect No Cell Dly, Speed grade: -1, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Timing 38-433] Consider using Xilinx recommended XPM_CDC modules to avoid Critical severities
INFO: [Timing 38-314] The report_cdc command only analyzes and reports clock domain crossing paths where clocks have been defined on both source and destination sides. Ports with no input delay constraint are skipped. Please run check_timing to verify there are no missing clock definitions in your design, nor any unconstrained input port.
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| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
| Command      : report_cdc -return_string
| Design       : cdc_top
| Device       : 7a35t-cpg236
| Speed File   : -1  PRODUCTION 1.23 2018-06-13
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CDC Report

Severity  Source Clock  Destination Clock  CDC Type                 Exceptions  Endpoints  Safe  Unsafe  Unknown  No ASYNC_REG
--------  ------------  -----------------  -----------------------  ----------  ---------  ----  ------  -------  ------------
Critical  clk_a         clk_b              No Common Primary Clock  None                5     1       0        4             0
