INFO: [Timing 38-91] UpdateTimingParams: No interconnect No Cell Dly, Speed grade: -1, Delay Type: max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Timing 38-433] Consider using Xilinx recommended XPM_CDC modules to avoid Critical severities
INFO: [Timing 38-314] The report_cdc command only analyzes and reports clock domain crossing paths where clocks have been defined on both source and destination sides. Ports with no input delay constraint are skipped. Please run check_timing to verify there are no missing clock definitions in your design, nor any unconstrained input port.
Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
| Command      : report_cdc -details -return_string
| Design       : cdc_top
| Device       : 7a35t-cpg236
| Speed File   : -1  PRODUCTION 1.23 2018-06-13
------------------------------------------------------------------------------------

CDC Report

ID     Severity  Count  Description
-----  --------  -----  ------------------------------------------
CDC-3  Info          1  1-bit synchronized with ASYNC_REG property
CDC-4  Critical      1  Multi-bit unknown CDC circuitry

ID     Waived Endpoints
-----  ----------------
CDC-1                 1

Source Clock: clk_a
Destination Clock: clk_b
CDC Type: No Common Primary Clock

Row  ID     Severity  Description                                 Depth  Exception  Source (From)      Destination (To)
---  -----  --------  ------------------------------------------  -----  ---------  -----------------  ---------------------
  1  CDC-3  Info      1-bit synchronized with ASYNC_REG property      2  None       source_reg[1]/C    sync1_reg/D
  2  CDC-4  Critical  Multi-bit unknown CDC circuitry                 0  None       source_reg[3:1]/C  unsafe_bus_reg[3:1]/D
