Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------
      0.234        0.000                      0                  150        0.045        0.000                      0                  150


All user specified timing constraints are met.


------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------

Clock       Waveform(ns)       Period(ns)      Frequency(MHz)
-----       ------------       ----------      --------------
userclk2    {0.000 2.000}      4.000           250.000
sys_clk     {0.000 5.000}      10.000          100.000


------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------
userclk2            0.234        0.000                      0                  120        0.045        0.000                      0                  120
sys_clk             2.456        0.000                      0                   30        0.123        0.000                      0                   30


Slack (MET) :             0.234ns  (required time - arrival time)
  Source:                 xdma_0/inst/pcie_top/pcie_7x_i/pcie_bram_top/reg_a/C
                            (rising edge-triggered cell FDRE clocked by userclk2  {rise@0.000ns fall@2.000ns period=4.000ns})
  Destination:            xdma_0/inst/pcie_top/pcie_7x_i/pcie_bram_top/reg_b/D
                            (rising edge-triggered cell FDRE clocked by userclk2  {rise@0.000ns fall@2.000ns period=4.000ns})
  Path Group:             userclk2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.000ns  (userclk2 rise@4.000ns - userclk2 rise@0.000ns)
  Data Path Delay:        3.766ns  (logic 1.234ns (32.8%)  route 2.532ns (67.2%))
  Logic Levels:           5  (LUT2=1 LUT4=2 LUT6=1 MUXF7=1)
  Clock Path Skew:        -0.042ns (DCD - SCD + CPR)

Slack (MET) :             2.456ns  (required time - arrival time)
  Source:                 clk_gen/mmcm_inst/CLKOUT0
                            (rising edge-triggered cell MMCME2_ADV clocked by sys_clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            reset_sync/sync_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by sys_clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             sys_clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (sys_clk rise@10.000ns - sys_clk rise@0.000ns)
  Data Path Delay:        7.544ns  (logic 2.100ns (27.8%)  route 5.444ns (72.2%))
  Logic Levels:           3  (LUT4=1 LUT6=2)
  Clock Path Skew:        0.100ns (DCD - SCD + CPR)
