Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
| Date         : Tue Jun 10 12:00:00 2026
| Host         : DESKTOP-NJ running 64-bit major release  (build 9200)
| Command      : report_utilization
| Design       : top
| Device       : 7a35tcpg236-1
| Design State : Routed
-------------------------------------------------------------------------------------------------------------------------

Utilization Design Information

Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Memory
3. DSP
4. IO and GT Specific
5. Clocking

1. Slice Logic
--------------

+----------------------------+------+-------+-----------+-------+
|          Site Type         | Used | Fixed | Available | Util% |
+----------------------------+------+-------+-----------+-------+
| Slice LUTs                 | 1440 |     0 |     20800 |  6.92 |
|   LUT as Logic             | 1380 |     0 |     20800 |  6.63 |
|   LUT as Memory            |   60 |     0 |      9600 |  0.63 |
| Slice Registers            | 2200 |     0 |     41600 |  5.29 |
|   Register as Flip Flop    | 2200 |     0 |     41600 |  5.29 |
|   Register as Latch        |    0 |     0 |     41600 |  0.00 |
+----------------------------+------+-------+-----------+-------+

2. Memory
---------

+-------------------+------+-------+-----------+-------+
|     Site Type     | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile    |   12 |     0 |        50 | 24.00 |
|   RAMB36/FIFO*    |   10 |     0 |        50 | 20.00 |
|     RAMB36E1 only |   10 |       |           |       |
|   RAMB18          |    4 |     0 |       100 |  4.00 |
|     RAMB18E1 only |    4 |       |           |       |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1

3. DSP
------

+----------------+------+-------+-----------+-------+
|    Site Type   | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs           |    8 |     0 |        90 |  8.89 |
|   DSP48E1 only |    8 |       |           |       |
+----------------+------+-------+-----------+-------+

4. IO and GT Specific
---------------------

+-----------------------------+------+-------+-----------+-------+
|          Site Type          | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB                  |   16 |    16 |       106 | 15.09 |
+-----------------------------+------+-------+-----------+-------+

5. Clocking
-----------

+------------+------+-------+-----------+-------+
|  Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL   |    2 |     0 |        32 |  6.25 |
| MMCME2_ADV |    1 |     0 |         5 | 20.00 |
| PLLE2_ADV  |    0 |     0 |         5 |  0.00 |
+------------+------+-------+-----------+-------+
