Metadata-Version: 2.4
Name: constraintforge
Version: 0.1.0
Summary: A pre-synthesis structural timing analyzer and constraint generator for RTL.
Author-email: Dev Tyagi <dev@example.com>
Project-URL: Homepage, https://devtyagi3909.github.io/constraintforge
Project-URL: Repository, https://github.com/devtyagi3909/constraintforge
Classifier: Programming Language :: Python :: 3
Classifier: License :: OSI Approved :: MIT License
Classifier: Operating System :: OS Independent
Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
Requires-Python: >=3.10
Description-Content-Type: text/markdown
Requires-Dist: click>=8.1.0
Requires-Dist: rich>=13.0.0

# ConstraintForge CLI

A pre-synthesis structural timing diagnostic engine for Verilog and SystemVerilog.

ConstraintForge parses raw RTL into an AST, builds a Directed Acyclic Graph (DAG) of your logic, and runs a modified Depth-First Search to accurately estimate combinational logic depth and fanout. It flags setup time violations and routing bottlenecks *before* you run synthesis.

## Requirements
- Python 3.10+
- [Yosys](https://yosyshq.net/yosys/) (Must be installed and available in `$PATH`)

## Installation

```bash
pip install constraintforge
```

## Usage

```bash
constraintforge diagnose src/*.v --top top_module --max-depth 20 --max-fanout 50
```
