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Modules Rule Check Generate Config Docs GitHub

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Axion-HDL

Automated AXI4-Lite Register Interface Generator

MIT License — Free and Open Source

Resources

Documentation Examples CLI Reference Python API

Project

GitHub Repository Issue Tracker PyPI Package License

Contact

support@axion-hdl.com GitHub @bugratufan bugratufan.com

© 2026 Bugra Tufan. Built for the ASIC/FPGA community.

GUI Beta Notice

The Axion-HDL graphical interface is currently in beta. You may encounter unexpected errors or features that are not yet fully supported.

For stable and fully-featured usage, the CLI interface or Python API is recommended.

If you run into a bug, please report it on GitHub:

Open a Bug Report

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