PyICe.xml_registers¶
XML Register Map Tools and Generators¶
Collection of Tools to Manage and Leverage an XML Description of a Register/Memory Map.
Submodules¶
PyICe.xml_registers.asm_header.xml_to_asm_header |
micro16a/b Assembly Header Generator |
PyICe.xml_registers.c_api.xml_to_c_api |
Distributable Embedded C Communication Library Generator |
PyICe.xml_registers.c_api.c_configurator |
Distributable Embedded C POR Defaults Configurator Generator |
PyICe.xml_registers.cpp_ets_api.generate_cpp |
Eagle Test System C++ I2C Communication Class Generator |
PyICe.xml_registers.datasheet_indesign.datasheet_registers_xml |
Adobe Indesign (Datasheet) Register Table and Hyperlink Generator |
PyICe.xml_registers.doc.doc_generator |
HTML Register Map Documentation Generator |
PyICe.xml_registers.doc.html_link_checker |
Autogenerated HTML Link Check Tool |
PyICe.xml_registers.micro16c.xml_to_headers |
micro16c C and Assembly Register Map Header Generator |
PyICe.xml_registers.python_api.generate_python_api |
Distributable Python Communication Library Generator |
PyICe.xml_registers.register_lint.register_lint |
Automated Register Map Audit Tool |
PyICe.xml_registers.sanitize.sanitize_xml |
Distributable Public XML Register Map Generator |
PyICe.xml_registers.variants.split_variants |
Multiple Chip Shared Register Description Splitter Tool |
PyICe.xml_registers.vb_api.xml_to_vb_api |
Visual Basic Register Map Header Generator |
PyICe.xml_registers.verilog_header.xml_to_verilog_header |
Verilog Register Map Header Generator |
PyICe.xml_registers.verilog_mem_map.xml_to_verilog_mem_map |
Verilog SFR Memory Map Generator for Embedded uC |
PyICe.xml_registers.verilog_rtl.xml_to_verilog_rtl |
Verilog Register Generator for non-uC Designs |