PyICe.spi_interface¶
SPI Interface Hardware Drivers¶
Created on Feb 23, 2015 Heavily modified August 2016 to be more generic.
@author: JKapasi @author: DSimmons
The SPI interface is composed of two separate classes:
- shift_register
abstracts individual bit-fields into integer representing contents of full-length shift register
- spiInterface: Defines the hardware interface including baudrate, mode (CPOL/CPHA), CS operation.
Specific hardware implementations should overload this class and implement _shift_data method.
Functions
Classes
shift_register ([bit_field_name, ...]) |
helper class to assemble multiple bit-fields together into a single larger integer and to disassemble received data into individual bit-fields. |
spiInterface (CPOL, CPHA, ss_ctrl, word_size) |
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spi_bbone (CPOL, CPHA, ss_ctrl, word_size) |
The Beaglebone black will use the Adafruit BBIO, thus we can initialize this package for all purposes This instrument probably got a broken when the parent class interface was modified to support multiple interface hardware boards and more general SPI communication. |
spi_bitbang (SCK_channel[, MOSI_channel, ...]) |
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spi_buspirate (interface_raw_serial[, CPOL, ...]) |
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spi_cfgpro (visa_interface, CPOL, CPHA[, ...]) |
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spi_dc590 (interface_stream[, ss_ctrl]) |
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spi_dummy ([delay, word_size]) |
Exceptions
SPIMasterError |
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class
PyICe.spi_interface.
shift_register
(bit_field_name=None, bit_field_bit_count=None)[source]¶ Bases:
object
helper class to assemble multiple bit-fields together into a single larger integer and to disassemble received data into individual bit-fields.
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add_bit_field
(bit_field_name, bit_field_bit_count)[source]¶ build SPI shift register data protocol sequentially MSB->LSB with repeated calls to add_bit_field
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class
PyICe.spi_interface.
spi_bbone
(CPOL, CPHA, ss_ctrl, word_size)[source]¶ Bases:
PyICe.spi_interface.spiInterface
The Beaglebone black will use the Adafruit BBIO, thus we can initialize this package for all purposes This instrument probably got a broken when the parent class interface was modified to support multiple interface hardware boards and more general SPI communication. Needs testing/repair.
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pack
(data_list, word_size=8)¶ pack byte,word aligned pieces (list) from communication hardware into single integer comprising full shift register width. integer can then be broken up by shift_register object into bit field aligned pieces.
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set_ss_ctrl
(ss_ctrl_function)¶ change ss_ctrl function after instantiation. function should take single boolean argument. If true, assert slave select. If false, deassert slave select. There will typically be a logic inversion inside ss_ctrl to achieve active low _cs.
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set_strict_alignment
(strict)¶ If true, enforce that SPI master and slave hardware lengths match. If false, enable automatic padding to correct alignment.
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transceive
(data, clk_count)¶ send data word out MOSI with clk_count clocks. return word of same size read simultaneously on MISO. Frame entire transaction with slave select.
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unpack
(data, bit_count, word_size=8)¶ break full shift register width integer into byte,word aligned pieces. Return list of pieces MS first, LS last. helper to send byte-aligned pieces to hardware even if bit fields span bytes (or 1-bit, 16-bit 32-bit, etc words for other hardware)
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