Metadata-Version: 2.1
Name: zuspec-be-sw
Version: 0.1.0.13350119097rc0
Summary: Backend library to generate software output
Home-page: https://github.com/zuspec/zuspec-be-sw
Author: Matthew Ballance
Author-email: matt.ballance@gmail.com
License: Apache 2.0
Keywords: SystemVerilog,Verilog,RTL,Python
License-File: LICENSE
Requires-Dist: ciostream
Requires-Dist: zuspec-arl-dm>=0.1.0
Requires-Dist: vsc-dm
Requires-Dist: debug-mgr


  Provides features for mapping ARL models to software output
  
