### method align(bytes=64)
.balign 64
### method asmfile_annotations()
.section .note.GNU-stack,"",%progbits
### method c_simd_size_function()
static inline size_t get_simd_size() { return 64; }
### method cb(cmp=NE, label=notequal, reg1=r8, reg2=r9)
cmp %r9,%r8
jne .notequal
### method compiler_flags()
['-mavx512f', '-mavx512vl', '-mavx512dq', '-mavx512bw', '-mavx512fp16', '-mavx512bf16']
### method create_callconv(name=default)
<asmgen.callconv.callconv.callconv object>
### method enabled_features()
{BF16, BW, DQ, FP16, VL}
### method freg(dt=DOUBLE, reg_idx=0)
xmm0
### method freg(dt=HALF, reg_idx=0)
xmm0
### method freg(dt=SINGLE, reg_idx=0)
xmm0
### method get_param_value(name=dummy)
dummy
### method get_parameters()
['VL', 'DQ', 'BW', 'FP16', 'BF16', 'enable-disp8', 'enable-disp32']
### method greg(reg_idx=0)
r8
### method is_vla()
False
### method isaclear()
None
### method isadata()

### method isaendquirks(dt=DOUBLE, rt=<asmgen.registers.reg_tracker object>)

### method isaendquirks(dt=HALF, rt=<asmgen.registers.reg_tracker object>)

### method isaendquirks(dt=SINGLE, rt=<asmgen.registers.reg_tracker object>)

### method isaquirks(dt=DOUBLE, rt=<asmgen.registers.reg_tracker object>)

### method isaquirks(dt=HALF, rt=<asmgen.registers.reg_tracker object>)

### method isaquirks(dt=SINGLE, rt=<asmgen.registers.reg_tracker object>)

### method jfzero(dt=DOUBLE, freg1=xmm0, freg2=xmm1, greg=r8, label=someloop)
vpxord %xmm1,%xmm1,%xmm1
ucomisd %xmm1,%xmm0
je .someloop
### method jfzero(dt=HALF, freg1=xmm0, freg2=xmm1, greg=r8, label=someloop)
vpxord %xmm1,%xmm1,%xmm1
ucomish %xmm1,%xmm0
je .someloop
### method jfzero(dt=SINGLE, freg1=xmm0, freg2=xmm1, greg=r8, label=someloop)
vpxord %xmm1,%xmm1,%xmm1
ucomiss %xmm1,%xmm0
je .someloop
### method jump(label=someloop)
jmp .someloop
### method jvzero(dt=DOUBLE, freg=xmm2, greg=r8, label=someloop, vreg1=zmm0, vreg2=zmm1)
vpxorq %zmm1,%zmm1,%zmm1
vcmpeqpd %zmm1,%zmm0,%zmm1
vptest %zmm1,%zmm1
jne .someloop
### method jvzero(dt=HALF, freg=xmm2, greg=r8, label=someloop, vreg1=zmm0, vreg2=zmm1)
vpxorq %zmm1,%zmm1,%zmm1
vcmpeqph %zmm1,%zmm0,%zmm1
vptest %zmm1,%zmm1
jne .someloop
### method jvzero(dt=SINGLE, freg=xmm2, greg=r8, label=someloop, vreg1=zmm0, vreg2=zmm1)
vpxorq %zmm1,%zmm1,%zmm1
vcmpeqps %zmm1,%zmm0,%zmm1
vptest %zmm1,%zmm1
jne .someloop
### method jzero(label=someloop, reg=r8)
test %r8,%r8
jz .someloop
### method kiterkleft(kleftreg=r9, kreg=r8, tmpreg=r10, unroll=4)
movq %r8, %r9
andq $3, %r9
shrq $2, %r8
### method label(label=label)
.label:
### method labelstr(label=label)
.label
### method loopbegin(label=someloop, reg=r8)
.someloop:
sub $1, %r8
### method loopbegin_nz(label=someloop, labelskip=someloop_nz, reg=r8)
test %r8,%r8
jz .someloop_nz
.someloop:
sub $1, %r8
### method loopend(label=someloop, reg=r8)
cmp $0x0,%r8
jne .someloop
### method max_fregs()
32
### method max_gregs()
16
### method max_tregs(dt=DOUBLE)
0
### method max_tregs(dt=HALF)
0
### method max_tregs(dt=SINGLE)
0
### method max_vregs()
32
### method nop()
nop
### method ret()
ret
### method simd_size()
64
### method supported_on_host()
True
### method supportedby_cpuinfo(cpuinfo=invalid_isa)
False
### method tile_types()
[]
### method treg(dt=DOUBLE, reg_idx=0)
!NotImplementedError: Not tile support in AVX (will be supported with AMX)
### method treg(dt=HALF, reg_idx=0)
!NotImplementedError: Not tile support in AVX (will be supported with AMX)
### method treg(dt=SINGLE, reg_idx=0)
!NotImplementedError: Not tile support in AVX (will be supported with AMX)
### method treg_tag(dt=DOUBLE)
treg
### method treg_tag(dt=HALF)
treg
### method treg_tag(dt=SINGLE)
treg
### method vreg(reg_idx=0)
zmm0
### op add [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64
movq %rcx,%rsi
addq %rdx,%rsi
### op add [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64{ISHIFT} cdreg:REGISTER:GP:SINT64 bdreg_shift:IMMEDIATE:-:-
leaq (%rcx,%rdx,1),%rsi
### op add [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64{ISHIFT} cdreg:REGISTER:GP:SINT64 bdreg_shift:IMMEDIATE:-:- @far
leaq (%rcx,%rdx,8),%rsi
### op add [] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:-
movq %rcx,%rdx
addq $-2147483648,%rdx
### op add [] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:- @far
movq %rcx,%rdx
addq $2147483647,%rdx
### op add [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64
movq %rcx,%rsi
addq %rdx,%rsi
### op add [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64{ISHIFT} cdreg:REGISTER:GP:UINT64 bdreg_shift:IMMEDIATE:-:-
leaq (%rcx,%rdx,1),%rsi
### op add [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64{ISHIFT} cdreg:REGISTER:GP:UINT64 bdreg_shift:IMMEDIATE:-:- @far
leaq (%rcx,%rdx,8),%rsi
### op add [] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:-
movq %rcx,%rdx
addq $-2147483648,%rdx
### op add [] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:- @far
movq %rcx,%rdx
addq $2147483647,%rdx
### op add [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE
vaddpd %zmm1,%zmm2,%zmm3
### op add [] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF
vaddph %zmm1,%zmm2,%zmm3
### op add [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE
vaddps %zmm1,%zmm2,%zmm3
### op fma [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE
vfmadd231pd %zmm1,%zmm2,%zmm3
### op fma [] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF
vfmadd231ph %zmm1,%zmm2,%zmm3
### op fma [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE
vfmadd231ps %zmm1,%zmm2,%zmm3
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu16 -8192(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu16 8128(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu16 -8192(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu16 8128(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu16 -8192(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu16 8128(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu16 -8192(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu16 8128(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovupd -8192(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovupd 8128(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovupd -8192(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovupd 8128(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovupd -8192(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovupd 8128(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovupd -8192(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovupd 8128(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu16 -8192(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu16 8128(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu16 -8192(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu16 8128(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu16 -8192(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu16 8128(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu16 -8192(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu16 8128(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovups -8192(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovups 8128(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovups -8192(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovups 8128(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovups -8192(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovups 8128(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovups -8192(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovups 8128(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu16 -8192(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu16 8128(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu16 -8192(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu16 8128(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu16 -8192(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu16 8128(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu16 -8192(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu16 8128(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu32 -8192(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu32 8128(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu32 -8192(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu32 8128(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu32 -8192(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu32 8128(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu32 -8192(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu32 8128(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 -8192(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 8128(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 -8192(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 8128(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 -8192(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 8128(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 -8192(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 8128(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu8 -8192(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu8 8128(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu8 -8192(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu8 8128(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu8 -8192(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu8 8128(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu8 -8192(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu8 8128(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu16 -8192(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu16 8128(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu16 -8192(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu16 8128(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu16 -8192(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu16 8128(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu16 -8192(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu16 8128(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu32 -8192(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu32 8128(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu32 -8192(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu32 8128(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu32 -8192(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu32 8128(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu32 -8192(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu32 8128(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 -8192(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 8128(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 -8192(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 8128(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 -8192(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 8128(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 -8192(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 8128(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu8 -8192(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu8 8128(%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu8 -8192(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu8 8128(%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu8 -8192(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu8 8128(%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu8 -8192(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu8 8128(%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu16 -8192(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu16 8128(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovupd -8192(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovupd 8128(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu16 -8192(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu16 8128(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovups -8192(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovups 8128(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu16 -8192(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu16 8128(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu32 -8192(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu32 8128(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 -8192(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 8128(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu8 -8192(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu8 8128(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu16 -8192(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu16 8128(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu32 -8192(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu32 8128(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 -8192(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 8128(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu8 -8192(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu8 8128(%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
vmovsh -128(%rcx,%rdx,1), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
vmovsh 127(%rcx,%rdx,1), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
vmovsh -128(%rcx,%rdx,2), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
vmovsh 127(%rcx,%rdx,2), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
vmovsh -128(%rcx,%rdx,4), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
vmovsh 127(%rcx,%rdx,4), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
vmovsh -128(%rcx,%rdx,8), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
vmovsh 127(%rcx,%rdx,8), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
vmovsd -128(%rcx,%rdx,1), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
vmovsd 127(%rcx,%rdx,1), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
vmovsd -128(%rcx,%rdx,2), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
vmovsd 127(%rcx,%rdx,2), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
vmovsd -128(%rcx,%rdx,4), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
vmovsd 127(%rcx,%rdx,4), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
vmovsd -128(%rcx,%rdx,8), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
vmovsd 127(%rcx,%rdx,8), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
vmovsh -128(%rcx,%rdx,1), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
vmovsh 127(%rcx,%rdx,1), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
vmovsh -128(%rcx,%rdx,2), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
vmovsh 127(%rcx,%rdx,2), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
vmovsh -128(%rcx,%rdx,4), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
vmovsh 127(%rcx,%rdx,4), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
vmovsh -128(%rcx,%rdx,8), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
vmovsh 127(%rcx,%rdx,8), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
vmovss -128(%rcx,%rdx,1), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
vmovss 127(%rcx,%rdx,1), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
vmovss -128(%rcx,%rdx,2), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
vmovss 127(%rcx,%rdx,2), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
vmovss -128(%rcx,%rdx,4), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
vmovss 127(%rcx,%rdx,4), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
vmovss -128(%rcx,%rdx,8), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
vmovss 127(%rcx,%rdx,8), %xmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
movw -128(%rdx,%rsi,1), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
movw 127(%rdx,%rsi,1), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
movw -128(%rdx,%rsi,2), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
movw 127(%rdx,%rsi,2), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
movw -128(%rdx,%rsi,4), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
movw 127(%rdx,%rsi,4), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
movw -128(%rdx,%rsi,8), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
movw 127(%rdx,%rsi,8), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
movl -128(%rdx,%rsi,1), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
movl 127(%rdx,%rsi,1), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
movl -128(%rdx,%rsi,2), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
movl 127(%rdx,%rsi,2), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
movl -128(%rdx,%rsi,4), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
movl 127(%rdx,%rsi,4), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
movl -128(%rdx,%rsi,8), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
movl 127(%rdx,%rsi,8), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
movq -128(%rdx,%rsi,1), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
movq 127(%rdx,%rsi,1), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
movq -128(%rdx,%rsi,2), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
movq 127(%rdx,%rsi,2), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
movq -128(%rdx,%rsi,4), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
movq 127(%rdx,%rsi,4), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
movq -128(%rdx,%rsi,8), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
movq 127(%rdx,%rsi,8), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
movb -128(%rdx,%rsi,1), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
movb 127(%rdx,%rsi,1), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
movb -128(%rdx,%rsi,2), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
movb 127(%rdx,%rsi,2), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
movb -128(%rdx,%rsi,4), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
movb 127(%rdx,%rsi,4), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
movb -128(%rdx,%rsi,8), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
movb 127(%rdx,%rsi,8), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
movw -128(%rdx,%rsi,1), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
movw 127(%rdx,%rsi,1), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
movw -128(%rdx,%rsi,2), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
movw 127(%rdx,%rsi,2), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
movw -128(%rdx,%rsi,4), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
movw 127(%rdx,%rsi,4), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
movw -128(%rdx,%rsi,8), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
movw 127(%rdx,%rsi,8), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
movl -128(%rdx,%rsi,1), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
movl 127(%rdx,%rsi,1), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
movl -128(%rdx,%rsi,2), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
movl 127(%rdx,%rsi,2), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
movl -128(%rdx,%rsi,4), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
movl 127(%rdx,%rsi,4), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
movl -128(%rdx,%rsi,8), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
movl 127(%rdx,%rsi,8), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
movq -128(%rdx,%rsi,1), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
movq 127(%rdx,%rsi,1), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
movq -128(%rdx,%rsi,2), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
movq 127(%rdx,%rsi,2), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
movq -128(%rdx,%rsi,4), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
movq 127(%rdx,%rsi,4), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
movq -128(%rdx,%rsi,8), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
movq 127(%rdx,%rsi,8), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
movb -128(%rdx,%rsi,1), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
movb 127(%rdx,%rsi,1), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
movb -128(%rdx,%rsi,2), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
movb 127(%rdx,%rsi,2), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
movb -128(%rdx,%rsi,4), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
movb 127(%rdx,%rsi,4), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
movb -128(%rdx,%rsi,8), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
movb 127(%rdx,%rsi,8), %rcx
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 -8192(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 8128(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 -8192(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 8128(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 -8192(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 8128(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 -8192(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 8128(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovupd -8192(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovupd 8128(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovupd -8192(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovupd 8128(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovupd -8192(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovupd 8128(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovupd -8192(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovupd 8128(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vbroadcastsd -1024(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vbroadcastsd 1016(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vbroadcastsd -1024(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vbroadcastsd 1016(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vbroadcastsd -1024(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vbroadcastsd 1016(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vbroadcastsd -1024(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vbroadcastsd 1016(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 -8192(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 8128(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 -8192(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 8128(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 -8192(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 8128(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 -8192(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 8128(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovups -8192(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovups 8128(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovups -8192(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovups 8128(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovups -8192(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovups 8128(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovups -8192(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovups 8128(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vbroadcastss -512(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vbroadcastss 508(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vbroadcastss -512(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vbroadcastss 508(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vbroadcastss -512(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vbroadcastss 508(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vbroadcastss -512(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vbroadcastss 508(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 -8192(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 8128(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 -8192(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 8128(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 -8192(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 8128(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 -8192(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 8128(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 -8192(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 8128(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 -8192(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 8128(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 -8192(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 8128(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 -8192(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 8128(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vbroadcastss -512(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vbroadcastss 508(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vbroadcastss -512(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vbroadcastss 508(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vbroadcastss -512(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vbroadcastss 508(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vbroadcastss -512(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vbroadcastss 508(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 -8192(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 8128(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 -8192(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 8128(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 -8192(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 8128(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 -8192(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 8128(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vbroadcastsd -1024(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vbroadcastsd 1016(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vbroadcastsd -1024(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vbroadcastsd 1016(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vbroadcastsd -1024(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vbroadcastsd 1016(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vbroadcastsd -1024(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vbroadcastsd 1016(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 -8192(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 8128(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 -8192(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 8128(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 -8192(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 8128(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 -8192(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 8128(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 -8192(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 8128(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 -8192(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 8128(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 -8192(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 8128(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 -8192(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 8128(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 -8192(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 8128(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 -8192(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 8128(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 -8192(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 8128(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 -8192(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 8128(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vbroadcastss -512(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vbroadcastss 508(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vbroadcastss -512(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vbroadcastss 508(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vbroadcastss -512(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vbroadcastss 508(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vbroadcastss -512(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vbroadcastss 508(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 -8192(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 8128(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 -8192(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 8128(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 -8192(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 8128(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 -8192(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 8128(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vbroadcastsd -1024(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vbroadcastsd 1016(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vbroadcastsd -1024(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vbroadcastsd 1016(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vbroadcastsd -1024(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vbroadcastsd 1016(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vbroadcastsd -1024(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vbroadcastsd 1016(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 -8192(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 8128(%rcx,%rdx,1), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 -8192(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 8128(%rcx,%rdx,2), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 -8192(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 8128(%rcx,%rdx,4), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 -8192(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 8128(%rcx,%rdx,8), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
vmovsh -128(%rcx,%rdx), %xmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
vmovsh 127(%rcx,%rdx), %xmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
vmovsd -128(%rcx,%rdx), %xmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
vmovsd 127(%rcx,%rdx), %xmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
vmovsh -128(%rcx,%rdx), %xmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
vmovsh 127(%rcx,%rdx), %xmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
vmovss -128(%rcx,%rdx), %xmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
vmovss 127(%rcx,%rdx), %xmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movw -128(%rdx,%rsi), %rcx
### op load [GOFFSET,IOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movw 127(%rdx,%rsi), %rcx
### op load [GOFFSET,IOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movl -128(%rdx,%rsi), %rcx
### op load [GOFFSET,IOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movl 127(%rdx,%rsi), %rcx
### op load [GOFFSET,IOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movq -128(%rdx,%rsi), %rcx
### op load [GOFFSET,IOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movq 127(%rdx,%rsi), %rcx
### op load [GOFFSET,IOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movb -128(%rdx,%rsi), %rcx
### op load [GOFFSET,IOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movb 127(%rdx,%rsi), %rcx
### op load [GOFFSET,IOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movw -128(%rdx,%rsi), %rcx
### op load [GOFFSET,IOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movw 127(%rdx,%rsi), %rcx
### op load [GOFFSET,IOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movl -128(%rdx,%rsi), %rcx
### op load [GOFFSET,IOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movl 127(%rdx,%rsi), %rcx
### op load [GOFFSET,IOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movq -128(%rdx,%rsi), %rcx
### op load [GOFFSET,IOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movq 127(%rdx,%rsi), %rcx
### op load [GOFFSET,IOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movb -128(%rdx,%rsi), %rcx
### op load [GOFFSET,IOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movb 127(%rdx,%rsi), %rcx
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 -8192(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 8128(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovupd -8192(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovupd 8128(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vbroadcastsd -1024(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vbroadcastsd 1016(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 -8192(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 8128(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovups -8192(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovups 8128(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vbroadcastss -512(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vbroadcastss 508(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 -8192(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 8128(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 -8192(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 8128(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vbroadcastss -512(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vbroadcastss 508(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 -8192(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 8128(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vbroadcastsd -1024(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vbroadcastsd 1016(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 -8192(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 8128(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 -8192(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 8128(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 -8192(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 8128(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vbroadcastss -512(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vbroadcastss 508(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 -8192(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 8128(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vbroadcastsd -1024(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vbroadcastsd 1016(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 -8192(%rcx,%rdx), %zmm1
### op load [GOFFSET,IOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 8128(%rcx,%rdx), %zmm1
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu16 (%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu16 (%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu16 (%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu16 (%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovupd (%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovupd (%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovupd (%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovupd (%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu16 (%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu16 (%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu16 (%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu16 (%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovups (%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovups (%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovups (%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovups (%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu16 (%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu16 (%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu16 (%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu16 (%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu32 (%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu32 (%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu32 (%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu32 (%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 (%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 (%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 (%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 (%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu8 (%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu8 (%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu8 (%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu8 (%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu16 (%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu16 (%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu16 (%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu16 (%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu32 (%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu32 (%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu32 (%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu32 (%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 (%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 (%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 (%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 (%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu8 (%rcx,%rdx,1), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu8 (%rcx,%rdx,2), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu8 (%rcx,%rdx,4), %zmm1{%k1}{z}
### op load [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu8 (%rcx,%rdx,8), %zmm1{%k1}{z}
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 offreg:REGISTER:GP:UINT64
vmovdqu16 (%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE offreg:REGISTER:GP:UINT64
vmovupd (%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF offreg:REGISTER:GP:UINT64
vmovdqu16 (%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE offreg:REGISTER:GP:UINT64
vmovups (%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 offreg:REGISTER:GP:UINT64
vmovdqu16 (%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 offreg:REGISTER:GP:UINT64
vmovdqu32 (%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 (%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 offreg:REGISTER:GP:UINT64
vmovdqu8 (%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 offreg:REGISTER:GP:UINT64
vmovdqu16 (%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 offreg:REGISTER:GP:UINT64
vmovdqu32 (%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 (%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 offreg:REGISTER:GP:UINT64
vmovdqu8 (%rcx,%rdx), %zmm1{%k1}{z}
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovsh (%rcx,%rdx,1), %xmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovsh (%rcx,%rdx,2), %xmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovsh (%rcx,%rdx,4), %xmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovsh (%rcx,%rdx,8), %xmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovsd (%rcx,%rdx,1), %xmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovsd (%rcx,%rdx,2), %xmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovsd (%rcx,%rdx,4), %xmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovsd (%rcx,%rdx,8), %xmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovsh (%rcx,%rdx,1), %xmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovsh (%rcx,%rdx,2), %xmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovsh (%rcx,%rdx,4), %xmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovsh (%rcx,%rdx,8), %xmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovss (%rcx,%rdx,1), %xmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovss (%rcx,%rdx,2), %xmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovss (%rcx,%rdx,4), %xmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovss (%rcx,%rdx,8), %xmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
movw (%rdx,%rsi,1), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
movw (%rdx,%rsi,2), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
movw (%rdx,%rsi,4), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
movw (%rdx,%rsi,8), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
movl (%rdx,%rsi,1), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
movl (%rdx,%rsi,2), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
movl (%rdx,%rsi,4), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
movl (%rdx,%rsi,8), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
movq (%rdx,%rsi,1), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
movq (%rdx,%rsi,2), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
movq (%rdx,%rsi,4), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
movq (%rdx,%rsi,8), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
movb (%rdx,%rsi,1), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
movb (%rdx,%rsi,2), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
movb (%rdx,%rsi,4), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
movb (%rdx,%rsi,8), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
movw (%rdx,%rsi,1), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
movw (%rdx,%rsi,2), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
movw (%rdx,%rsi,4), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
movw (%rdx,%rsi,8), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
movl (%rdx,%rsi,1), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
movl (%rdx,%rsi,2), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
movl (%rdx,%rsi,4), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
movl (%rdx,%rsi,8), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
movq (%rdx,%rsi,1), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
movq (%rdx,%rsi,2), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
movq (%rdx,%rsi,4), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
movq (%rdx,%rsi,8), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
movb (%rdx,%rsi,1), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
movb (%rdx,%rsi,2), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
movb (%rdx,%rsi,4), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
movb (%rdx,%rsi,8), %rcx
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 (%rcx,%rdx,1), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 (%rcx,%rdx,2), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 (%rcx,%rdx,4), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 (%rcx,%rdx,8), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovupd (%rcx,%rdx,1), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovupd (%rcx,%rdx,2), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovupd (%rcx,%rdx,4), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovupd (%rcx,%rdx,8), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vbroadcastsd (%rcx,%rdx,1), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vbroadcastsd (%rcx,%rdx,2), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vbroadcastsd (%rcx,%rdx,4), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vbroadcastsd (%rcx,%rdx,8), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 (%rcx,%rdx,1), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 (%rcx,%rdx,2), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 (%rcx,%rdx,4), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 (%rcx,%rdx,8), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovups (%rcx,%rdx,1), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovups (%rcx,%rdx,2), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovups (%rcx,%rdx,4), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovups (%rcx,%rdx,8), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vbroadcastss (%rcx,%rdx,1), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vbroadcastss (%rcx,%rdx,2), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vbroadcastss (%rcx,%rdx,4), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vbroadcastss (%rcx,%rdx,8), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 (%rcx,%rdx,1), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 (%rcx,%rdx,2), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 (%rcx,%rdx,4), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 (%rcx,%rdx,8), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 (%rcx,%rdx,1), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 (%rcx,%rdx,2), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 (%rcx,%rdx,4), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 (%rcx,%rdx,8), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vbroadcastss (%rcx,%rdx,1), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vbroadcastss (%rcx,%rdx,2), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vbroadcastss (%rcx,%rdx,4), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vbroadcastss (%rcx,%rdx,8), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 (%rcx,%rdx,1), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 (%rcx,%rdx,2), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 (%rcx,%rdx,4), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 (%rcx,%rdx,8), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vbroadcastsd (%rcx,%rdx,1), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vbroadcastsd (%rcx,%rdx,2), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vbroadcastsd (%rcx,%rdx,4), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vbroadcastsd (%rcx,%rdx,8), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 (%rcx,%rdx,1), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 (%rcx,%rdx,2), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 (%rcx,%rdx,4), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 (%rcx,%rdx,8), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 (%rcx,%rdx,1), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 (%rcx,%rdx,2), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 (%rcx,%rdx,4), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 (%rcx,%rdx,8), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 (%rcx,%rdx,1), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 (%rcx,%rdx,2), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 (%rcx,%rdx,4), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 (%rcx,%rdx,8), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vbroadcastss (%rcx,%rdx,1), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vbroadcastss (%rcx,%rdx,2), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vbroadcastss (%rcx,%rdx,4), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vbroadcastss (%rcx,%rdx,8), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 (%rcx,%rdx,1), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 (%rcx,%rdx,2), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 (%rcx,%rdx,4), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 (%rcx,%rdx,8), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vbroadcastsd (%rcx,%rdx,1), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vbroadcastsd (%rcx,%rdx,2), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vbroadcastsd (%rcx,%rdx,4), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vbroadcastsd (%rcx,%rdx,8), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 (%rcx,%rdx,1), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 (%rcx,%rdx,2), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 (%rcx,%rdx,4), %zmm1
### op load [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 (%rcx,%rdx,8), %zmm1
### op load [GOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovsh (%rcx,%rdx), %xmm1
### op load [GOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovsd (%rcx,%rdx), %xmm1
### op load [GOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovsh (%rcx,%rdx), %xmm1
### op load [GOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovss (%rcx,%rdx), %xmm1
### op load [GOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
movw (%rdx,%rsi), %rcx
### op load [GOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
movl (%rdx,%rsi), %rcx
### op load [GOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
movq (%rdx,%rsi), %rcx
### op load [GOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
movb (%rdx,%rsi), %rcx
### op load [GOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
movw (%rdx,%rsi), %rcx
### op load [GOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
movl (%rdx,%rsi), %rcx
### op load [GOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
movq (%rdx,%rsi), %rcx
### op load [GOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
movb (%rdx,%rsi), %rcx
### op load [GOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 (%rcx,%rdx), %zmm1
### op load [GOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovupd (%rcx,%rdx), %zmm1
### op load [GOFFSET] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vbroadcastsd (%rcx,%rdx), %zmm1
### op load [GOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 (%rcx,%rdx), %zmm1
### op load [GOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovups (%rcx,%rdx), %zmm1
### op load [GOFFSET] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vbroadcastss (%rcx,%rdx), %zmm1
### op load [GOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 (%rcx,%rdx), %zmm1
### op load [GOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 (%rcx,%rdx), %zmm1
### op load [GOFFSET] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vbroadcastss (%rcx,%rdx), %zmm1
### op load [GOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 (%rcx,%rdx), %zmm1
### op load [GOFFSET] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vbroadcastsd (%rcx,%rdx), %zmm1
### op load [GOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 (%rcx,%rdx), %zmm1
### op load [GOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 (%rcx,%rdx), %zmm1
### op load [GOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 (%rcx,%rdx), %zmm1
### op load [GOFFSET] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vbroadcastss (%rcx,%rdx), %zmm1
### op load [GOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 (%rcx,%rdx), %zmm1
### op load [GOFFSET] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vbroadcastsd (%rcx,%rdx), %zmm1
### op load [GOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 (%rcx,%rdx), %zmm1
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:-
vmovdqu16 -8192(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- @far
vmovdqu16 8128(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:-
vmovupd -8192(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- @far
vmovupd 8128(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:-
vmovdqu16 -8192(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- @far
vmovdqu16 8128(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:-
vmovups -8192(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- @far
vmovups 8128(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:-
vmovdqu16 -8192(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- @far
vmovdqu16 8128(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:-
vmovdqu32 -8192(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- @far
vmovdqu32 8128(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:-
vmovdqu8 -8192(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- @far
vmovdqu8 8128(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:-
vmovdqu16 -8192(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- @far
vmovdqu16 8128(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:-
vmovdqu32 -8192(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- @far
vmovdqu32 8128(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:-
vmovdqu8 -8192(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- @far
vmovdqu8 8128(%rcx), %zmm1{%k1}{z}
### op load [IOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
vmovsh -128(%rcx), %xmm1
### op load [IOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
vmovsh 127(%rcx), %xmm1
### op load [IOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
vmovsd -128(%rcx), %xmm1
### op load [IOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
vmovsd 127(%rcx), %xmm1
### op load [IOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
vmovsh -128(%rcx), %xmm1
### op load [IOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
vmovsh 127(%rcx), %xmm1
### op load [IOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
vmovss -128(%rcx), %xmm1
### op load [IOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
vmovss 127(%rcx), %xmm1
### op load [IOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movw -128(%rdx), %rcx
### op load [IOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movw 127(%rdx), %rcx
### op load [IOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movl -128(%rdx), %rcx
### op load [IOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movl 127(%rdx), %rcx
### op load [IOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movq -128(%rdx), %rcx
### op load [IOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movq 127(%rdx), %rcx
### op load [IOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movb -128(%rdx), %rcx
### op load [IOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movb 127(%rdx), %rcx
### op load [IOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movw -128(%rdx), %rcx
### op load [IOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movw 127(%rdx), %rcx
### op load [IOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movl -128(%rdx), %rcx
### op load [IOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movl 127(%rdx), %rcx
### op load [IOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movq -128(%rdx), %rcx
### op load [IOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movq 127(%rdx), %rcx
### op load [IOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movb -128(%rdx), %rcx
### op load [IOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movb 127(%rdx), %rcx
### op load [IOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:BF16{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpinsrw $0, -128(%rcx), %xmm1, %xmm1
### op load [IOFFSET] adreg:REGISTER:VEC:BF16{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpinsrw $7, 127(%rcx), %xmm1, %xmm1
### op load [IOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovupd -8192(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovupd 8128(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vbroadcastsd -1024(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vbroadcastsd 1016(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:DOUBLE{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vmovsd -128(%rcx), %xmm1
### op load [IOFFSET] adreg:REGISTER:VEC:DOUBLE{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vmovhpd 127(%rcx), %xmm1, %xmm1
### op load [IOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:HALF{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpinsrw $0, -128(%rcx), %xmm1, %xmm1
### op load [IOFFSET] adreg:REGISTER:VEC:HALF{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpinsrw $7, 127(%rcx), %xmm1, %xmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovups -8192(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovups 8128(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vbroadcastss -512(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vbroadcastss 508(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINGLE{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vmovss -128(%rcx), %xmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINGLE{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vinsertps $48, 127(%rcx), %xmm1, %xmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINT16{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpinsrw $0, -128(%rcx), %xmm1, %xmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINT16{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpinsrw $7, 127(%rcx), %xmm1, %xmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vbroadcastss -512(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vbroadcastss 508(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINT32{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpinsrd $0, -128(%rcx), %xmm1, %xmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINT32{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpinsrd $3, 127(%rcx), %xmm1, %xmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vbroadcastsd -1024(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vbroadcastsd 1016(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINT64{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpinsrq $0, -128(%rcx), %xmm1, %xmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINT64{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpinsrq $1, 127(%rcx), %xmm1, %xmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINT8{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpinsrb $0, -128(%rcx), %xmm1, %xmm1
### op load [IOFFSET] adreg:REGISTER:VEC:SINT8{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpinsrb $15, 127(%rcx), %xmm1, %xmm1
### op load [IOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:UINT16{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpinsrw $0, -128(%rcx), %xmm1, %xmm1
### op load [IOFFSET] adreg:REGISTER:VEC:UINT16{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpinsrw $7, 127(%rcx), %xmm1, %xmm1
### op load [IOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vbroadcastss -512(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vbroadcastss 508(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:UINT32{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpinsrd $0, -128(%rcx), %xmm1, %xmm1
### op load [IOFFSET] adreg:REGISTER:VEC:UINT32{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpinsrd $3, 127(%rcx), %xmm1, %xmm1
### op load [IOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vbroadcastsd -1024(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vbroadcastsd 1016(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:UINT64{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpinsrq $0, -128(%rcx), %xmm1, %xmm1
### op load [IOFFSET] adreg:REGISTER:VEC:UINT64{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpinsrq $1, 127(%rcx), %xmm1, %xmm1
### op load [IOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1
### op load [IOFFSET] adreg:REGISTER:VEC:UINT8{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpinsrb $0, -128(%rcx), %xmm1, %xmm1
### op load [IOFFSET] adreg:REGISTER:VEC:UINT8{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpinsrb $15, 127(%rcx), %xmm1, %xmm1
### op load [MASK,VINDEX] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE vidxreg:REGISTER:VEC:DOUBLE {it:INT64}
vgatherqpd (%rcx,%zmm2,1), %zmm1{%k1}
### op load [MASK,VINDEX] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE vidxreg:REGISTER:VEC:SINGLE {it:INT32}
vgatherdps (%rcx,%zmm2,1), %zmm1{%k1}
### op load [MASK,VINDEX] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 vidxreg:REGISTER:VEC:SINT32 {it:INT32}
vgatherdps (%rcx,%zmm2,1), %zmm1{%k1}
### op load [MASK,VINDEX] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 vidxreg:REGISTER:VEC:SINT64 {it:INT64}
vgatherqpd (%rcx,%zmm2,1), %zmm1{%k1}
### op load [MASK,VINDEX] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 vidxreg:REGISTER:VEC:UINT32 {it:INT32}
vgatherdps (%rcx,%zmm2,1), %zmm1{%k1}
### op load [MASK,VINDEX] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 vidxreg:REGISTER:VEC:UINT64 {it:INT64}
vgatherqpd (%rcx,%zmm2,1), %zmm1{%k1}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 voffset:IMMEDIATE:-:-
vmovdqu16 -8192(%rcx), %zmm1{%k1}{z}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 voffset:IMMEDIATE:-:- @far
vmovdqu16 8128(%rcx), %zmm1{%k1}{z}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE voffset:IMMEDIATE:-:-
vmovupd -8192(%rcx), %zmm1{%k1}{z}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE voffset:IMMEDIATE:-:- @far
vmovupd 8128(%rcx), %zmm1{%k1}{z}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF voffset:IMMEDIATE:-:-
vmovdqu16 -8192(%rcx), %zmm1{%k1}{z}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF voffset:IMMEDIATE:-:- @far
vmovdqu16 8128(%rcx), %zmm1{%k1}{z}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE voffset:IMMEDIATE:-:-
vmovups -8192(%rcx), %zmm1{%k1}{z}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE voffset:IMMEDIATE:-:- @far
vmovups 8128(%rcx), %zmm1{%k1}{z}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 voffset:IMMEDIATE:-:-
vmovdqu16 -8192(%rcx), %zmm1{%k1}{z}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 voffset:IMMEDIATE:-:- @far
vmovdqu16 8128(%rcx), %zmm1{%k1}{z}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 voffset:IMMEDIATE:-:-
vmovdqu32 -8192(%rcx), %zmm1{%k1}{z}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 voffset:IMMEDIATE:-:- @far
vmovdqu32 8128(%rcx), %zmm1{%k1}{z}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 voffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1{%k1}{z}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1{%k1}{z}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 voffset:IMMEDIATE:-:-
vmovdqu8 -8192(%rcx), %zmm1{%k1}{z}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 voffset:IMMEDIATE:-:- @far
vmovdqu8 8128(%rcx), %zmm1{%k1}{z}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 voffset:IMMEDIATE:-:-
vmovdqu16 -8192(%rcx), %zmm1{%k1}{z}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 voffset:IMMEDIATE:-:- @far
vmovdqu16 8128(%rcx), %zmm1{%k1}{z}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 voffset:IMMEDIATE:-:-
vmovdqu32 -8192(%rcx), %zmm1{%k1}{z}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 voffset:IMMEDIATE:-:- @far
vmovdqu32 8128(%rcx), %zmm1{%k1}{z}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 voffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1{%k1}{z}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1{%k1}{z}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 voffset:IMMEDIATE:-:-
vmovdqu8 -8192(%rcx), %zmm1{%k1}{z}
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 voffset:IMMEDIATE:-:- @far
vmovdqu8 8128(%rcx), %zmm1{%k1}{z}
### op load [MASK] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16
vmovdqu16 (%rcx), %zmm1{%k1}{z}
### op load [MASK] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE
vmovupd (%rcx), %zmm1{%k1}{z}
### op load [MASK] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF
vmovdqu16 (%rcx), %zmm1{%k1}{z}
### op load [MASK] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE
vmovups (%rcx), %zmm1{%k1}{z}
### op load [MASK] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16
vmovdqu16 (%rcx), %zmm1{%k1}{z}
### op load [MASK] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32
vmovdqu32 (%rcx), %zmm1{%k1}{z}
### op load [MASK] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64
vmovdqu64 (%rcx), %zmm1{%k1}{z}
### op load [MASK] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8
vmovdqu8 (%rcx), %zmm1{%k1}{z}
### op load [MASK] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16
vmovdqu16 (%rcx), %zmm1{%k1}{z}
### op load [MASK] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32
vmovdqu32 (%rcx), %zmm1{%k1}{z}
### op load [MASK] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64
vmovdqu64 (%rcx), %zmm1{%k1}{z}
### op load [MASK] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8
vmovdqu8 (%rcx), %zmm1{%k1}{z}
### op load [PARAM] adreg:REGISTER:FP:BF16 param:NAME:-:-
vmovsh %[p], %xmm1
### op load [PARAM] adreg:REGISTER:FP:DOUBLE param:NAME:-:-
vmovsd %[p], %xmm1
### op load [PARAM] adreg:REGISTER:FP:HALF param:NAME:-:-
vmovsh %[p], %xmm1
### op load [PARAM] adreg:REGISTER:FP:SINGLE param:NAME:-:-
vmovss %[p], %xmm1
### op load [PARAM] adreg:REGISTER:GP:SINT16 param:NAME:-:-
movw %[p], %rcx
### op load [PARAM] adreg:REGISTER:GP:SINT32 param:NAME:-:-
movl %[p], %rcx
### op load [PARAM] adreg:REGISTER:GP:SINT64 param:NAME:-:-
movq %[p], %rcx
### op load [PARAM] adreg:REGISTER:GP:SINT8 param:NAME:-:-
movb %[p], %rcx
### op load [PARAM] adreg:REGISTER:GP:UINT16 param:NAME:-:-
movw %[p], %rcx
### op load [PARAM] adreg:REGISTER:GP:UINT32 param:NAME:-:-
movl %[p], %rcx
### op load [PARAM] adreg:REGISTER:GP:UINT64 param:NAME:-:-
movq %[p], %rcx
### op load [PARAM] adreg:REGISTER:GP:UINT8 param:NAME:-:-
movb %[p], %rcx
### op load [VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:BF16{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpinsrw $0, -8192(%rcx), %xmm1, %xmm1
### op load [VOFFSET] adreg:REGISTER:VEC:BF16{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpinsrw $7, 8128(%rcx), %xmm1, %xmm1
### op load [VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovupd -8192(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovupd 8128(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vbroadcastsd -8192(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vbroadcastsd 8128(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:DOUBLE{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vmovsd -8192(%rcx), %xmm1
### op load [VOFFSET] adreg:REGISTER:VEC:DOUBLE{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vmovhpd 8128(%rcx), %xmm1, %xmm1
### op load [VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:HALF{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpinsrw $0, -8192(%rcx), %xmm1, %xmm1
### op load [VOFFSET] adreg:REGISTER:VEC:HALF{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpinsrw $7, 8128(%rcx), %xmm1, %xmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovups -8192(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovups 8128(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vbroadcastss -8192(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vbroadcastss 8128(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINGLE{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vmovss -8192(%rcx), %xmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINGLE{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vinsertps $48, 8128(%rcx), %xmm1, %xmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINT16{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpinsrw $0, -8192(%rcx), %xmm1, %xmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINT16{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpinsrw $7, 8128(%rcx), %xmm1, %xmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vbroadcastss -8192(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vbroadcastss 8128(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINT32{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpinsrd $0, -8192(%rcx), %xmm1, %xmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINT32{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpinsrd $3, 8128(%rcx), %xmm1, %xmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vbroadcastsd -8192(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vbroadcastsd 8128(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINT64{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpinsrq $0, -8192(%rcx), %xmm1, %xmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINT64{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpinsrq $1, 8128(%rcx), %xmm1, %xmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINT8{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpinsrb $0, -8192(%rcx), %xmm1, %xmm1
### op load [VOFFSET] adreg:REGISTER:VEC:SINT8{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpinsrb $15, 8128(%rcx), %xmm1, %xmm1
### op load [VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:UINT16{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpinsrw $0, -8192(%rcx), %xmm1, %xmm1
### op load [VOFFSET] adreg:REGISTER:VEC:UINT16{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpinsrw $7, 8128(%rcx), %xmm1, %xmm1
### op load [VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vbroadcastss -8192(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vbroadcastss 8128(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:UINT32{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpinsrd $0, -8192(%rcx), %xmm1, %xmm1
### op load [VOFFSET] adreg:REGISTER:VEC:UINT32{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpinsrd $3, 8128(%rcx), %xmm1, %xmm1
### op load [VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vbroadcastsd -8192(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vbroadcastsd 8128(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:UINT64{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpinsrq $0, -8192(%rcx), %xmm1, %xmm1
### op load [VOFFSET] adreg:REGISTER:VEC:UINT64{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpinsrq $1, 8128(%rcx), %xmm1, %xmm1
### op load [VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovdqu64 -8192(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 8128(%rcx), %zmm1
### op load [VOFFSET] adreg:REGISTER:VEC:UINT8{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpinsrb $0, -8192(%rcx), %xmm1, %xmm1
### op load [VOFFSET] adreg:REGISTER:VEC:UINT8{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpinsrb $15, 8128(%rcx), %xmm1, %xmm1
### op load [] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64
vmovsh (%rcx), %xmm1
### op load [] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64
vmovsd (%rcx), %xmm1
### op load [] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64
vmovsh (%rcx), %xmm1
### op load [] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64
vmovss (%rcx), %xmm1
### op load [] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64
movw (%rdx), %rcx
### op load [] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64
movl (%rdx), %rcx
### op load [] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64
movq (%rdx), %rcx
### op load [] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64
movb (%rdx), %rcx
### op load [] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64
movw (%rdx), %rcx
### op load [] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64
movl (%rdx), %rcx
### op load [] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64
movq (%rdx), %rcx
### op load [] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64
movb (%rdx), %rcx
### op load [] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64
vmovdqu64 (%rcx), %zmm1
### op load [] adreg:REGISTER:VEC:BF16{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vpinsrw $0, (%rcx), %xmm1, %xmm1
### op load [] adreg:REGISTER:VEC:BF16{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vpinsrw $7, (%rcx), %xmm1, %xmm1
### op load [] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64
vmovupd (%rcx), %zmm1
### op load [] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64
vbroadcastsd (%rcx), %zmm1
### op load [] adreg:REGISTER:VEC:DOUBLE{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vmovsd (%rcx), %xmm1
### op load [] adreg:REGISTER:VEC:DOUBLE{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vmovhpd (%rcx), %xmm1, %xmm1
### op load [] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64
vmovdqu64 (%rcx), %zmm1
### op load [] adreg:REGISTER:VEC:HALF{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vpinsrw $0, (%rcx), %xmm1, %xmm1
### op load [] adreg:REGISTER:VEC:HALF{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vpinsrw $7, (%rcx), %xmm1, %xmm1
### op load [] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64
vmovups (%rcx), %zmm1
### op load [] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64
vbroadcastss (%rcx), %zmm1
### op load [] adreg:REGISTER:VEC:SINGLE{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vmovss (%rcx), %xmm1
### op load [] adreg:REGISTER:VEC:SINGLE{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vinsertps $48, (%rcx), %xmm1, %xmm1
### op load [] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64
vmovdqu64 (%rcx), %zmm1
### op load [] adreg:REGISTER:VEC:SINT16{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vpinsrw $0, (%rcx), %xmm1, %xmm1
### op load [] adreg:REGISTER:VEC:SINT16{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vpinsrw $7, (%rcx), %xmm1, %xmm1
### op load [] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64
vmovdqu64 (%rcx), %zmm1
### op load [] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64
vbroadcastss (%rcx), %zmm1
### op load [] adreg:REGISTER:VEC:SINT32{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vpinsrd $0, (%rcx), %xmm1, %xmm1
### op load [] adreg:REGISTER:VEC:SINT32{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vpinsrd $3, (%rcx), %xmm1, %xmm1
### op load [] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64
vmovdqu64 (%rcx), %zmm1
### op load [] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64
vbroadcastsd (%rcx), %zmm1
### op load [] adreg:REGISTER:VEC:SINT64{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vpinsrq $0, (%rcx), %xmm1, %xmm1
### op load [] adreg:REGISTER:VEC:SINT64{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vpinsrq $1, (%rcx), %xmm1, %xmm1
### op load [] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64
vmovdqu64 (%rcx), %zmm1
### op load [] adreg:REGISTER:VEC:SINT8{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vpinsrb $0, (%rcx), %xmm1, %xmm1
### op load [] adreg:REGISTER:VEC:SINT8{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vpinsrb $15, (%rcx), %xmm1, %xmm1
### op load [] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64
vmovdqu64 (%rcx), %zmm1
### op load [] adreg:REGISTER:VEC:UINT16{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vpinsrw $0, (%rcx), %xmm1, %xmm1
### op load [] adreg:REGISTER:VEC:UINT16{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vpinsrw $7, (%rcx), %xmm1, %xmm1
### op load [] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64
vmovdqu64 (%rcx), %zmm1
### op load [] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64
vbroadcastss (%rcx), %zmm1
### op load [] adreg:REGISTER:VEC:UINT32{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vpinsrd $0, (%rcx), %xmm1, %xmm1
### op load [] adreg:REGISTER:VEC:UINT32{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vpinsrd $3, (%rcx), %xmm1, %xmm1
### op load [] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64
vmovdqu64 (%rcx), %zmm1
### op load [] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64
vbroadcastsd (%rcx), %zmm1
### op load [] adreg:REGISTER:VEC:UINT64{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vpinsrq $0, (%rcx), %xmm1, %xmm1
### op load [] adreg:REGISTER:VEC:UINT64{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vpinsrq $1, (%rcx), %xmm1, %xmm1
### op load [] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64
vmovdqu64 (%rcx), %zmm1
### op load [] adreg:REGISTER:VEC:UINT8{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vpinsrb $0, (%rcx), %xmm1, %xmm1
### op load [] adreg:REGISTER:VEC:UINT8{ILANE,ZEROOTHERS} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vpinsrb $15, (%rcx), %xmm1, %xmm1
### op move [BITS] adreg:REGISTER:GP:UINT16 bdreg:REGISTER:FP:HALF
vmovd %ecx,%xmm1
### op move [BITS] adreg:REGISTER:GP:UINT32 bdreg:REGISTER:FP:SINGLE
vmovd %ecx,%xmm1
### op move [BITS] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:FP:DOUBLE
vmovq %rcx,%xmm1
### op move [PERMUTE] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE {bits:128,pattern:uzp_even,segment:None}
vshuff64x2 $0x88,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE {bits:128,pattern:uzp_odd,segment:None}
vshuff64x2 $0xDD,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE {bits:256,pattern:zip_hi,segment:None}
vshuff64x2 $0xEE,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE {bits:256,pattern:zip_lo,segment:None}
vshuff64x2 $0x44,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE {bits:64,pattern:zip_hi,segment:128}
vunpckhpd %zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE {bits:64,pattern:zip_lo,segment:128}
vunpcklpd %zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {bits:128,pattern:uzp_even,segment:None}
vshuff64x2 $0x88,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {bits:128,pattern:uzp_odd,segment:None}
vshuff64x2 $0xDD,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {bits:256,pattern:zip_hi,segment:None}
vshuff64x2 $0xEE,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {bits:256,pattern:zip_lo,segment:None}
vshuff64x2 $0x44,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {bits:32,pattern:zip_hi,segment:128}
vunpckhps %zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {bits:32,pattern:zip_lo,segment:128}
vunpcklps %zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {bits:64,pattern:zip_hi,segment:128}
vunpckhpd %zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {bits:64,pattern:zip_lo,segment:128}
vunpcklpd %zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {bits:128,pattern:uzp_even,segment:None}
vshuff64x2 $0x88,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {bits:128,pattern:uzp_odd,segment:None}
vshuff64x2 $0xDD,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {bits:256,pattern:zip_hi,segment:None}
vshuff64x2 $0xEE,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {bits:256,pattern:zip_lo,segment:None}
vshuff64x2 $0x44,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {bits:32,pattern:zip_hi,segment:128}
vunpckhps %zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {bits:32,pattern:zip_lo,segment:128}
vunpcklps %zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {bits:64,pattern:zip_hi,segment:128}
vunpckhpd %zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {bits:64,pattern:zip_lo,segment:128}
vunpcklpd %zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 {bits:128,pattern:uzp_even,segment:None}
vshuff64x2 $0x88,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 {bits:128,pattern:uzp_odd,segment:None}
vshuff64x2 $0xDD,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 {bits:256,pattern:zip_hi,segment:None}
vshuff64x2 $0xEE,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 {bits:256,pattern:zip_lo,segment:None}
vshuff64x2 $0x44,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 {bits:64,pattern:zip_hi,segment:128}
vunpckhpd %zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 {bits:64,pattern:zip_lo,segment:128}
vunpcklpd %zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {bits:128,pattern:uzp_even,segment:None}
vshuff64x2 $0x88,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {bits:128,pattern:uzp_odd,segment:None}
vshuff64x2 $0xDD,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {bits:256,pattern:zip_hi,segment:None}
vshuff64x2 $0xEE,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {bits:256,pattern:zip_lo,segment:None}
vshuff64x2 $0x44,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {bits:32,pattern:zip_hi,segment:128}
vunpckhps %zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {bits:32,pattern:zip_lo,segment:128}
vunpcklps %zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {bits:64,pattern:zip_hi,segment:128}
vunpckhpd %zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {bits:64,pattern:zip_lo,segment:128}
vunpcklpd %zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 {bits:128,pattern:uzp_even,segment:None}
vshuff64x2 $0x88,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 {bits:128,pattern:uzp_odd,segment:None}
vshuff64x2 $0xDD,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 {bits:256,pattern:zip_hi,segment:None}
vshuff64x2 $0xEE,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 {bits:256,pattern:zip_lo,segment:None}
vshuff64x2 $0x44,%zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 {bits:64,pattern:zip_hi,segment:128}
vunpckhpd %zmm2,%zmm1,%zmm3
### op move [PERMUTE] adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 {bits:64,pattern:zip_lo,segment:128}
vunpcklpd %zmm2,%zmm1,%zmm3
### op move [] adreg:REGISTER:FP:DOUBLE bdreg:REGISTER:FP:DOUBLE
vmovsd xmm1, xmm2
### op move [] adreg:REGISTER:FP:DOUBLE bdreg:REGISTER:VEC:DOUBLE{BCAST}
vbroadcastsd %xmm1,%zmm1
### op move [] adreg:REGISTER:FP:HALF bdreg:REGISTER:FP:HALF
vmovsh xmm1, xmm2
### op move [] adreg:REGISTER:FP:HALF bdreg:REGISTER:VEC:HALF{BCAST}
vpbroadcastw %xmm1,%zmm1
### op move [] adreg:REGISTER:FP:SINGLE bdreg:REGISTER:FP:SINGLE
vmovss xmm1, xmm2
### op move [] adreg:REGISTER:FP:SINGLE bdreg:REGISTER:VEC:SINGLE{BCAST}
vbroadcastss %xmm1,%zmm1
### op move [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64
movq %rcx, %rdx
### op move [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64
movq %rcx, %rdx
### op move [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE
vmovaps %zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE{IBLOCK} bdreg_block:IMMEDIATE:-:- {bdreg_blocksize:2}
vinsertf32x4 $0,%xmm1,%zmm2,%zmm2
### op move [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE{IBLOCK} bdreg_block:IMMEDIATE:-:- {bdreg_blocksize:2} @far
vinsertf32x4 $3,%xmm1,%zmm2,%zmm2
### op move [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE{IBLOCK} bdreg_block:IMMEDIATE:-:- {bdreg_blocksize:4}
vinsertf64x4 $0,%ymm1,%zmm2,%zmm2
### op move [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE{IBLOCK} bdreg_block:IMMEDIATE:-:- {bdreg_blocksize:4} @far
vinsertf64x4 $1,%ymm1,%zmm2,%zmm2
### op move [] adreg:REGISTER:VEC:DOUBLE{IBLOCKROT} bdreg:REGISTER:VEC:DOUBLE adreg_irot:IMMEDIATE:-:- {adreg_blocksize:2}
vshuff64x2 $147,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:DOUBLE{IBLOCKROT} bdreg:REGISTER:VEC:DOUBLE adreg_irot:IMMEDIATE:-:- {adreg_blocksize:2} @far
vshuff64x2 $57,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:DOUBLE{IBLOCK} bdreg:REGISTER:VEC:DOUBLE adreg_block:IMMEDIATE:-:- {adreg_blocksize:2}
vextractf32x4 $0,%zmm1,%xmm2
### op move [] adreg:REGISTER:VEC:DOUBLE{IBLOCK} bdreg:REGISTER:VEC:DOUBLE adreg_block:IMMEDIATE:-:- {adreg_blocksize:2} @far
vextractf32x4 $3,%zmm1,%xmm2
### op move [] adreg:REGISTER:VEC:DOUBLE{IBLOCK} bdreg:REGISTER:VEC:DOUBLE adreg_block:IMMEDIATE:-:- {adreg_blocksize:4}
vextractf64x4 $0,%zmm1,%ymm2
### op move [] adreg:REGISTER:VEC:DOUBLE{IBLOCK} bdreg:REGISTER:VEC:DOUBLE adreg_block:IMMEDIATE:-:- {adreg_blocksize:4} @far
vextractf64x4 $1,%zmm1,%ymm2
### op move [] adreg:REGISTER:VEC:DOUBLE{IBLOCK} bdreg:REGISTER:VEC:DOUBLE{BCAST,BLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:2,bdreg_blocksize:2}
vshuff32x4 $0x0,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:DOUBLE{IBLOCK} bdreg:REGISTER:VEC:DOUBLE{BCAST,BLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:2,bdreg_blocksize:2} @far
vshuff32x4 $0xff,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:DOUBLE{IBLOCK} bdreg:REGISTER:VEC:DOUBLE{BCAST,BLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:4,bdreg_blocksize:4}
vshuff64x2 $0x44,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:DOUBLE{IBLOCK} bdreg:REGISTER:VEC:DOUBLE{BCAST,BLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:4,bdreg_blocksize:4} @far
vshuff64x2 $0xee,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:DOUBLE{ILANEROT} bdreg:REGISTER:VEC:DOUBLE adreg_irot:IMMEDIATE:-:-
valignq $7,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:DOUBLE{ILANEROT} bdreg:REGISTER:VEC:DOUBLE adreg_irot:IMMEDIATE:-:- @far
valignq $1,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:DOUBLE{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:DOUBLE adreg_irot:IMMEDIATE:-:-
valignq $7,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:DOUBLE{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:DOUBLE adreg_irot:IMMEDIATE:-:- @far
valignq $1,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE
vmovaps %zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE{IBLOCK} bdreg_block:IMMEDIATE:-:- {bdreg_blocksize:4}
vinsertf32x4 $0,%xmm1,%zmm2,%zmm2
### op move [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE{IBLOCK} bdreg_block:IMMEDIATE:-:- {bdreg_blocksize:4} @far
vinsertf32x4 $3,%xmm1,%zmm2,%zmm2
### op move [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE{IBLOCK} bdreg_block:IMMEDIATE:-:- {bdreg_blocksize:8}
vinsertf64x4 $0,%ymm1,%zmm2,%zmm2
### op move [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE{IBLOCK} bdreg_block:IMMEDIATE:-:- {bdreg_blocksize:8} @far
vinsertf64x4 $1,%ymm1,%zmm2,%zmm2
### op move [] adreg:REGISTER:VEC:SINGLE{IBLOCKROT} bdreg:REGISTER:VEC:SINGLE adreg_irot:IMMEDIATE:-:- {adreg_blocksize:4}
vshuff64x2 $147,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:SINGLE{IBLOCKROT} bdreg:REGISTER:VEC:SINGLE adreg_irot:IMMEDIATE:-:- {adreg_blocksize:4} @far
vshuff64x2 $57,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:SINGLE{IBLOCK} bdreg:REGISTER:VEC:SINGLE adreg_block:IMMEDIATE:-:- {adreg_blocksize:4}
vextractf32x4 $0,%zmm1,%xmm2
### op move [] adreg:REGISTER:VEC:SINGLE{IBLOCK} bdreg:REGISTER:VEC:SINGLE adreg_block:IMMEDIATE:-:- {adreg_blocksize:4} @far
vextractf32x4 $3,%zmm1,%xmm2
### op move [] adreg:REGISTER:VEC:SINGLE{IBLOCK} bdreg:REGISTER:VEC:SINGLE adreg_block:IMMEDIATE:-:- {adreg_blocksize:8}
vextractf64x4 $0,%zmm1,%ymm2
### op move [] adreg:REGISTER:VEC:SINGLE{IBLOCK} bdreg:REGISTER:VEC:SINGLE adreg_block:IMMEDIATE:-:- {adreg_blocksize:8} @far
vextractf64x4 $1,%zmm1,%ymm2
### op move [] adreg:REGISTER:VEC:SINGLE{IBLOCK} bdreg:REGISTER:VEC:SINGLE{BCAST,BLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:4,bdreg_blocksize:4}
vshuff32x4 $0x0,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:SINGLE{IBLOCK} bdreg:REGISTER:VEC:SINGLE{BCAST,BLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:4,bdreg_blocksize:4} @far
vshuff32x4 $0xff,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:SINGLE{IBLOCK} bdreg:REGISTER:VEC:SINGLE{BCAST,BLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:8,bdreg_blocksize:8}
vshuff64x2 $0x44,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:SINGLE{IBLOCK} bdreg:REGISTER:VEC:SINGLE{BCAST,BLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:8,bdreg_blocksize:8} @far
vshuff64x2 $0xee,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:SINGLE{ILANEROT} bdreg:REGISTER:VEC:SINGLE adreg_irot:IMMEDIATE:-:-
valignd $15,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:SINGLE{ILANEROT} bdreg:REGISTER:VEC:SINGLE adreg_irot:IMMEDIATE:-:- @far
valignd $1,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:SINGLE{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINGLE adreg_irot:IMMEDIATE:-:-
valignd $15,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:SINGLE{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINGLE adreg_irot:IMMEDIATE:-:- @far
valignd $1,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:SINT32{ILANEROT} bdreg:REGISTER:VEC:SINT32 adreg_irot:IMMEDIATE:-:-
valignd $15,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:SINT32{ILANEROT} bdreg:REGISTER:VEC:SINT32 adreg_irot:IMMEDIATE:-:- @far
valignd $1,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:SINT32{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINT32 adreg_irot:IMMEDIATE:-:-
valignd $15,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:SINT32{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINT32 adreg_irot:IMMEDIATE:-:- @far
valignd $1,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:SINT64{ILANEROT} bdreg:REGISTER:VEC:SINT64 adreg_irot:IMMEDIATE:-:-
valignq $7,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:SINT64{ILANEROT} bdreg:REGISTER:VEC:SINT64 adreg_irot:IMMEDIATE:-:- @far
valignq $1,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:SINT64{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINT64 adreg_irot:IMMEDIATE:-:-
valignq $7,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:SINT64{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINT64 adreg_irot:IMMEDIATE:-:- @far
valignq $1,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:UINT32{ILANEROT} bdreg:REGISTER:VEC:UINT32 adreg_irot:IMMEDIATE:-:-
valignd $15,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:UINT32{ILANEROT} bdreg:REGISTER:VEC:UINT32 adreg_irot:IMMEDIATE:-:- @far
valignd $1,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:UINT32{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:UINT32 adreg_irot:IMMEDIATE:-:-
valignd $15,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:UINT32{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:UINT32 adreg_irot:IMMEDIATE:-:- @far
valignd $1,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:UINT64{ILANEROT} bdreg:REGISTER:VEC:UINT64 adreg_irot:IMMEDIATE:-:-
valignq $7,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:UINT64{ILANEROT} bdreg:REGISTER:VEC:UINT64 adreg_irot:IMMEDIATE:-:- @far
valignq $1,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:UINT64{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:UINT64 adreg_irot:IMMEDIATE:-:-
valignq $7,%zmm1,%zmm1,%zmm2
### op move [] adreg:REGISTER:VEC:UINT64{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:UINT64 adreg_irot:IMMEDIATE:-:- @far
valignq $1,%zmm1,%zmm1,%zmm2
### op mul [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64
movq %rcx,%rsi
imulq %rdx,%rsi
### op mul [] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:-
imulq $-2147483648,%rcx,%rdx
### op mul [] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:- @far
imulq $2147483647,%rcx,%rdx
### op mul [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64
movq %rcx,%rsi
imulq %rdx,%rsi
### op mul [] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:-
imulq $-2147483648,%rcx,%rdx
### op mul [] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:- @far
imulq $2147483647,%rcx,%rdx
### op mul [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE
vmulpd %zmm1,%zmm2,%zmm3
### op mul [] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF
vmulph %zmm1,%zmm2,%zmm3
### op mul [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE
vmulps %zmm1,%zmm2,%zmm3
### op prefetch [GOFFSET] agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
prefetcht0 (%rcx,%rdx)
### op prefetch [IOFFSET] agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
prefetcht0 -128(%rcx)
### op prefetch [IOFFSET] agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
prefetcht0 127(%rcx)
### op prefetch [] agreg:REGISTER:GP:UINT64
prefetcht0 (%rcx)
### op set [CONSTMASK] dreg:REGISTER:MASK:DOUBLE count:IMMEDIATE:-:- {mask:first}
kxnorw %k1,%k1,%k1
kshiftrw $15,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:DOUBLE count:IMMEDIATE:-:- {mask:first} @far
kxnorw %k1,%k1,%k1
kshiftrw $8,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:DOUBLE {mask:allfalse}
kxorw %k1,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:DOUBLE {mask:alltrue}
kxnorw %k1,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:HALF {mask:allfalse}
kxorw %k1,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:HALF {mask:alltrue}
kxnorw %k1,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:SINGLE count:IMMEDIATE:-:- {mask:first}
kxnorw %k1,%k1,%k1
kshiftrw $15,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:SINGLE count:IMMEDIATE:-:- {mask:first} @far
kxnorw %k1,%k1,%k1
kshiftrw $0,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:SINGLE {mask:allfalse}
kxorw %k1,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:SINGLE {mask:alltrue}
kxnorw %k1,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT16 {mask:allfalse}
kxorw %k1,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT16 {mask:alltrue}
kxnorw %k1,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT32 count:IMMEDIATE:-:- {mask:first}
kxnorw %k1,%k1,%k1
kshiftrw $15,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT32 count:IMMEDIATE:-:- {mask:first} @far
kxnorw %k1,%k1,%k1
kshiftrw $0,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT32 {mask:allfalse}
kxorw %k1,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT32 {mask:alltrue}
kxnorw %k1,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT64 count:IMMEDIATE:-:- {mask:first}
kxnorw %k1,%k1,%k1
kshiftrw $15,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT64 count:IMMEDIATE:-:- {mask:first} @far
kxnorw %k1,%k1,%k1
kshiftrw $8,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT64 {mask:allfalse}
kxorw %k1,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT64 {mask:alltrue}
kxnorw %k1,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT8 {mask:allfalse}
kxorw %k1,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT8 {mask:alltrue}
kxnorw %k1,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT16 {mask:allfalse}
kxorw %k1,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT16 {mask:alltrue}
kxnorw %k1,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT32 count:IMMEDIATE:-:- {mask:first}
kxnorw %k1,%k1,%k1
kshiftrw $15,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT32 count:IMMEDIATE:-:- {mask:first} @far
kxnorw %k1,%k1,%k1
kshiftrw $0,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT32 {mask:allfalse}
kxorw %k1,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT32 {mask:alltrue}
kxnorw %k1,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT64 count:IMMEDIATE:-:- {mask:first}
kxnorw %k1,%k1,%k1
kshiftrw $15,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT64 count:IMMEDIATE:-:- {mask:first} @far
kxnorw %k1,%k1,%k1
kshiftrw $8,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT64 {mask:allfalse}
kxorw %k1,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT64 {mask:alltrue}
kxnorw %k1,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT8 {mask:allfalse}
kxorw %k1,%k1,%k1
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT8 {mask:alltrue}
kxnorw %k1,%k1,%k1
### op set [CONST] dreg:REGISTER:FP:DOUBLE {constant:one}
vpternlogd $0xff,%xmm1,%xmm1,%xmm1
vpsllq $54,%xmm1,%xmm1
vpsrlq $2,%xmm1,%xmm1
### op set [CONST] dreg:REGISTER:FP:DOUBLE {constant:zero}
vpxord %xmm1,%xmm1,%xmm1
### op set [CONST] dreg:REGISTER:FP:HALF {constant:one}
vpternlogd $0xff,%xmm1,%xmm1,%xmm1
vpsllw $12,%xmm1,%xmm1
vpsrlw $2,%xmm1,%xmm1
### op set [CONST] dreg:REGISTER:FP:HALF {constant:zero}
vpxord %xmm1,%xmm1,%xmm1
### op set [CONST] dreg:REGISTER:FP:SINGLE {constant:one}
vpternlogd $0xff,%xmm1,%xmm1,%xmm1
vpslld $25,%xmm1,%xmm1
vpsrld $2,%xmm1,%xmm1
### op set [CONST] dreg:REGISTER:FP:SINGLE {constant:zero}
vpxord %xmm1,%xmm1,%xmm1
### op set [CONST] dreg:REGISTER:GP:SINT64 value:IMMEDIATE:-:-
movq $-9223372036854775808,%rcx
### op set [CONST] dreg:REGISTER:GP:SINT64 value:IMMEDIATE:-:- @far
movq $-1,%rcx
### op set [CONST] dreg:REGISTER:GP:SINT64 {constant:one}
movq $1,%rcx
### op set [CONST] dreg:REGISTER:GP:SINT64 {constant:zero}
movq $0,%rcx
### op set [CONST] dreg:REGISTER:GP:UINT64 value:IMMEDIATE:-:-
movq $-9223372036854775808,%rcx
### op set [CONST] dreg:REGISTER:GP:UINT64 value:IMMEDIATE:-:- @far
movq $-1,%rcx
### op set [CONST] dreg:REGISTER:GP:UINT64 {constant:one}
movq $1,%rcx
### op set [CONST] dreg:REGISTER:GP:UINT64 {constant:zero}
movq $0,%rcx
### op set [CONST] dreg:REGISTER:VEC:DOUBLE {constant:one}
vpternlogd $0xff,%zmm1,%zmm1,%zmm1
vpsllq $54,%zmm1,%zmm1
vpsrlq $2,%zmm1,%zmm1
### op set [CONST] dreg:REGISTER:VEC:DOUBLE {constant:zero}
vpxorq %zmm1,%zmm1,%zmm1
### op set [CONST] dreg:REGISTER:VEC:HALF {constant:one}
vpternlogd $0xff,%zmm1,%zmm1,%zmm1
vpsllw $12,%zmm1,%zmm1
vpsrlw $2,%zmm1,%zmm1
### op set [CONST] dreg:REGISTER:VEC:HALF {constant:zero}
vpxorq %zmm1,%zmm1,%zmm1
### op set [CONST] dreg:REGISTER:VEC:SINGLE {constant:one}
vpternlogd $0xff,%zmm1,%zmm1,%zmm1
vpslld $25,%zmm1,%zmm1
vpsrld $2,%zmm1,%zmm1
### op set [CONST] dreg:REGISTER:VEC:SINGLE {constant:zero}
vpxorq %zmm1,%zmm1,%zmm1
### op set [CONST] dreg:REGISTER:VEC:SINT16 {constant:one}
vpternlogd $0xff,%zmm1,%zmm1,%zmm1
vpsrlw $15,%zmm1,%zmm1
### op set [CONST] dreg:REGISTER:VEC:SINT16 {constant:zero}
vpxorq %zmm1,%zmm1,%zmm1
### op set [CONST] dreg:REGISTER:VEC:SINT32 {constant:one}
vpternlogd $0xff,%zmm1,%zmm1,%zmm1
vpsrld $31,%zmm1,%zmm1
### op set [CONST] dreg:REGISTER:VEC:SINT32 {constant:zero}
vpxorq %zmm1,%zmm1,%zmm1
### op set [CONST] dreg:REGISTER:VEC:SINT64 {constant:one}
vpternlogd $0xff,%zmm1,%zmm1,%zmm1
vpsrlq $63,%zmm1,%zmm1
### op set [CONST] dreg:REGISTER:VEC:SINT64 {constant:zero}
vpxorq %zmm1,%zmm1,%zmm1
### op set [CONST] dreg:REGISTER:VEC:SINT8 {constant:one}
vpternlogd $0xff,%zmm1,%zmm1,%zmm1
vpabsb %zmm1,%zmm1
### op set [CONST] dreg:REGISTER:VEC:SINT8 {constant:zero}
vpxorq %zmm1,%zmm1,%zmm1
### op set [CONST] dreg:REGISTER:VEC:UINT16 {constant:one}
vpternlogd $0xff,%zmm1,%zmm1,%zmm1
vpsrlw $15,%zmm1,%zmm1
### op set [CONST] dreg:REGISTER:VEC:UINT16 {constant:zero}
vpxorq %zmm1,%zmm1,%zmm1
### op set [CONST] dreg:REGISTER:VEC:UINT32 {constant:one}
vpternlogd $0xff,%zmm1,%zmm1,%zmm1
vpsrld $31,%zmm1,%zmm1
### op set [CONST] dreg:REGISTER:VEC:UINT32 {constant:zero}
vpxorq %zmm1,%zmm1,%zmm1
### op set [CONST] dreg:REGISTER:VEC:UINT64 {constant:one}
vpternlogd $0xff,%zmm1,%zmm1,%zmm1
vpsrlq $63,%zmm1,%zmm1
### op set [CONST] dreg:REGISTER:VEC:UINT64 {constant:zero}
vpxorq %zmm1,%zmm1,%zmm1
### op set [CONST] dreg:REGISTER:VEC:UINT8 {constant:one}
vpternlogd $0xff,%zmm1,%zmm1,%zmm1
vpabsb %zmm1,%zmm1
### op set [CONST] dreg:REGISTER:VEC:UINT8 {constant:zero}
vpxorq %zmm1,%zmm1,%zmm1
### op set [MASKAVL] dreg:REGISTER:MASK:DOUBLE avlreg:REGISTER:GP:UINT64 tmpreg:REGISTER:GP:UINT64
movq $-1,%rdx
bzhiq %rcx,%rdx,%rdx
kmovw %edx,%k1
### op set [MASKAVL] dreg:REGISTER:MASK:SINGLE avlreg:REGISTER:GP:UINT64 tmpreg:REGISTER:GP:UINT64
movq $-1,%rdx
bzhiq %rcx,%rdx,%rdx
kmovw %edx,%k1
### op set [MASKAVL] dreg:REGISTER:MASK:SINT32 avlreg:REGISTER:GP:UINT64 tmpreg:REGISTER:GP:UINT64
movq $-1,%rdx
bzhiq %rcx,%rdx,%rdx
kmovw %edx,%k1
### op set [MASKAVL] dreg:REGISTER:MASK:SINT64 avlreg:REGISTER:GP:UINT64 tmpreg:REGISTER:GP:UINT64
movq $-1,%rdx
bzhiq %rcx,%rdx,%rdx
kmovw %edx,%k1
### op set [MASKAVL] dreg:REGISTER:MASK:UINT32 avlreg:REGISTER:GP:UINT64 tmpreg:REGISTER:GP:UINT64
movq $-1,%rdx
bzhiq %rcx,%rdx,%rdx
kmovw %edx,%k1
### op set [MASKAVL] dreg:REGISTER:MASK:UINT64 avlreg:REGISTER:GP:UINT64 tmpreg:REGISTER:GP:UINT64
movq $-1,%rdx
bzhiq %rcx,%rdx,%rdx
kmovw %edx,%k1
### op set [STINDEX] dreg:REGISTER:VEC:DOUBLE streg:REGISTER:GP:UINT64
vpbroadcastq %rcx,%zmm1
vpmuludq .iota_64x8(%rip),%zmm1,%zmm1
### op set [STINDEX] dreg:REGISTER:VEC:HALF streg:REGISTER:GP:UINT64
vpbroadcastw %ecx,%zmm1
vpmullw .iota_16x32(%rip),%zmm1,%zmm1
### op set [STINDEX] dreg:REGISTER:VEC:SINGLE streg:REGISTER:GP:UINT64
vpbroadcastd %ecx,%zmm1
vpmulld .iota_32x16(%rip),%zmm1,%zmm1
### op set [STINDEX] dreg:REGISTER:VEC:SINT16 streg:REGISTER:GP:UINT64
vpbroadcastw %ecx,%zmm1
vpmullw .iota_16x32(%rip),%zmm1,%zmm1
### op set [STINDEX] dreg:REGISTER:VEC:SINT32 streg:REGISTER:GP:UINT64
vpbroadcastd %ecx,%zmm1
vpmulld .iota_32x16(%rip),%zmm1,%zmm1
### op set [STINDEX] dreg:REGISTER:VEC:SINT64 streg:REGISTER:GP:UINT64
vpbroadcastq %rcx,%zmm1
vpmuludq .iota_64x8(%rip),%zmm1,%zmm1
### op set [STINDEX] dreg:REGISTER:VEC:UINT16 streg:REGISTER:GP:UINT64
vpbroadcastw %ecx,%zmm1
vpmullw .iota_16x32(%rip),%zmm1,%zmm1
### op set [STINDEX] dreg:REGISTER:VEC:UINT32 streg:REGISTER:GP:UINT64
vpbroadcastd %ecx,%zmm1
vpmulld .iota_32x16(%rip),%zmm1,%zmm1
### op set [STINDEX] dreg:REGISTER:VEC:UINT64 streg:REGISTER:GP:UINT64
vpbroadcastq %rcx,%zmm1
vpmuludq .iota_64x8(%rip),%zmm1,%zmm1
### op set [VLEN] dreg:REGISTER:GP:UINT64
movq $8,%rcx
### op shift [SHL] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:-
movq %rcx,%rdx
shlq $0,%rdx
### op shift [SHL] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:- @far
movq %rcx,%rdx
shlq $63,%rdx
### op shift [SHL] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:-
movq %rcx,%rdx
shlq $0,%rdx
### op shift [SHL] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:- @far
movq %rcx,%rdx
shlq $63,%rdx
### op shift [SHR] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:-
movq %rcx,%rdx
shrq $0,%rdx
### op shift [SHR] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:- @far
movq %rcx,%rdx
shrq $63,%rdx
### op shift [SHR] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:-
movq %rcx,%rdx
shrq $0,%rdx
### op shift [SHR] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:- @far
movq %rcx,%rdx
shrq $63,%rdx
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu16 %zmm1, -8192(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu16 %zmm1, 8128(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu16 %zmm1, -8192(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu16 %zmm1, 8128(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu16 %zmm1, -8192(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu16 %zmm1, 8128(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu16 %zmm1, -8192(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu16 %zmm1, 8128(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovupd %zmm1, -8192(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovupd %zmm1, 8128(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovupd %zmm1, -8192(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovupd %zmm1, 8128(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovupd %zmm1, -8192(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovupd %zmm1, 8128(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovupd %zmm1, -8192(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovupd %zmm1, 8128(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu16 %zmm1, -8192(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu16 %zmm1, 8128(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu16 %zmm1, -8192(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu16 %zmm1, 8128(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu16 %zmm1, -8192(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu16 %zmm1, 8128(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu16 %zmm1, -8192(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu16 %zmm1, 8128(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovups %zmm1, -8192(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovups %zmm1, 8128(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovups %zmm1, -8192(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovups %zmm1, 8128(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovups %zmm1, -8192(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovups %zmm1, 8128(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovups %zmm1, -8192(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovups %zmm1, 8128(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu16 %zmm1, -8192(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu16 %zmm1, 8128(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu16 %zmm1, -8192(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu16 %zmm1, 8128(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu16 %zmm1, -8192(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu16 %zmm1, 8128(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu16 %zmm1, -8192(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu16 %zmm1, 8128(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu32 %zmm1, -8192(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu32 %zmm1, 8128(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu32 %zmm1, -8192(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu32 %zmm1, 8128(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu32 %zmm1, -8192(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu32 %zmm1, 8128(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu32 %zmm1, -8192(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu32 %zmm1, 8128(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu8 %zmm1, -8192(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu8 %zmm1, 8128(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu8 %zmm1, -8192(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu8 %zmm1, 8128(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu8 %zmm1, -8192(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu8 %zmm1, 8128(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu8 %zmm1, -8192(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu8 %zmm1, 8128(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu16 %zmm1, -8192(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu16 %zmm1, 8128(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu16 %zmm1, -8192(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu16 %zmm1, 8128(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu16 %zmm1, -8192(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu16 %zmm1, 8128(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu16 %zmm1, -8192(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu16 %zmm1, 8128(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu32 %zmm1, -8192(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu32 %zmm1, 8128(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu32 %zmm1, -8192(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu32 %zmm1, 8128(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu32 %zmm1, -8192(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu32 %zmm1, 8128(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu32 %zmm1, -8192(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu32 %zmm1, 8128(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu8 %zmm1, -8192(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu8 %zmm1, 8128(%rcx,%rdx,1){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu8 %zmm1, -8192(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu8 %zmm1, 8128(%rcx,%rdx,2){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu8 %zmm1, -8192(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu8 %zmm1, 8128(%rcx,%rdx,4){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu8 %zmm1, -8192(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu8 %zmm1, 8128(%rcx,%rdx,8){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu16 %zmm1, -8192(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu16 %zmm1, 8128(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovupd %zmm1, -8192(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovupd %zmm1, 8128(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu16 %zmm1, -8192(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu16 %zmm1, 8128(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovups %zmm1, -8192(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovups %zmm1, 8128(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu16 %zmm1, -8192(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu16 %zmm1, 8128(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu32 %zmm1, -8192(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu32 %zmm1, 8128(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, -8192(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu8 %zmm1, -8192(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu8 %zmm1, 8128(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu16 %zmm1, -8192(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu16 %zmm1, 8128(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu32 %zmm1, -8192(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu32 %zmm1, 8128(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, -8192(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu8 %zmm1, -8192(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,MASK] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu8 %zmm1, 8128(%rcx,%rdx){%k1}
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
vmovsh %xmm1, -128(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
vmovsh %xmm1, 127(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
vmovsh %xmm1, -128(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
vmovsh %xmm1, 127(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
vmovsh %xmm1, -128(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
vmovsh %xmm1, 127(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
vmovsh %xmm1, -128(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
vmovsh %xmm1, 127(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
vmovsd %xmm1, -128(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
vmovsd %xmm1, 127(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
vmovsd %xmm1, -128(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
vmovsd %xmm1, 127(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
vmovsd %xmm1, -128(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
vmovsd %xmm1, 127(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
vmovsd %xmm1, -128(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
vmovsd %xmm1, 127(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
vmovsh %xmm1, -128(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
vmovsh %xmm1, 127(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
vmovsh %xmm1, -128(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
vmovsh %xmm1, 127(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
vmovsh %xmm1, -128(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
vmovsh %xmm1, 127(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
vmovsh %xmm1, -128(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
vmovsh %xmm1, 127(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
vmovss %xmm1, -128(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
vmovss %xmm1, 127(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
vmovss %xmm1, -128(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
vmovss %xmm1, 127(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
vmovss %xmm1, -128(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
vmovss %xmm1, 127(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
vmovss %xmm1, -128(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
vmovss %xmm1, 127(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
movw %rcx, -128(%rdx,%rsi,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
movw %rcx, 127(%rdx,%rsi,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
movw %rcx, -128(%rdx,%rsi,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
movw %rcx, 127(%rdx,%rsi,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
movw %rcx, -128(%rdx,%rsi,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
movw %rcx, 127(%rdx,%rsi,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
movw %rcx, -128(%rdx,%rsi,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
movw %rcx, 127(%rdx,%rsi,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
movl %rcx, -128(%rdx,%rsi,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
movl %rcx, 127(%rdx,%rsi,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
movl %rcx, -128(%rdx,%rsi,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
movl %rcx, 127(%rdx,%rsi,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
movl %rcx, -128(%rdx,%rsi,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
movl %rcx, 127(%rdx,%rsi,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
movl %rcx, -128(%rdx,%rsi,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
movl %rcx, 127(%rdx,%rsi,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
movq %rcx, -128(%rdx,%rsi,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
movq %rcx, 127(%rdx,%rsi,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
movq %rcx, -128(%rdx,%rsi,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
movq %rcx, 127(%rdx,%rsi,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
movq %rcx, -128(%rdx,%rsi,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
movq %rcx, 127(%rdx,%rsi,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
movq %rcx, -128(%rdx,%rsi,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
movq %rcx, 127(%rdx,%rsi,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
movb %rcx, -128(%rdx,%rsi,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
movb %rcx, 127(%rdx,%rsi,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
movb %rcx, -128(%rdx,%rsi,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
movb %rcx, 127(%rdx,%rsi,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
movb %rcx, -128(%rdx,%rsi,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
movb %rcx, 127(%rdx,%rsi,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
movb %rcx, -128(%rdx,%rsi,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
movb %rcx, 127(%rdx,%rsi,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
movw %rcx, -128(%rdx,%rsi,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
movw %rcx, 127(%rdx,%rsi,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
movw %rcx, -128(%rdx,%rsi,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
movw %rcx, 127(%rdx,%rsi,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
movw %rcx, -128(%rdx,%rsi,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
movw %rcx, 127(%rdx,%rsi,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
movw %rcx, -128(%rdx,%rsi,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
movw %rcx, 127(%rdx,%rsi,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
movl %rcx, -128(%rdx,%rsi,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
movl %rcx, 127(%rdx,%rsi,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
movl %rcx, -128(%rdx,%rsi,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
movl %rcx, 127(%rdx,%rsi,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
movl %rcx, -128(%rdx,%rsi,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
movl %rcx, 127(%rdx,%rsi,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
movl %rcx, -128(%rdx,%rsi,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
movl %rcx, 127(%rdx,%rsi,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
movq %rcx, -128(%rdx,%rsi,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
movq %rcx, 127(%rdx,%rsi,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
movq %rcx, -128(%rdx,%rsi,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
movq %rcx, 127(%rdx,%rsi,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
movq %rcx, -128(%rdx,%rsi,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
movq %rcx, 127(%rdx,%rsi,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
movq %rcx, -128(%rdx,%rsi,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
movq %rcx, 127(%rdx,%rsi,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1}
movb %rcx, -128(%rdx,%rsi,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:1} @far
movb %rcx, 127(%rdx,%rsi,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2}
movb %rcx, -128(%rdx,%rsi,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:2} @far
movb %rcx, 127(%rdx,%rsi,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4}
movb %rcx, -128(%rdx,%rsi,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:4} @far
movb %rcx, 127(%rdx,%rsi,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8}
movb %rcx, -128(%rdx,%rsi,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 {scale_factor:8} @far
movb %rcx, 127(%rdx,%rsi,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovupd %zmm1, -8192(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovupd %zmm1, 8128(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovupd %zmm1, -8192(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovupd %zmm1, 8128(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovupd %zmm1, -8192(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovupd %zmm1, 8128(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovupd %zmm1, -8192(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovupd %zmm1, 8128(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovups %zmm1, -8192(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovups %zmm1, 8128(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovups %zmm1, -8192(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovups %zmm1, 8128(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovups %zmm1, -8192(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovups %zmm1, 8128(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovups %zmm1, -8192(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovups %zmm1, 8128(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:1} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,1)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:2} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,2)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:4} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,4)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, -8192(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 {scale_factor:8} @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx,8)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
vmovsh %xmm1, -128(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
vmovsh %xmm1, 127(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
vmovsd %xmm1, -128(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
vmovsd %xmm1, 127(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
vmovsh %xmm1, -128(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
vmovsh %xmm1, 127(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
vmovss %xmm1, -128(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
vmovss %xmm1, 127(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movw %rcx, -128(%rdx,%rsi)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movw %rcx, 127(%rdx,%rsi)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movl %rcx, -128(%rdx,%rsi)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movl %rcx, 127(%rdx,%rsi)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movq %rcx, -128(%rdx,%rsi)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movq %rcx, 127(%rdx,%rsi)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movb %rcx, -128(%rdx,%rsi)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movb %rcx, 127(%rdx,%rsi)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movw %rcx, -128(%rdx,%rsi)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movw %rcx, 127(%rdx,%rsi)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movl %rcx, -128(%rdx,%rsi)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movl %rcx, 127(%rdx,%rsi)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movq %rcx, -128(%rdx,%rsi)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movq %rcx, 127(%rdx,%rsi)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movb %rcx, -128(%rdx,%rsi)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movb %rcx, 127(%rdx,%rsi)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, -8192(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovupd %zmm1, -8192(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovupd %zmm1, 8128(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, -8192(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovups %zmm1, -8192(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovups %zmm1, 8128(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, -8192(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, -8192(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, -8192(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, -8192(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, -8192(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, -8192(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, -8192(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, -8192(%rcx,%rdx)
### op store [GOFFSET,IOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- offreg:REGISTER:GP:UINT64 @far
vmovdqu64 %zmm1, 8128(%rcx,%rdx)
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu16 %zmm1, (%rcx,%rdx,1){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu16 %zmm1, (%rcx,%rdx,2){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu16 %zmm1, (%rcx,%rdx,4){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu16 %zmm1, (%rcx,%rdx,8){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovupd %zmm1, (%rcx,%rdx,1){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovupd %zmm1, (%rcx,%rdx,2){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovupd %zmm1, (%rcx,%rdx,4){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovupd %zmm1, (%rcx,%rdx,8){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu16 %zmm1, (%rcx,%rdx,1){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu16 %zmm1, (%rcx,%rdx,2){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu16 %zmm1, (%rcx,%rdx,4){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu16 %zmm1, (%rcx,%rdx,8){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovups %zmm1, (%rcx,%rdx,1){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovups %zmm1, (%rcx,%rdx,2){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovups %zmm1, (%rcx,%rdx,4){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovups %zmm1, (%rcx,%rdx,8){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu16 %zmm1, (%rcx,%rdx,1){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu16 %zmm1, (%rcx,%rdx,2){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu16 %zmm1, (%rcx,%rdx,4){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu16 %zmm1, (%rcx,%rdx,8){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu32 %zmm1, (%rcx,%rdx,1){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu32 %zmm1, (%rcx,%rdx,2){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu32 %zmm1, (%rcx,%rdx,4){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu32 %zmm1, (%rcx,%rdx,8){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, (%rcx,%rdx,1){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, (%rcx,%rdx,2){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, (%rcx,%rdx,4){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, (%rcx,%rdx,8){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu8 %zmm1, (%rcx,%rdx,1){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu8 %zmm1, (%rcx,%rdx,2){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu8 %zmm1, (%rcx,%rdx,4){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu8 %zmm1, (%rcx,%rdx,8){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu16 %zmm1, (%rcx,%rdx,1){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu16 %zmm1, (%rcx,%rdx,2){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu16 %zmm1, (%rcx,%rdx,4){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu16 %zmm1, (%rcx,%rdx,8){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu32 %zmm1, (%rcx,%rdx,1){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu32 %zmm1, (%rcx,%rdx,2){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu32 %zmm1, (%rcx,%rdx,4){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu32 %zmm1, (%rcx,%rdx,8){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, (%rcx,%rdx,1){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, (%rcx,%rdx,2){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, (%rcx,%rdx,4){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, (%rcx,%rdx,8){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu8 %zmm1, (%rcx,%rdx,1){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu8 %zmm1, (%rcx,%rdx,2){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu8 %zmm1, (%rcx,%rdx,4){%k1}
### op store [GOFFSET,MASK,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu8 %zmm1, (%rcx,%rdx,8){%k1}
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 offreg:REGISTER:GP:UINT64
vmovdqu16 %zmm1, (%rcx,%rdx){%k1}
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE offreg:REGISTER:GP:UINT64
vmovupd %zmm1, (%rcx,%rdx){%k1}
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF offreg:REGISTER:GP:UINT64
vmovdqu16 %zmm1, (%rcx,%rdx){%k1}
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE offreg:REGISTER:GP:UINT64
vmovups %zmm1, (%rcx,%rdx){%k1}
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 offreg:REGISTER:GP:UINT64
vmovdqu16 %zmm1, (%rcx,%rdx){%k1}
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 offreg:REGISTER:GP:UINT64
vmovdqu32 %zmm1, (%rcx,%rdx){%k1}
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, (%rcx,%rdx){%k1}
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 offreg:REGISTER:GP:UINT64
vmovdqu8 %zmm1, (%rcx,%rdx){%k1}
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 offreg:REGISTER:GP:UINT64
vmovdqu16 %zmm1, (%rcx,%rdx){%k1}
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 offreg:REGISTER:GP:UINT64
vmovdqu32 %zmm1, (%rcx,%rdx){%k1}
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, (%rcx,%rdx){%k1}
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 offreg:REGISTER:GP:UINT64
vmovdqu8 %zmm1, (%rcx,%rdx){%k1}
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovsh %xmm1, (%rcx,%rdx,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovsh %xmm1, (%rcx,%rdx,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovsh %xmm1, (%rcx,%rdx,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovsh %xmm1, (%rcx,%rdx,8)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovsd %xmm1, (%rcx,%rdx,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovsd %xmm1, (%rcx,%rdx,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovsd %xmm1, (%rcx,%rdx,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovsd %xmm1, (%rcx,%rdx,8)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovsh %xmm1, (%rcx,%rdx,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovsh %xmm1, (%rcx,%rdx,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovsh %xmm1, (%rcx,%rdx,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovsh %xmm1, (%rcx,%rdx,8)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovss %xmm1, (%rcx,%rdx,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovss %xmm1, (%rcx,%rdx,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovss %xmm1, (%rcx,%rdx,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovss %xmm1, (%rcx,%rdx,8)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
movw %rcx, (%rdx,%rsi,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
movw %rcx, (%rdx,%rsi,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
movw %rcx, (%rdx,%rsi,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
movw %rcx, (%rdx,%rsi,8)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
movl %rcx, (%rdx,%rsi,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
movl %rcx, (%rdx,%rsi,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
movl %rcx, (%rdx,%rsi,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
movl %rcx, (%rdx,%rsi,8)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
movq %rcx, (%rdx,%rsi,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
movq %rcx, (%rdx,%rsi,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
movq %rcx, (%rdx,%rsi,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
movq %rcx, (%rdx,%rsi,8)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
movb %rcx, (%rdx,%rsi,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
movb %rcx, (%rdx,%rsi,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
movb %rcx, (%rdx,%rsi,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
movb %rcx, (%rdx,%rsi,8)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
movw %rcx, (%rdx,%rsi,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
movw %rcx, (%rdx,%rsi,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
movw %rcx, (%rdx,%rsi,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
movw %rcx, (%rdx,%rsi,8)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
movl %rcx, (%rdx,%rsi,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
movl %rcx, (%rdx,%rsi,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
movl %rcx, (%rdx,%rsi,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
movl %rcx, (%rdx,%rsi,8)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
movq %rcx, (%rdx,%rsi,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
movq %rcx, (%rdx,%rsi,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
movq %rcx, (%rdx,%rsi,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
movq %rcx, (%rdx,%rsi,8)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
movb %rcx, (%rdx,%rsi,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
movb %rcx, (%rdx,%rsi,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
movb %rcx, (%rdx,%rsi,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
movb %rcx, (%rdx,%rsi,8)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, (%rcx,%rdx,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, (%rcx,%rdx,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, (%rcx,%rdx,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, (%rcx,%rdx,8)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovupd %zmm1, (%rcx,%rdx,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovupd %zmm1, (%rcx,%rdx,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovupd %zmm1, (%rcx,%rdx,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovupd %zmm1, (%rcx,%rdx,8)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, (%rcx,%rdx,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, (%rcx,%rdx,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, (%rcx,%rdx,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, (%rcx,%rdx,8)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovups %zmm1, (%rcx,%rdx,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovups %zmm1, (%rcx,%rdx,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovups %zmm1, (%rcx,%rdx,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovups %zmm1, (%rcx,%rdx,8)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, (%rcx,%rdx,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, (%rcx,%rdx,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, (%rcx,%rdx,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, (%rcx,%rdx,8)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, (%rcx,%rdx,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, (%rcx,%rdx,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, (%rcx,%rdx,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, (%rcx,%rdx,8)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, (%rcx,%rdx,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, (%rcx,%rdx,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, (%rcx,%rdx,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, (%rcx,%rdx,8)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, (%rcx,%rdx,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, (%rcx,%rdx,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, (%rcx,%rdx,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, (%rcx,%rdx,8)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, (%rcx,%rdx,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, (%rcx,%rdx,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, (%rcx,%rdx,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, (%rcx,%rdx,8)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, (%rcx,%rdx,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, (%rcx,%rdx,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, (%rcx,%rdx,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, (%rcx,%rdx,8)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, (%rcx,%rdx,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, (%rcx,%rdx,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, (%rcx,%rdx,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, (%rcx,%rdx,8)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:1}
vmovdqu64 %zmm1, (%rcx,%rdx,1)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:2}
vmovdqu64 %zmm1, (%rcx,%rdx,2)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:4}
vmovdqu64 %zmm1, (%rcx,%rdx,4)
### op store [GOFFSET,SCALEOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64 {scale_factor:8}
vmovdqu64 %zmm1, (%rcx,%rdx,8)
### op store [GOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovsh %xmm1, (%rcx,%rdx)
### op store [GOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovsd %xmm1, (%rcx,%rdx)
### op store [GOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovsh %xmm1, (%rcx,%rdx)
### op store [GOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovss %xmm1, (%rcx,%rdx)
### op store [GOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
movw %rcx, (%rdx,%rsi)
### op store [GOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
movl %rcx, (%rdx,%rsi)
### op store [GOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
movq %rcx, (%rdx,%rsi)
### op store [GOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
movb %rcx, (%rdx,%rsi)
### op store [GOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
movw %rcx, (%rdx,%rsi)
### op store [GOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
movl %rcx, (%rdx,%rsi)
### op store [GOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
movq %rcx, (%rdx,%rsi)
### op store [GOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
movb %rcx, (%rdx,%rsi)
### op store [GOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, (%rcx,%rdx)
### op store [GOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovupd %zmm1, (%rcx,%rdx)
### op store [GOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, (%rcx,%rdx)
### op store [GOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovups %zmm1, (%rcx,%rdx)
### op store [GOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, (%rcx,%rdx)
### op store [GOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, (%rcx,%rdx)
### op store [GOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, (%rcx,%rdx)
### op store [GOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, (%rcx,%rdx)
### op store [GOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, (%rcx,%rdx)
### op store [GOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, (%rcx,%rdx)
### op store [GOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, (%rcx,%rdx)
### op store [GOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, (%rcx,%rdx)
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:-
vmovdqu16 %zmm1, -8192(%rcx){%k1}
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- @far
vmovdqu16 %zmm1, 8128(%rcx){%k1}
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:-
vmovupd %zmm1, -8192(%rcx){%k1}
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- @far
vmovupd %zmm1, 8128(%rcx){%k1}
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:-
vmovdqu16 %zmm1, -8192(%rcx){%k1}
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- @far
vmovdqu16 %zmm1, 8128(%rcx){%k1}
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:-
vmovups %zmm1, -8192(%rcx){%k1}
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- @far
vmovups %zmm1, 8128(%rcx){%k1}
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:-
vmovdqu16 %zmm1, -8192(%rcx){%k1}
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- @far
vmovdqu16 %zmm1, 8128(%rcx){%k1}
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:-
vmovdqu32 %zmm1, -8192(%rcx){%k1}
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- @far
vmovdqu32 %zmm1, 8128(%rcx){%k1}
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx){%k1}
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx){%k1}
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:-
vmovdqu8 %zmm1, -8192(%rcx){%k1}
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- @far
vmovdqu8 %zmm1, 8128(%rcx){%k1}
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:-
vmovdqu16 %zmm1, -8192(%rcx){%k1}
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- @far
vmovdqu16 %zmm1, 8128(%rcx){%k1}
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:-
vmovdqu32 %zmm1, -8192(%rcx){%k1}
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- @far
vmovdqu32 %zmm1, 8128(%rcx){%k1}
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx){%k1}
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx){%k1}
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:-
vmovdqu8 %zmm1, -8192(%rcx){%k1}
### op store [IOFFSET,MASK] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- @far
vmovdqu8 %zmm1, 8128(%rcx){%k1}
### op store [IOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
vmovsh %xmm1, -128(%rcx)
### op store [IOFFSET] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
vmovsh %xmm1, 127(%rcx)
### op store [IOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
vmovsd %xmm1, -128(%rcx)
### op store [IOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
vmovsd %xmm1, 127(%rcx)
### op store [IOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
vmovsh %xmm1, -128(%rcx)
### op store [IOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
vmovsh %xmm1, 127(%rcx)
### op store [IOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
vmovss %xmm1, -128(%rcx)
### op store [IOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
vmovss %xmm1, 127(%rcx)
### op store [IOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movw %rcx, -128(%rdx)
### op store [IOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movw %rcx, 127(%rdx)
### op store [IOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movl %rcx, -128(%rdx)
### op store [IOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movl %rcx, 127(%rdx)
### op store [IOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movq %rcx, -128(%rdx)
### op store [IOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movq %rcx, 127(%rdx)
### op store [IOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movb %rcx, -128(%rdx)
### op store [IOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movb %rcx, 127(%rdx)
### op store [IOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movw %rcx, -128(%rdx)
### op store [IOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movw %rcx, 127(%rdx)
### op store [IOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movl %rcx, -128(%rdx)
### op store [IOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movl %rcx, 127(%rdx)
### op store [IOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movq %rcx, -128(%rdx)
### op store [IOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movq %rcx, 127(%rdx)
### op store [IOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
movb %rcx, -128(%rdx)
### op store [IOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64 @far
movb %rcx, 127(%rdx)
### op store [IOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:BF16{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpextrw $0, %xmm1, -128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:BF16{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpextrw $7, %xmm1, 127(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovupd %zmm1, -8192(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovupd %zmm1, 8128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vmovsd %xmm1,-128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vmovhpd %xmm1,127(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpextrw $0, %xmm1, -128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpextrw $7, %xmm1, 127(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovups %zmm1, -8192(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovups %zmm1, 8128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vextractps $0, %xmm1, -128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vextractps $3, %xmm1, 127(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpextrw $0, %xmm1, -128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpextrw $7, %xmm1, 127(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpextrd $0, %xmm1, -128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpextrd $3, %xmm1, 127(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpextrq $0, %xmm1, -128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpextrq $1, %xmm1, 127(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpextrb $0, %xmm1, -128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpextrb $15, %xmm1, 127(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpextrw $0, %xmm1, -128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpextrw $7, %xmm1, 127(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpextrd $0, %xmm1, -128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpextrd $3, %xmm1, 127(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpextrq $0, %xmm1, -128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpextrq $1, %xmm1, 127(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpextrb $0, %xmm1, -128(%rcx)
### op store [IOFFSET] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpextrb $15, %xmm1, 127(%rcx)
### op store [MASK,VINDEX] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE vidxreg:REGISTER:VEC:DOUBLE {it:INT64}
vscatterqpd %zmm1, (%rcx,%zmm2,1){%k1}
### op store [MASK,VINDEX] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE vidxreg:REGISTER:VEC:SINGLE {it:INT32}
vscatterdps %zmm1, (%rcx,%zmm2,1){%k1}
### op store [MASK,VINDEX] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 vidxreg:REGISTER:VEC:SINT32 {it:INT32}
vscatterdps %zmm1, (%rcx,%zmm2,1){%k1}
### op store [MASK,VINDEX] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 vidxreg:REGISTER:VEC:SINT64 {it:INT64}
vscatterqpd %zmm1, (%rcx,%zmm2,1){%k1}
### op store [MASK,VINDEX] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 vidxreg:REGISTER:VEC:UINT32 {it:INT32}
vscatterdps %zmm1, (%rcx,%zmm2,1){%k1}
### op store [MASK,VINDEX] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 vidxreg:REGISTER:VEC:UINT64 {it:INT64}
vscatterqpd %zmm1, (%rcx,%zmm2,1){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 voffset:IMMEDIATE:-:-
vmovdqu16 %zmm1, -8192(%rcx){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 voffset:IMMEDIATE:-:- @far
vmovdqu16 %zmm1, 8128(%rcx){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE voffset:IMMEDIATE:-:-
vmovupd %zmm1, -8192(%rcx){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE voffset:IMMEDIATE:-:- @far
vmovupd %zmm1, 8128(%rcx){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF voffset:IMMEDIATE:-:-
vmovdqu16 %zmm1, -8192(%rcx){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF voffset:IMMEDIATE:-:- @far
vmovdqu16 %zmm1, 8128(%rcx){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE voffset:IMMEDIATE:-:-
vmovups %zmm1, -8192(%rcx){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE voffset:IMMEDIATE:-:- @far
vmovups %zmm1, 8128(%rcx){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 voffset:IMMEDIATE:-:-
vmovdqu16 %zmm1, -8192(%rcx){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 voffset:IMMEDIATE:-:- @far
vmovdqu16 %zmm1, 8128(%rcx){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 voffset:IMMEDIATE:-:-
vmovdqu32 %zmm1, -8192(%rcx){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 voffset:IMMEDIATE:-:- @far
vmovdqu32 %zmm1, 8128(%rcx){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 voffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 voffset:IMMEDIATE:-:-
vmovdqu8 %zmm1, -8192(%rcx){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 voffset:IMMEDIATE:-:- @far
vmovdqu8 %zmm1, 8128(%rcx){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 voffset:IMMEDIATE:-:-
vmovdqu16 %zmm1, -8192(%rcx){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 voffset:IMMEDIATE:-:- @far
vmovdqu16 %zmm1, 8128(%rcx){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 voffset:IMMEDIATE:-:-
vmovdqu32 %zmm1, -8192(%rcx){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 voffset:IMMEDIATE:-:- @far
vmovdqu32 %zmm1, 8128(%rcx){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 voffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 voffset:IMMEDIATE:-:-
vmovdqu8 %zmm1, -8192(%rcx){%k1}
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 voffset:IMMEDIATE:-:- @far
vmovdqu8 %zmm1, 8128(%rcx){%k1}
### op store [MASK] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16
vmovdqu16 %zmm1, (%rcx){%k1}
### op store [MASK] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE
vmovupd %zmm1, (%rcx){%k1}
### op store [MASK] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF
vmovdqu16 %zmm1, (%rcx){%k1}
### op store [MASK] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE
vmovups %zmm1, (%rcx){%k1}
### op store [MASK] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16
vmovdqu16 %zmm1, (%rcx){%k1}
### op store [MASK] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32
vmovdqu32 %zmm1, (%rcx){%k1}
### op store [MASK] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64
vmovdqu64 %zmm1, (%rcx){%k1}
### op store [MASK] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8
vmovdqu8 %zmm1, (%rcx){%k1}
### op store [MASK] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16
vmovdqu16 %zmm1, (%rcx){%k1}
### op store [MASK] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32
vmovdqu32 %zmm1, (%rcx){%k1}
### op store [MASK] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64
vmovdqu64 %zmm1, (%rcx){%k1}
### op store [MASK] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8
vmovdqu8 %zmm1, (%rcx){%k1}
### op store [PARAM] adreg:REGISTER:FP:BF16 param:NAME:-:-
vmovsh %xmm1, %[p]
### op store [PARAM] adreg:REGISTER:FP:DOUBLE param:NAME:-:-
vmovsd %xmm1, %[p]
### op store [PARAM] adreg:REGISTER:FP:HALF param:NAME:-:-
vmovsh %xmm1, %[p]
### op store [PARAM] adreg:REGISTER:FP:SINGLE param:NAME:-:-
vmovss %xmm1, %[p]
### op store [PARAM] adreg:REGISTER:GP:SINT16 param:NAME:-:-
movw %rcx, %[p]
### op store [PARAM] adreg:REGISTER:GP:SINT32 param:NAME:-:-
movl %rcx, %[p]
### op store [PARAM] adreg:REGISTER:GP:SINT64 param:NAME:-:-
movq %rcx, %[p]
### op store [PARAM] adreg:REGISTER:GP:SINT8 param:NAME:-:-
movb %rcx, %[p]
### op store [PARAM] adreg:REGISTER:GP:UINT16 param:NAME:-:-
movw %rcx, %[p]
### op store [PARAM] adreg:REGISTER:GP:UINT32 param:NAME:-:-
movl %rcx, %[p]
### op store [PARAM] adreg:REGISTER:GP:UINT64 param:NAME:-:-
movq %rcx, %[p]
### op store [PARAM] adreg:REGISTER:GP:UINT8 param:NAME:-:-
movb %rcx, %[p]
### op store [VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:BF16{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpextrw $0, %xmm1, -8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:BF16{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpextrw $7, %xmm1, 8128(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovupd %zmm1, -8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovupd %zmm1, 8128(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vmovsd %xmm1,-8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vmovhpd %xmm1,8128(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpextrw $0, %xmm1, -8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpextrw $7, %xmm1, 8128(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovups %zmm1, -8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovups %zmm1, 8128(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vextractps $0, %xmm1, -8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vextractps $3, %xmm1, 8128(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpextrw $0, %xmm1, -8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpextrw $7, %xmm1, 8128(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpextrd $0, %xmm1, -8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpextrd $3, %xmm1, 8128(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpextrq $0, %xmm1, -8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpextrq $1, %xmm1, 8128(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpextrb $0, %xmm1, -8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpextrb $15, %xmm1, 8128(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpextrw $0, %xmm1, -8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpextrw $7, %xmm1, 8128(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpextrd $0, %xmm1, -8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpextrd $3, %xmm1, 8128(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpextrq $0, %xmm1, -8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpextrq $1, %xmm1, 8128(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
vmovdqu64 %zmm1, -8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
vmovdqu64 %zmm1, 8128(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
vpextrb $0, %xmm1, -8192(%rcx)
### op store [VOFFSET] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
vpextrb $15, %xmm1, 8128(%rcx)
### op store [] adreg:REGISTER:FP:BF16 agreg:REGISTER:GP:UINT64
vmovsh %xmm1, (%rcx)
### op store [] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64
vmovsd %xmm1, (%rcx)
### op store [] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64
vmovsh %xmm1, (%rcx)
### op store [] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64
vmovss %xmm1, (%rcx)
### op store [] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64
movw %rcx, (%rdx)
### op store [] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64
movl %rcx, (%rdx)
### op store [] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64
movq %rcx, (%rdx)
### op store [] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64
movb %rcx, (%rdx)
### op store [] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64
movw %rcx, (%rdx)
### op store [] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64
movl %rcx, (%rdx)
### op store [] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64
movq %rcx, (%rdx)
### op store [] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64
movb %rcx, (%rdx)
### op store [] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:BF16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vpextrw $0, %xmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:BF16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vpextrw $7, %xmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64
vmovupd %zmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vmovsd %xmm1,(%rcx)
### op store [] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vmovhpd %xmm1,(%rcx)
### op store [] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vpextrw $0, %xmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vpextrw $7, %xmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64
vmovups %zmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vextractps $0, %xmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vextractps $3, %xmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vpextrw $0, %xmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vpextrw $7, %xmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vpextrd $0, %xmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vpextrd $3, %xmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vpextrq $0, %xmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vpextrq $1, %xmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vpextrb $0, %xmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vpextrb $15, %xmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vpextrw $0, %xmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vpextrw $7, %xmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vpextrd $0, %xmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vpextrd $3, %xmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vpextrq $0, %xmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vpextrq $1, %xmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64
vmovdqu64 %zmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
vpextrb $0, %xmm1, (%rcx)
### op store [] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
vpextrb $15, %xmm1, (%rcx)
### op sub [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64
movq %rcx,%rsi
subq %rdx,%rsi
### op sub [] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:-
movq %rcx,%rdx
subq $-2147483648,%rdx
### op sub [] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:- @far
movq %rcx,%rdx
subq $2147483647,%rdx
### op sub [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64
movq %rcx,%rsi
subq %rdx,%rsi
### op sub [] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:-
movq %rcx,%rdx
subq $-2147483648,%rdx
### op sub [] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:- @far
movq %rcx,%rdx
subq $2147483647,%rdx
