### method align(bytes=64)
.balign 64
### method asmfile_annotations()
.section .note.GNU-stack,"",%progbits
### method c_simd_size_function()
static inline size_t get_simd_size() { return 16; }
### method cb(cmp=NE, label=notequal, reg1=x0, reg2=x1)
cmp x0,x1
b.ne .notequal
### method compiler_flags()
['-march=armv8.2-a+fp16+fp16fml+bf16+fp8fma+dotprod+i8mm']
### method create_callconv(name=default)
<asmgen.callconv.callconv.callconv object>
### method enabled_features()
{BF16, DOTPROD, FHM, FP16, FP8FMA, I8MM}
### method freg(dt=DOUBLE, reg_idx=0)
d0
### method freg(dt=HALF, reg_idx=0)
h0
### method freg(dt=SINGLE, reg_idx=0)
s0
### method get_param_value(name=dummy)
dummy
### method get_parameters()
['FP16', 'FHM', 'BF16', 'FP8FMA', 'DOTPROD', 'I8MM']
### method greg(reg_idx=0)
x0
### method is_vla()
False
### method isaclear()
None
### method isadata()

### method isaendquirks(dt=DOUBLE, rt=<asmgen.registers.reg_tracker object>)

### method isaendquirks(dt=HALF, rt=<asmgen.registers.reg_tracker object>)

### method isaendquirks(dt=SINGLE, rt=<asmgen.registers.reg_tracker object>)

### method isaquirks(dt=DOUBLE, rt=<asmgen.registers.reg_tracker object>)

### method isaquirks(dt=HALF, rt=<asmgen.registers.reg_tracker object>)

### method isaquirks(dt=SINGLE, rt=<asmgen.registers.reg_tracker object>)

### method jfzero(dt=DOUBLE, freg1=s0, freg2=s1, greg=x0, label=someloop)
fcmp s0,#0.0
b.eq .someloop
### method jfzero(dt=HALF, freg1=s0, freg2=s1, greg=x0, label=someloop)
fcmp s0,#0.0
b.eq .someloop
### method jfzero(dt=SINGLE, freg1=s0, freg2=s1, greg=x0, label=someloop)
fcmp s0,#0.0
b.eq .someloop
### method jump(label=someloop)
b .someloop
### method jvzero(dt=DOUBLE, freg=s2, greg=x0, label=someloop, vreg1=v0, vreg2=v1)
fmaxv s2, v1.2d
fcmp s2, #0.0
b.eq .someloop
### method jvzero(dt=HALF, freg=s2, greg=x0, label=someloop, vreg1=v0, vreg2=v1)
fmaxv s2, v1.8h
fcmp s2, #0.0
b.eq .someloop
### method jvzero(dt=SINGLE, freg=s2, greg=x0, label=someloop, vreg1=v0, vreg2=v1)
fmaxv s2, v1.4s
fcmp s2, #0.0
b.eq .someloop
### method jzero(label=someloop, reg=x0)
cmp x0,0
b.eq .someloop
### method kiterkleft(kleftreg=x1, kreg=x0, tmpreg=x2, unroll=4)
and x1,x0,#3
lsr x0,x0,#2
### method label(label=label)
.label:
### method labelstr(label=label)
.label
### method loopbegin(label=someloop, reg=x0)
.someloop:
sub x0,x0,1
### method loopbegin_nz(label=someloop, labelskip=someloop_nz, reg=x0)
cmp x0,0
b.eq .someloop_nz
.someloop:
sub x0,x0,1
### method loopend(label=someloop, reg=x0)
cmp x0,0
b.ne .someloop
### method max_fregs()
32
### method max_gregs()
32
### method max_tregs(dt=DOUBLE)
0
### method max_tregs(dt=HALF)
0
### method max_tregs(dt=SINGLE)
0
### method max_vregs()
32
### method nop()
nop
### method ret()
ret
### method simd_size()
16
### method supported_on_host()
False
### method supportedby_cpuinfo(cpuinfo=invalid_isa)
False
### method tile_types()
[]
### method treg(dt=DOUBLE, reg_idx=0)
!NotImplementedError: NEON has no tiles, use SME
### method treg(dt=HALF, reg_idx=0)
!NotImplementedError: NEON has no tiles, use SME
### method treg(dt=SINGLE, reg_idx=0)
!NotImplementedError: NEON has no tiles, use SME
### method treg_tag(dt=DOUBLE)
treg
### method treg_tag(dt=HALF)
treg
### method treg_tag(dt=SINGLE)
treg
### method vreg(reg_idx=0)
v0
### op add [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64
add x12,x10,x11
### op add [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64{ISHIFT} cdreg:REGISTER:GP:SINT64 bdreg_shift:IMMEDIATE:-:-
add x12,x10,x11
### op add [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64{ISHIFT} cdreg:REGISTER:GP:SINT64 bdreg_shift:IMMEDIATE:-:- @far
add x12,x10,x11, LSL #63
### op add [] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:-
add x11,x10,#-4095
### op add [] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:- @far
add x11,x10,#4095
### op add [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64
add x12,x10,x11
### op add [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64{ISHIFT} cdreg:REGISTER:GP:UINT64 bdreg_shift:IMMEDIATE:-:-
add x12,x10,x11
### op add [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64{ISHIFT} cdreg:REGISTER:GP:UINT64 bdreg_shift:IMMEDIATE:-:- @far
add x12,x10,x11, LSL #63
### op add [] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:-
add x11,x10,#-4095
### op add [] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:- @far
add x11,x10,#4095
### op add [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE
fadd v3.2d,v1.2d,v2.2d
### op add [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE bdreg_lane:IMMEDIATE:-:-
fadd v3.2d,v1.2d,v2.d[0]
### op add [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE bdreg_lane:IMMEDIATE:-:- @far
fadd v3.2d,v1.2d,v2.d[1]
### op add [] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF
fadd v3.8h,v1.8h,v2.8h
### op add [] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:-
fadd v3.8h,v1.8h,v2.h[0]
### op add [] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- @far
fadd v3.8h,v1.8h,v2.h[7]
### op add [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE
fadd v3.4s,v1.4s,v2.4s
### op add [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:-
fadd v3.4s,v1.4s,v2.s[0]
### op add [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- @far
fadd v3.4s,v1.4s,v2.s[3]
### op add [] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16
add v3.8h,v1.8h,v2.8h
### op add [] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:-
add v3.8h,v1.8h,v2.h[0]
### op add [] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- @far
add v3.8h,v1.8h,v2.h[7]
### op add [] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32
add v3.4s,v1.4s,v2.4s
### op add [] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:-
add v3.4s,v1.4s,v2.s[0]
### op add [] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- @far
add v3.4s,v1.4s,v2.s[3]
### op add [] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64
add v3.2d,v1.2d,v2.2d
### op add [] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64 bdreg_lane:IMMEDIATE:-:-
add v3.2d,v1.2d,v2.d[0]
### op add [] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64 bdreg_lane:IMMEDIATE:-:- @far
add v3.2d,v1.2d,v2.d[1]
### op add [] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8
add v3.16b,v1.16b,v2.16b
### op add [] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:-
add v3.16b,v1.16b,v2.b[0]
### op add [] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:- @far
add v3.16b,v1.16b,v2.b[15]
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlslb v3.8h,v1.16b,v2.16b
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlslt v3.8h,v1.16b,v2.16b
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlsllbb v3.4s,v1.16b,v2.16b
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlslltt v3.4s,v1.16b,v2.16b
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlslb v3.8h,v1.16b,v2.b[0]
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlslt v3.8h,v1.16b,v2.b[15]
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlsllbb v3.4s,v1.16b,v2.b[0]
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlslltt v3.4s,v1.16b,v2.b[15]
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlslb v3.8h,v1.16b,v2.16b
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlslt v3.8h,v1.16b,v2.16b
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlsllbb v3.4s,v1.16b,v2.16b
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlslltt v3.4s,v1.16b,v2.16b
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlslb v3.8h,v1.16b,v2.b[0]
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlslt v3.8h,v1.16b,v2.b[15]
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlsllbb v3.4s,v1.16b,v2.b[0]
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlslltt v3.4s,v1.16b,v2.b[15]
### op fma [NP,PART] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_CONTIGUOUS}
fmlsl v3.4s,v1.4h,v2.4h
### op fma [NP,PART] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_CONTIGUOUS} @far
fmlsl2 v3.4s,v1.4h,v2.4h
### op fma [NP,PART] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_CONTIGUOUS}
fmlsl v3.4s,v1.4h,v2.h[0]
### op fma [NP,PART] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_CONTIGUOUS} @far
fmlsl2 v3.4s,v1.4h,v2.h[7]
### op fma [NP,PART] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
smlslb v3.4s,v1.8h,v2.8h
### op fma [NP,PART] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
smlslt v3.4s,v1.8h,v2.8h
### op fma [NP,PART] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
smlslb v3.4s,v1.8h,v2.h[0]
### op fma [NP,PART] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
smlslt v3.4s,v1.8h,v2.h[7]
### op fma [NP,PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT16 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
smlslb v3.8h,v1.16b,v2.16b
### op fma [NP,PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT16 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
smlslt v3.8h,v1.16b,v2.16b
### op fma [NP,PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
smlsllbb v3.4s,v1.16b,v2.16b
### op fma [NP,PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
smlslltt v3.4s,v1.16b,v2.16b
### op fma [NP,PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
smlslb v3.8h,v1.16b,v2.b[0]
### op fma [NP,PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
smlslt v3.8h,v1.16b,v2.b[15]
### op fma [NP,PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
smlsllbb v3.4s,v1.16b,v2.b[0]
### op fma [NP,PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
smlslltt v3.4s,v1.16b,v2.b[15]
### op fma [NP,PART] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
umlslb v3.4s,v1.8h,v2.8h
### op fma [NP,PART] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
umlslt v3.4s,v1.8h,v2.8h
### op fma [NP,PART] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16{ILANE} cdreg:REGISTER:VEC:UINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
umlslb v3.4s,v1.8h,v2.h[0]
### op fma [NP,PART] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16{ILANE} cdreg:REGISTER:VEC:UINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
umlslt v3.4s,v1.8h,v2.h[7]
### op fma [NP,PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT16 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
umlslb v3.8h,v1.16b,v2.16b
### op fma [NP,PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT16 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
umlslt v3.8h,v1.16b,v2.16b
### op fma [NP,PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
umlsllbb v3.4s,v1.16b,v2.16b
### op fma [NP,PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
umlslltt v3.4s,v1.16b,v2.16b
### op fma [NP,PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
umlslb v3.8h,v1.16b,v2.b[0]
### op fma [NP,PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
umlslt v3.8h,v1.16b,v2.b[15]
### op fma [NP,PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
umlsllbb v3.4s,v1.16b,v2.b[0]
### op fma [NP,PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
umlslltt v3.4s,v1.16b,v2.b[15]
### op fma [NP] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE
fmls v3.2d,v1.2d,v2.2d
### op fma [NP] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE bdreg_lane:IMMEDIATE:-:-
fmls v3.2d,v1.2d,v2.d[0]
### op fma [NP] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE bdreg_lane:IMMEDIATE:-:- @far
fmls v3.2d,v1.2d,v2.d[1]
### op fma [NP] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF
fmls v3.8h,v1.8h,v2.8h
### op fma [NP] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:-
fmls v3.8h,v1.8h,v2.h[0]
### op fma [NP] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- @far
fmls v3.8h,v1.8h,v2.h[7]
### op fma [NP] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE
fmls v3.4s,v1.4s,v2.4s
### op fma [NP] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:-
fmls v3.4s,v1.4s,v2.s[0]
### op fma [NP] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- @far
fmls v3.4s,v1.4s,v2.s[3]
### op fma [NP] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16
mls v3.8h,v1.8h,v2.8h
### op fma [NP] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:-
mls v3.8h,v1.8h,v2.h[0]
### op fma [NP] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- @far
mls v3.8h,v1.8h,v2.h[7]
### op fma [NP] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32
mls v3.4s,v1.4s,v2.4s
### op fma [NP] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:-
mls v3.4s,v1.4s,v2.s[0]
### op fma [NP] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- @far
mls v3.4s,v1.4s,v2.s[3]
### op fma [NP] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64
mls v3.2d,v1.2d,v2.2d
### op fma [NP] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64 bdreg_lane:IMMEDIATE:-:-
mls v3.2d,v1.2d,v2.d[0]
### op fma [NP] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64 bdreg_lane:IMMEDIATE:-:- @far
mls v3.2d,v1.2d,v2.d[1]
### op fma [NP] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8
mls v3.16b,v1.16b,v2.16b
### op fma [NP] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:-
mls v3.16b,v1.16b,v2.b[0]
### op fma [NP] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:- @far
mls v3.16b,v1.16b,v2.b[15]
### op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlalb v3.8h,v1.16b,v2.16b
### op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlalt v3.8h,v1.16b,v2.16b
### op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlallbb v3.4s,v1.16b,v2.16b
### op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlalltt v3.4s,v1.16b,v2.16b
### op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlalb v3.8h,v1.16b,v2.b[0]
### op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlalt v3.8h,v1.16b,v2.b[15]
### op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlallbb v3.4s,v1.16b,v2.b[0]
### op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlalltt v3.4s,v1.16b,v2.b[15]
### op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlalb v3.8h,v1.16b,v2.16b
### op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlalt v3.8h,v1.16b,v2.16b
### op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlallbb v3.4s,v1.16b,v2.16b
### op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlalltt v3.4s,v1.16b,v2.16b
### op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlalb v3.8h,v1.16b,v2.b[0]
### op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlalt v3.8h,v1.16b,v2.b[15]
### op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlallbb v3.4s,v1.16b,v2.b[0]
### op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlalltt v3.4s,v1.16b,v2.b[15]
### op fma [PART] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_CONTIGUOUS}
fmlal v3.4s,v1.4h,v2.4h
### op fma [PART] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_CONTIGUOUS} @far
fmlal2 v3.4s,v1.4h,v2.4h
### op fma [PART] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_CONTIGUOUS}
fmlal v3.4s,v1.4h,v2.h[0]
### op fma [PART] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_CONTIGUOUS} @far
fmlal2 v3.4s,v1.4h,v2.h[7]
### op fma [PART] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
smlalb v3.4s,v1.8h,v2.8h
### op fma [PART] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
smlalt v3.4s,v1.8h,v2.8h
### op fma [PART] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
smlalb v3.4s,v1.8h,v2.h[0]
### op fma [PART] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
smlalt v3.4s,v1.8h,v2.h[7]
### op fma [PART] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
!RuntimeError: Unsupported datatype
### op fma [PART] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
!RuntimeError: Unsupported datatype
### op fma [PART] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:UINT16{ILANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
!RuntimeError: Unsupported datatype
### op fma [PART] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:UINT16{ILANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
!RuntimeError: Unsupported datatype
### op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT16 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
smlalb v3.8h,v1.16b,v2.16b
### op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT16 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
smlalt v3.8h,v1.16b,v2.16b
### op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
smlallbb v3.4s,v1.16b,v2.16b
### op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
smlalltt v3.4s,v1.16b,v2.16b
### op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
smlalb v3.8h,v1.16b,v2.b[0]
### op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
smlalt v3.8h,v1.16b,v2.b[15]
### op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
smlallbb v3.4s,v1.16b,v2.b[0]
### op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
smlalltt v3.4s,v1.16b,v2.b[15]
### op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:SINT16 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
!RuntimeError: Unsupported datatype
### op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:SINT16 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
!RuntimeError: Unsupported datatype
### op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
!RuntimeError: Unsupported datatype
### op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
!RuntimeError: Unsupported datatype
### op fma [PART] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
!RuntimeError: Unsupported datatype
### op fma [PART] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
!RuntimeError: Unsupported datatype
### op fma [PART] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
!RuntimeError: Unsupported datatype
### op fma [PART] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
!RuntimeError: Unsupported datatype
### op fma [PART] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
umlalb v3.4s,v1.8h,v2.8h
### op fma [PART] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
umlalt v3.4s,v1.8h,v2.8h
### op fma [PART] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16{ILANE} cdreg:REGISTER:VEC:UINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
umlalb v3.4s,v1.8h,v2.h[0]
### op fma [PART] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16{ILANE} cdreg:REGISTER:VEC:UINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
umlalt v3.4s,v1.8h,v2.h[7]
### op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT16 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
!RuntimeError: Unsupported datatype
### op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT16 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
!RuntimeError: Unsupported datatype
### op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
!RuntimeError: Unsupported datatype
### op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
!RuntimeError: Unsupported datatype
### op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT16 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
umlalb v3.8h,v1.16b,v2.16b
### op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT16 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
umlalt v3.8h,v1.16b,v2.16b
### op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
umlallbb v3.4s,v1.16b,v2.16b
### op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
umlalltt v3.4s,v1.16b,v2.16b
### op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
umlalb v3.8h,v1.16b,v2.b[0]
### op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
umlalt v3.8h,v1.16b,v2.b[15]
### op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
umlallbb v3.4s,v1.16b,v2.b[0]
### op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
umlalltt v3.4s,v1.16b,v2.b[15]
### op fma [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE
fmla v3.2d,v1.2d,v2.2d
### op fma [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE bdreg_lane:IMMEDIATE:-:-
fmla v3.2d,v1.2d,v2.d[0]
### op fma [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE bdreg_lane:IMMEDIATE:-:- @far
fmla v3.2d,v1.2d,v2.d[1]
### op fma [] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF
fmla v3.8h,v1.8h,v2.8h
### op fma [] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:-
fmla v3.8h,v1.8h,v2.h[0]
### op fma [] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- @far
fmla v3.8h,v1.8h,v2.h[7]
### op fma [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE
fmla v3.4s,v1.4s,v2.4s
### op fma [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:-
fmla v3.4s,v1.4s,v2.s[0]
### op fma [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- @far
fmla v3.4s,v1.4s,v2.s[3]
### op fma [] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16
mla v3.8h,v1.8h,v2.8h
### op fma [] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:-
mla v3.8h,v1.8h,v2.h[0]
### op fma [] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- @far
mla v3.8h,v1.8h,v2.h[7]
### op fma [] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32
mla v3.4s,v1.4s,v2.4s
### op fma [] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:-
mla v3.4s,v1.4s,v2.s[0]
### op fma [] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- @far
mla v3.4s,v1.4s,v2.s[3]
### op fma [] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64
mla v3.2d,v1.2d,v2.2d
### op fma [] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64 bdreg_lane:IMMEDIATE:-:-
mla v3.2d,v1.2d,v2.d[0]
### op fma [] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64 bdreg_lane:IMMEDIATE:-:- @far
mla v3.2d,v1.2d,v2.d[1]
### op fma [] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8
mla v3.16b,v1.16b,v2.16b
### op fma [] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:-
mla v3.16b,v1.16b,v2.b[0]
### op fma [] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:- @far
mla v3.16b,v1.16b,v2.b[15]
### op load [GOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldr d1, [x10, x11]
### op load [GOFFSET] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldr b1, [x10, x11]
### op load [GOFFSET] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldr b1, [x10, x11]
### op load [GOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldr h1, [x10, x11]
### op load [GOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldr s1, [x10, x11]
### op load [GOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldrh w10, [x11, x12]
### op load [GOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldr w10, [x11, x12]
### op load [GOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldr x10, [x11, x12]
### op load [GOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldrb w10, [x11, x12]
### op load [GOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldrh w10, [x11, x12]
### op load [GOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldr w10, [x11, x12]
### op load [GOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldr x10, [x11, x12]
### op load [GOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldrb w10, [x11, x12]
### op load [IOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldr d1, [x10]
### op load [IOFFSET] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldr b1, [x10]
### op load [IOFFSET] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldr b1, [x10]
### op load [IOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldr h1, [x10]
### op load [IOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldr s1, [x10]
### op load [IOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldrh w10, [x11]
### op load [IOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldr w10, [x11]
### op load [IOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldr x10, [x11]
### op load [IOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldrb w10, [x11]
### op load [IOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldrh w10, [x11]
### op load [IOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldr w10, [x11]
### op load [IOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldr x10, [x11]
### op load [IOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldrb w10, [x11]
### op load [IOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
ldr q1, [x10]
### op load [IOFFSET] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
ldr q1, [x10]
### op load [IOFFSET] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
ldr q1, [x10]
### op load [IOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
ldr q1, [x10]
### op load [IOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
ldr q1, [x10]
### op load [IOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
ldr q1, [x10]
### op load [IOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
ldr q1, [x10]
### op load [IOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
ldr q1, [x10]
### op load [IOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
ldr q1, [x10]
### op load [IOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
ldr q1, [x10]
### op load [IOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
ldr q1, [x10]
### op load [IOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
ldr q1, [x10]
### op load [IOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
ldr q1, [x10]
### op load [PARAM] adreg:REGISTER:FP:DOUBLE param:NAME:-:-
ldr d1, %[p]
### op load [PARAM] adreg:REGISTER:FP:FP8E4M3 param:NAME:-:-
ldr b1, %[p]
### op load [PARAM] adreg:REGISTER:FP:FP8E5M2 param:NAME:-:-
ldr b1, %[p]
### op load [PARAM] adreg:REGISTER:FP:HALF param:NAME:-:-
ldr h1, %[p]
### op load [PARAM] adreg:REGISTER:FP:SINGLE param:NAME:-:-
ldr s1, %[p]
### op load [PARAM] adreg:REGISTER:GP:SINT16 param:NAME:-:-
ldrh w10, %[p]
### op load [PARAM] adreg:REGISTER:GP:SINT32 param:NAME:-:-
ldr w10, %[p]
### op load [PARAM] adreg:REGISTER:GP:SINT64 param:NAME:-:-
ldr x10, %[p]
### op load [PARAM] adreg:REGISTER:GP:SINT8 param:NAME:-:-
ldrb w10, %[p]
### op load [PARAM] adreg:REGISTER:GP:UINT16 param:NAME:-:-
ldrh w10, %[p]
### op load [PARAM] adreg:REGISTER:GP:UINT32 param:NAME:-:-
ldr w10, %[p]
### op load [PARAM] adreg:REGISTER:GP:UINT64 param:NAME:-:-
ldr x10, %[p]
### op load [PARAM] adreg:REGISTER:GP:UINT8 param:NAME:-:-
ldrb w10, %[p]
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE iinc:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.2d, v2.2d, v3.2d, v4.2d}, [x10], #64
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.2d, v2.2d, v3.2d, v4.2d}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE iinc:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.2d, v2.2d, v3.2d}, [x10], #48
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.2d, v2.2d, v3.2d}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE iinc:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.2d, v2.2d}, [x10], #32
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.2d, v2.2d}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{BCAST} cdreg:REGISTER:VEC:DOUBLE{BCAST} ddreg:REGISTER:VEC:DOUBLE{BCAST} iinc:IMMEDIATE:-:- {nstructs:4}
ld4r {v1.2d, v2.2d, v3.2d, v4.2d}, [x10], #32
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{BCAST} cdreg:REGISTER:VEC:DOUBLE{BCAST} ddreg:REGISTER:VEC:DOUBLE{BCAST} increg:REGISTER:GP:UINT64 {nstructs:4}
ld4r {v1.2d, v2.2d, v3.2d, v4.2d}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{BCAST} cdreg:REGISTER:VEC:DOUBLE{BCAST} iinc:IMMEDIATE:-:- {nstructs:3}
ld3r {v1.2d, v2.2d, v3.2d}, [x10], #24
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{BCAST} cdreg:REGISTER:VEC:DOUBLE{BCAST} increg:REGISTER:GP:UINT64 {nstructs:3}
ld3r {v1.2d, v2.2d, v3.2d}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{BCAST} iinc:IMMEDIATE:-:- {nstructs:2}
ld2r {v1.2d, v2.2d}, [x10], #16
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{BCAST} increg:REGISTER:GP:UINT64 {nstructs:2}
ld2r {v1.2d, v2.2d}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.d, v2.d}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
ld2 {v1.d, v2.d}[1], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.d, v2.d, v3.d}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
ld3 {v1.d, v2.d, v3.d}[1], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE{ILANE} ddreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.d, v2.d, v3.d, v4.d}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE{ILANE} ddreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
ld4 {v1.d, v2.d, v3.d, v4.d}[1], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 iinc:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], #64
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 iinc:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.16b, v2.16b, v3.16b}, [x10], #48
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.16b, v2.16b, v3.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3 iinc:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.16b, v2.16b}, [x10], #32
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3 increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.16b, v2.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{BCAST} cdreg:REGISTER:VEC:FP8E4M3{BCAST} ddreg:REGISTER:VEC:FP8E4M3{BCAST} iinc:IMMEDIATE:-:- {nstructs:4}
ld4r {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], #4
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{BCAST} cdreg:REGISTER:VEC:FP8E4M3{BCAST} ddreg:REGISTER:VEC:FP8E4M3{BCAST} increg:REGISTER:GP:UINT64 {nstructs:4}
ld4r {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{BCAST} cdreg:REGISTER:VEC:FP8E4M3{BCAST} iinc:IMMEDIATE:-:- {nstructs:3}
ld3r {v1.16b, v2.16b, v3.16b}, [x10], #3
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{BCAST} cdreg:REGISTER:VEC:FP8E4M3{BCAST} increg:REGISTER:GP:UINT64 {nstructs:3}
ld3r {v1.16b, v2.16b, v3.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{BCAST} iinc:IMMEDIATE:-:- {nstructs:2}
ld2r {v1.16b, v2.16b}, [x10], #2
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{BCAST} increg:REGISTER:GP:UINT64 {nstructs:2}
ld2r {v1.16b, v2.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.b, v2.b}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
ld2 {v1.b, v2.b}[15], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.b, v2.b, v3.b}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
ld3 {v1.b, v2.b, v3.b}[15], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:FP8E4M3{ILANE} ddreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.b, v2.b, v3.b, v4.b}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:FP8E4M3{ILANE} ddreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
ld4 {v1.b, v2.b, v3.b, v4.b}[15], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 iinc:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], #64
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 iinc:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.16b, v2.16b, v3.16b}, [x10], #48
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.16b, v2.16b, v3.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2 iinc:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.16b, v2.16b}, [x10], #32
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2 increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.16b, v2.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{BCAST} cdreg:REGISTER:VEC:FP8E5M2{BCAST} ddreg:REGISTER:VEC:FP8E5M2{BCAST} iinc:IMMEDIATE:-:- {nstructs:4}
ld4r {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], #4
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{BCAST} cdreg:REGISTER:VEC:FP8E5M2{BCAST} ddreg:REGISTER:VEC:FP8E5M2{BCAST} increg:REGISTER:GP:UINT64 {nstructs:4}
ld4r {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{BCAST} cdreg:REGISTER:VEC:FP8E5M2{BCAST} iinc:IMMEDIATE:-:- {nstructs:3}
ld3r {v1.16b, v2.16b, v3.16b}, [x10], #3
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{BCAST} cdreg:REGISTER:VEC:FP8E5M2{BCAST} increg:REGISTER:GP:UINT64 {nstructs:3}
ld3r {v1.16b, v2.16b, v3.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{BCAST} iinc:IMMEDIATE:-:- {nstructs:2}
ld2r {v1.16b, v2.16b}, [x10], #2
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{BCAST} increg:REGISTER:GP:UINT64 {nstructs:2}
ld2r {v1.16b, v2.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.b, v2.b}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
ld2 {v1.b, v2.b}[15], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.b, v2.b, v3.b}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
ld3 {v1.b, v2.b, v3.b}[15], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:FP8E5M2{ILANE} ddreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.b, v2.b, v3.b, v4.b}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:FP8E5M2{ILANE} ddreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
ld4 {v1.b, v2.b, v3.b, v4.b}[15], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF iinc:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.8h, v2.8h, v3.8h, v4.8h}, [x10], #64
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.8h, v2.8h, v3.8h, v4.8h}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF iinc:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.8h, v2.8h, v3.8h}, [x10], #48
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.8h, v2.8h, v3.8h}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF iinc:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.8h, v2.8h}, [x10], #32
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.8h, v2.8h}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{BCAST} cdreg:REGISTER:VEC:HALF{BCAST} ddreg:REGISTER:VEC:HALF{BCAST} iinc:IMMEDIATE:-:- {nstructs:4}
ld4r {v1.8h, v2.8h, v3.8h, v4.8h}, [x10], #8
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{BCAST} cdreg:REGISTER:VEC:HALF{BCAST} ddreg:REGISTER:VEC:HALF{BCAST} increg:REGISTER:GP:UINT64 {nstructs:4}
ld4r {v1.8h, v2.8h, v3.8h, v4.8h}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{BCAST} cdreg:REGISTER:VEC:HALF{BCAST} iinc:IMMEDIATE:-:- {nstructs:3}
ld3r {v1.8h, v2.8h, v3.8h}, [x10], #6
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{BCAST} cdreg:REGISTER:VEC:HALF{BCAST} increg:REGISTER:GP:UINT64 {nstructs:3}
ld3r {v1.8h, v2.8h, v3.8h}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{BCAST} iinc:IMMEDIATE:-:- {nstructs:2}
ld2r {v1.8h, v2.8h}, [x10], #4
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{BCAST} increg:REGISTER:GP:UINT64 {nstructs:2}
ld2r {v1.8h, v2.8h}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.h, v2.h}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
ld2 {v1.h, v2.h}[7], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.h, v2.h, v3.h}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
ld3 {v1.h, v2.h, v3.h}[7], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF{ILANE} ddreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.h, v2.h, v3.h, v4.h}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF{ILANE} ddreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
ld4 {v1.h, v2.h, v3.h, v4.h}[7], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE iinc:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.4s, v2.4s, v3.4s, v4.4s}, [x10], #64
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.4s, v2.4s, v3.4s, v4.4s}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE iinc:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.4s, v2.4s, v3.4s}, [x10], #48
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.4s, v2.4s, v3.4s}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE iinc:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.4s, v2.4s}, [x10], #32
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.4s, v2.4s}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{BCAST} cdreg:REGISTER:VEC:SINGLE{BCAST} ddreg:REGISTER:VEC:SINGLE{BCAST} iinc:IMMEDIATE:-:- {nstructs:4}
ld4r {v1.4s, v2.4s, v3.4s, v4.4s}, [x10], #16
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{BCAST} cdreg:REGISTER:VEC:SINGLE{BCAST} ddreg:REGISTER:VEC:SINGLE{BCAST} increg:REGISTER:GP:UINT64 {nstructs:4}
ld4r {v1.4s, v2.4s, v3.4s, v4.4s}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{BCAST} cdreg:REGISTER:VEC:SINGLE{BCAST} iinc:IMMEDIATE:-:- {nstructs:3}
ld3r {v1.4s, v2.4s, v3.4s}, [x10], #12
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{BCAST} cdreg:REGISTER:VEC:SINGLE{BCAST} increg:REGISTER:GP:UINT64 {nstructs:3}
ld3r {v1.4s, v2.4s, v3.4s}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{BCAST} iinc:IMMEDIATE:-:- {nstructs:2}
ld2r {v1.4s, v2.4s}, [x10], #8
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{BCAST} increg:REGISTER:GP:UINT64 {nstructs:2}
ld2r {v1.4s, v2.4s}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.s, v2.s}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
ld2 {v1.s, v2.s}[3], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.s, v2.s, v3.s}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
ld3 {v1.s, v2.s, v3.s}[3], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE{ILANE} ddreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.s, v2.s, v3.s, v4.s}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE{ILANE} ddreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
ld4 {v1.s, v2.s, v3.s, v4.s}[3], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 iinc:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.8h, v2.8h, v3.8h, v4.8h}, [x10], #64
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.8h, v2.8h, v3.8h, v4.8h}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 iinc:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.8h, v2.8h, v3.8h}, [x10], #48
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.8h, v2.8h, v3.8h}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16 iinc:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.8h, v2.8h}, [x10], #32
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16 increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.8h, v2.8h}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{BCAST} cdreg:REGISTER:VEC:SINT16{BCAST} ddreg:REGISTER:VEC:SINT16{BCAST} iinc:IMMEDIATE:-:- {nstructs:4}
ld4r {v1.8h, v2.8h, v3.8h, v4.8h}, [x10], #8
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{BCAST} cdreg:REGISTER:VEC:SINT16{BCAST} ddreg:REGISTER:VEC:SINT16{BCAST} increg:REGISTER:GP:UINT64 {nstructs:4}
ld4r {v1.8h, v2.8h, v3.8h, v4.8h}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{BCAST} cdreg:REGISTER:VEC:SINT16{BCAST} iinc:IMMEDIATE:-:- {nstructs:3}
ld3r {v1.8h, v2.8h, v3.8h}, [x10], #6
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{BCAST} cdreg:REGISTER:VEC:SINT16{BCAST} increg:REGISTER:GP:UINT64 {nstructs:3}
ld3r {v1.8h, v2.8h, v3.8h}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{BCAST} iinc:IMMEDIATE:-:- {nstructs:2}
ld2r {v1.8h, v2.8h}, [x10], #4
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{BCAST} increg:REGISTER:GP:UINT64 {nstructs:2}
ld2r {v1.8h, v2.8h}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.h, v2.h}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
ld2 {v1.h, v2.h}[7], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.h, v2.h, v3.h}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
ld3 {v1.h, v2.h, v3.h}[7], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16{ILANE} ddreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.h, v2.h, v3.h, v4.h}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16{ILANE} ddreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
ld4 {v1.h, v2.h, v3.h, v4.h}[7], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 iinc:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.4s, v2.4s, v3.4s, v4.4s}, [x10], #64
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.4s, v2.4s, v3.4s, v4.4s}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 iinc:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.4s, v2.4s, v3.4s}, [x10], #48
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.4s, v2.4s, v3.4s}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32 iinc:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.4s, v2.4s}, [x10], #32
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32 increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.4s, v2.4s}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{BCAST} cdreg:REGISTER:VEC:SINT32{BCAST} ddreg:REGISTER:VEC:SINT32{BCAST} iinc:IMMEDIATE:-:- {nstructs:4}
ld4r {v1.4s, v2.4s, v3.4s, v4.4s}, [x10], #16
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{BCAST} cdreg:REGISTER:VEC:SINT32{BCAST} ddreg:REGISTER:VEC:SINT32{BCAST} increg:REGISTER:GP:UINT64 {nstructs:4}
ld4r {v1.4s, v2.4s, v3.4s, v4.4s}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{BCAST} cdreg:REGISTER:VEC:SINT32{BCAST} iinc:IMMEDIATE:-:- {nstructs:3}
ld3r {v1.4s, v2.4s, v3.4s}, [x10], #12
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{BCAST} cdreg:REGISTER:VEC:SINT32{BCAST} increg:REGISTER:GP:UINT64 {nstructs:3}
ld3r {v1.4s, v2.4s, v3.4s}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{BCAST} iinc:IMMEDIATE:-:- {nstructs:2}
ld2r {v1.4s, v2.4s}, [x10], #8
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{BCAST} increg:REGISTER:GP:UINT64 {nstructs:2}
ld2r {v1.4s, v2.4s}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.s, v2.s}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
ld2 {v1.s, v2.s}[3], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.s, v2.s, v3.s}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
ld3 {v1.s, v2.s, v3.s}[3], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32{ILANE} ddreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.s, v2.s, v3.s, v4.s}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32{ILANE} ddreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
ld4 {v1.s, v2.s, v3.s, v4.s}[3], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 iinc:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.2d, v2.2d, v3.2d, v4.2d}, [x10], #64
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.2d, v2.2d, v3.2d, v4.2d}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 iinc:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.2d, v2.2d, v3.2d}, [x10], #48
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.2d, v2.2d, v3.2d}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64 iinc:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.2d, v2.2d}, [x10], #32
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64 increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.2d, v2.2d}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{BCAST} cdreg:REGISTER:VEC:SINT64{BCAST} ddreg:REGISTER:VEC:SINT64{BCAST} iinc:IMMEDIATE:-:- {nstructs:4}
ld4r {v1.2d, v2.2d, v3.2d, v4.2d}, [x10], #32
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{BCAST} cdreg:REGISTER:VEC:SINT64{BCAST} ddreg:REGISTER:VEC:SINT64{BCAST} increg:REGISTER:GP:UINT64 {nstructs:4}
ld4r {v1.2d, v2.2d, v3.2d, v4.2d}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{BCAST} cdreg:REGISTER:VEC:SINT64{BCAST} iinc:IMMEDIATE:-:- {nstructs:3}
ld3r {v1.2d, v2.2d, v3.2d}, [x10], #24
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{BCAST} cdreg:REGISTER:VEC:SINT64{BCAST} increg:REGISTER:GP:UINT64 {nstructs:3}
ld3r {v1.2d, v2.2d, v3.2d}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{BCAST} iinc:IMMEDIATE:-:- {nstructs:2}
ld2r {v1.2d, v2.2d}, [x10], #16
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{BCAST} increg:REGISTER:GP:UINT64 {nstructs:2}
ld2r {v1.2d, v2.2d}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.d, v2.d}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
ld2 {v1.d, v2.d}[1], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.d, v2.d, v3.d}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
ld3 {v1.d, v2.d, v3.d}[1], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64{ILANE} ddreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.d, v2.d, v3.d, v4.d}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64{ILANE} ddreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
ld4 {v1.d, v2.d, v3.d, v4.d}[1], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 iinc:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], #64
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 iinc:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.16b, v2.16b, v3.16b}, [x10], #48
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.16b, v2.16b, v3.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8 iinc:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.16b, v2.16b}, [x10], #32
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8 increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.16b, v2.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{BCAST} cdreg:REGISTER:VEC:SINT8{BCAST} ddreg:REGISTER:VEC:SINT8{BCAST} iinc:IMMEDIATE:-:- {nstructs:4}
ld4r {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], #4
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{BCAST} cdreg:REGISTER:VEC:SINT8{BCAST} ddreg:REGISTER:VEC:SINT8{BCAST} increg:REGISTER:GP:UINT64 {nstructs:4}
ld4r {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{BCAST} cdreg:REGISTER:VEC:SINT8{BCAST} iinc:IMMEDIATE:-:- {nstructs:3}
ld3r {v1.16b, v2.16b, v3.16b}, [x10], #3
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{BCAST} cdreg:REGISTER:VEC:SINT8{BCAST} increg:REGISTER:GP:UINT64 {nstructs:3}
ld3r {v1.16b, v2.16b, v3.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{BCAST} iinc:IMMEDIATE:-:- {nstructs:2}
ld2r {v1.16b, v2.16b}, [x10], #2
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{BCAST} increg:REGISTER:GP:UINT64 {nstructs:2}
ld2r {v1.16b, v2.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.b, v2.b}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
ld2 {v1.b, v2.b}[15], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.b, v2.b, v3.b}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
ld3 {v1.b, v2.b, v3.b}[15], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8{ILANE} ddreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.b, v2.b, v3.b, v4.b}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8{ILANE} ddreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
ld4 {v1.b, v2.b, v3.b, v4.b}[15], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 iinc:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.8h, v2.8h, v3.8h, v4.8h}, [x10], #64
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.8h, v2.8h, v3.8h, v4.8h}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 iinc:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.8h, v2.8h, v3.8h}, [x10], #48
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.8h, v2.8h, v3.8h}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16 iinc:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.8h, v2.8h}, [x10], #32
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16 increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.8h, v2.8h}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{BCAST} cdreg:REGISTER:VEC:UINT16{BCAST} ddreg:REGISTER:VEC:UINT16{BCAST} iinc:IMMEDIATE:-:- {nstructs:4}
ld4r {v1.8h, v2.8h, v3.8h, v4.8h}, [x10], #8
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{BCAST} cdreg:REGISTER:VEC:UINT16{BCAST} ddreg:REGISTER:VEC:UINT16{BCAST} increg:REGISTER:GP:UINT64 {nstructs:4}
ld4r {v1.8h, v2.8h, v3.8h, v4.8h}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{BCAST} cdreg:REGISTER:VEC:UINT16{BCAST} iinc:IMMEDIATE:-:- {nstructs:3}
ld3r {v1.8h, v2.8h, v3.8h}, [x10], #6
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{BCAST} cdreg:REGISTER:VEC:UINT16{BCAST} increg:REGISTER:GP:UINT64 {nstructs:3}
ld3r {v1.8h, v2.8h, v3.8h}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{BCAST} iinc:IMMEDIATE:-:- {nstructs:2}
ld2r {v1.8h, v2.8h}, [x10], #4
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{BCAST} increg:REGISTER:GP:UINT64 {nstructs:2}
ld2r {v1.8h, v2.8h}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.h, v2.h}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
ld2 {v1.h, v2.h}[7], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} cdreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.h, v2.h, v3.h}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} cdreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
ld3 {v1.h, v2.h, v3.h}[7], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} cdreg:REGISTER:VEC:UINT16{ILANE} ddreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.h, v2.h, v3.h, v4.h}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} cdreg:REGISTER:VEC:UINT16{ILANE} ddreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
ld4 {v1.h, v2.h, v3.h, v4.h}[7], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 iinc:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.4s, v2.4s, v3.4s, v4.4s}, [x10], #64
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.4s, v2.4s, v3.4s, v4.4s}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 iinc:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.4s, v2.4s, v3.4s}, [x10], #48
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.4s, v2.4s, v3.4s}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32 iinc:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.4s, v2.4s}, [x10], #32
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32 increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.4s, v2.4s}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{BCAST} cdreg:REGISTER:VEC:UINT32{BCAST} ddreg:REGISTER:VEC:UINT32{BCAST} iinc:IMMEDIATE:-:- {nstructs:4}
ld4r {v1.4s, v2.4s, v3.4s, v4.4s}, [x10], #16
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{BCAST} cdreg:REGISTER:VEC:UINT32{BCAST} ddreg:REGISTER:VEC:UINT32{BCAST} increg:REGISTER:GP:UINT64 {nstructs:4}
ld4r {v1.4s, v2.4s, v3.4s, v4.4s}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{BCAST} cdreg:REGISTER:VEC:UINT32{BCAST} iinc:IMMEDIATE:-:- {nstructs:3}
ld3r {v1.4s, v2.4s, v3.4s}, [x10], #12
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{BCAST} cdreg:REGISTER:VEC:UINT32{BCAST} increg:REGISTER:GP:UINT64 {nstructs:3}
ld3r {v1.4s, v2.4s, v3.4s}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{BCAST} iinc:IMMEDIATE:-:- {nstructs:2}
ld2r {v1.4s, v2.4s}, [x10], #8
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{BCAST} increg:REGISTER:GP:UINT64 {nstructs:2}
ld2r {v1.4s, v2.4s}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.s, v2.s}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
ld2 {v1.s, v2.s}[3], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} cdreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.s, v2.s, v3.s}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} cdreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
ld3 {v1.s, v2.s, v3.s}[3], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} cdreg:REGISTER:VEC:UINT32{ILANE} ddreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.s, v2.s, v3.s, v4.s}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} cdreg:REGISTER:VEC:UINT32{ILANE} ddreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
ld4 {v1.s, v2.s, v3.s, v4.s}[3], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 iinc:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.2d, v2.2d, v3.2d, v4.2d}, [x10], #64
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.2d, v2.2d, v3.2d, v4.2d}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 iinc:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.2d, v2.2d, v3.2d}, [x10], #48
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.2d, v2.2d, v3.2d}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64 iinc:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.2d, v2.2d}, [x10], #32
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64 increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.2d, v2.2d}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{BCAST} cdreg:REGISTER:VEC:UINT64{BCAST} ddreg:REGISTER:VEC:UINT64{BCAST} iinc:IMMEDIATE:-:- {nstructs:4}
ld4r {v1.2d, v2.2d, v3.2d, v4.2d}, [x10], #32
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{BCAST} cdreg:REGISTER:VEC:UINT64{BCAST} ddreg:REGISTER:VEC:UINT64{BCAST} increg:REGISTER:GP:UINT64 {nstructs:4}
ld4r {v1.2d, v2.2d, v3.2d, v4.2d}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{BCAST} cdreg:REGISTER:VEC:UINT64{BCAST} iinc:IMMEDIATE:-:- {nstructs:3}
ld3r {v1.2d, v2.2d, v3.2d}, [x10], #24
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{BCAST} cdreg:REGISTER:VEC:UINT64{BCAST} increg:REGISTER:GP:UINT64 {nstructs:3}
ld3r {v1.2d, v2.2d, v3.2d}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{BCAST} iinc:IMMEDIATE:-:- {nstructs:2}
ld2r {v1.2d, v2.2d}, [x10], #16
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{BCAST} increg:REGISTER:GP:UINT64 {nstructs:2}
ld2r {v1.2d, v2.2d}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.d, v2.d}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
ld2 {v1.d, v2.d}[1], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} cdreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.d, v2.d, v3.d}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} cdreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
ld3 {v1.d, v2.d, v3.d}[1], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} cdreg:REGISTER:VEC:UINT64{ILANE} ddreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.d, v2.d, v3.d, v4.d}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} cdreg:REGISTER:VEC:UINT64{ILANE} ddreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
ld4 {v1.d, v2.d, v3.d, v4.d}[1], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 iinc:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], #64
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 iinc:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.16b, v2.16b, v3.16b}, [x10], #48
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.16b, v2.16b, v3.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8 iinc:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.16b, v2.16b}, [x10], #32
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8 increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.16b, v2.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{BCAST} cdreg:REGISTER:VEC:UINT8{BCAST} ddreg:REGISTER:VEC:UINT8{BCAST} iinc:IMMEDIATE:-:- {nstructs:4}
ld4r {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], #4
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{BCAST} cdreg:REGISTER:VEC:UINT8{BCAST} ddreg:REGISTER:VEC:UINT8{BCAST} increg:REGISTER:GP:UINT64 {nstructs:4}
ld4r {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{BCAST} cdreg:REGISTER:VEC:UINT8{BCAST} iinc:IMMEDIATE:-:- {nstructs:3}
ld3r {v1.16b, v2.16b, v3.16b}, [x10], #3
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{BCAST} cdreg:REGISTER:VEC:UINT8{BCAST} increg:REGISTER:GP:UINT64 {nstructs:3}
ld3r {v1.16b, v2.16b, v3.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{BCAST} iinc:IMMEDIATE:-:- {nstructs:2}
ld2r {v1.16b, v2.16b}, [x10], #2
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{BCAST} increg:REGISTER:GP:UINT64 {nstructs:2}
ld2r {v1.16b, v2.16b}, [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
ld2 {v1.b, v2.b}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
ld2 {v1.b, v2.b}[15], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
ld3 {v1.b, v2.b, v3.b}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
ld3 {v1.b, v2.b, v3.b}[15], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT8{ILANE} ddreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
ld4 {v1.b, v2.b, v3.b, v4.b}[0], [x10], x11
### op load [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT8{ILANE} ddreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
ld4 {v1.b, v2.b, v3.b, v4.b}[15], [x10], x11
### op load [POSTINC] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldr d1, [x10], #-256
### op load [POSTINC] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldr d1, [x10], #255
### op load [POSTINC] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldr d1, [x10], x11
### op load [POSTINC] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldr b1, [x10], #-256
### op load [POSTINC] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldr b1, [x10], #255
### op load [POSTINC] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldr b1, [x10], x11
### op load [POSTINC] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldr b1, [x10], #-256
### op load [POSTINC] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldr b1, [x10], #255
### op load [POSTINC] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldr b1, [x10], x11
### op load [POSTINC] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldr h1, [x10], #-256
### op load [POSTINC] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldr h1, [x10], #255
### op load [POSTINC] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldr h1, [x10], x11
### op load [POSTINC] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldr s1, [x10], #-256
### op load [POSTINC] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldr s1, [x10], #255
### op load [POSTINC] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldr s1, [x10], x11
### op load [POSTINC] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldrh w10, [x11], #-256
### op load [POSTINC] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldrh w10, [x11], #255
### op load [POSTINC] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldrh w10, [x11], x12
### op load [POSTINC] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldr w10, [x11], #-256
### op load [POSTINC] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldr w10, [x11], #255
### op load [POSTINC] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldr w10, [x11], x12
### op load [POSTINC] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldr x10, [x11], #-256
### op load [POSTINC] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldr x10, [x11], #255
### op load [POSTINC] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldr x10, [x11], x12
### op load [POSTINC] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldrb w10, [x11], #-256
### op load [POSTINC] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldrb w10, [x11], #255
### op load [POSTINC] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldrb w10, [x11], x12
### op load [POSTINC] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldrh w10, [x11], #-256
### op load [POSTINC] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldrh w10, [x11], #255
### op load [POSTINC] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldrh w10, [x11], x12
### op load [POSTINC] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldr w10, [x11], #-256
### op load [POSTINC] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldr w10, [x11], #255
### op load [POSTINC] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldr w10, [x11], x12
### op load [POSTINC] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldr x10, [x11], #-256
### op load [POSTINC] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldr x10, [x11], #255
### op load [POSTINC] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldr x10, [x11], x12
### op load [POSTINC] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldrb w10, [x11], #-256
### op load [POSTINC] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldrb w10, [x11], #255
### op load [POSTINC] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldrb w10, [x11], x12
### op load [POSTINC] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ldr q1, [x10], #-256
### op load [POSTINC] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
ldr q1, [x10], #255
### op load [POSTINC] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1 {v1.2d}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ld1r {v1.2d}, [x10], #8
### op load [POSTINC] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1r {v1.2d}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
ld1 {v1.d}[0], [x10], #8
### op load [POSTINC] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
ld1 {v1.d}[1], [x10], #8
### op load [POSTINC] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
ld1 {v1.d}[0], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
ld1 {v1.d}[1], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ldr q1, [x10], #-256
### op load [POSTINC] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
ldr q1, [x10], #255
### op load [POSTINC] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1 {v1.16b}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:FP8E4M3{BCAST} agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ld1r {v1.16b}, [x10], #1
### op load [POSTINC] adreg:REGISTER:VEC:FP8E4M3{BCAST} agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1r {v1.16b}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
ld1 {v1.b}[0], [x10], #1
### op load [POSTINC] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
ld1 {v1.b}[15], [x10], #1
### op load [POSTINC] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
ld1 {v1.b}[0], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
ld1 {v1.b}[15], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ldr q1, [x10], #-256
### op load [POSTINC] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
ldr q1, [x10], #255
### op load [POSTINC] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1 {v1.16b}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:FP8E5M2{BCAST} agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ld1r {v1.16b}, [x10], #1
### op load [POSTINC] adreg:REGISTER:VEC:FP8E5M2{BCAST} agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1r {v1.16b}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
ld1 {v1.b}[0], [x10], #1
### op load [POSTINC] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
ld1 {v1.b}[15], [x10], #1
### op load [POSTINC] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
ld1 {v1.b}[0], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
ld1 {v1.b}[15], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ldr q1, [x10], #-256
### op load [POSTINC] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
ldr q1, [x10], #255
### op load [POSTINC] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1 {v1.8h}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:HALF{BCAST} agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ld1r {v1.8h}, [x10], #2
### op load [POSTINC] adreg:REGISTER:VEC:HALF{BCAST} agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1r {v1.8h}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
ld1 {v1.h}[0], [x10], #2
### op load [POSTINC] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
ld1 {v1.h}[7], [x10], #2
### op load [POSTINC] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
ld1 {v1.h}[0], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
ld1 {v1.h}[7], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ldr q1, [x10], #-256
### op load [POSTINC] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
ldr q1, [x10], #255
### op load [POSTINC] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1 {v1.4s}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ld1r {v1.4s}, [x10], #4
### op load [POSTINC] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1r {v1.4s}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
ld1 {v1.s}[0], [x10], #4
### op load [POSTINC] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
ld1 {v1.s}[3], [x10], #4
### op load [POSTINC] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
ld1 {v1.s}[0], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
ld1 {v1.s}[3], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ldr q1, [x10], #-256
### op load [POSTINC] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
ldr q1, [x10], #255
### op load [POSTINC] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1 {v1.8h}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:SINT16{BCAST} agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ld1r {v1.8h}, [x10], #2
### op load [POSTINC] adreg:REGISTER:VEC:SINT16{BCAST} agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1r {v1.8h}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
ld1 {v1.h}[0], [x10], #2
### op load [POSTINC] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
ld1 {v1.h}[7], [x10], #2
### op load [POSTINC] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
ld1 {v1.h}[0], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
ld1 {v1.h}[7], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ldr q1, [x10], #-256
### op load [POSTINC] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
ldr q1, [x10], #255
### op load [POSTINC] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1 {v1.4s}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ld1r {v1.4s}, [x10], #4
### op load [POSTINC] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1r {v1.4s}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
ld1 {v1.s}[0], [x10], #4
### op load [POSTINC] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
ld1 {v1.s}[3], [x10], #4
### op load [POSTINC] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
ld1 {v1.s}[0], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
ld1 {v1.s}[3], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ldr q1, [x10], #-256
### op load [POSTINC] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
ldr q1, [x10], #255
### op load [POSTINC] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1 {v1.2d}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ld1r {v1.2d}, [x10], #8
### op load [POSTINC] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1r {v1.2d}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
ld1 {v1.d}[0], [x10], #8
### op load [POSTINC] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
ld1 {v1.d}[1], [x10], #8
### op load [POSTINC] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
ld1 {v1.d}[0], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
ld1 {v1.d}[1], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ldr q1, [x10], #-256
### op load [POSTINC] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
ldr q1, [x10], #255
### op load [POSTINC] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1 {v1.16b}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:SINT8{BCAST} agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ld1r {v1.16b}, [x10], #1
### op load [POSTINC] adreg:REGISTER:VEC:SINT8{BCAST} agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1r {v1.16b}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
ld1 {v1.b}[0], [x10], #1
### op load [POSTINC] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
ld1 {v1.b}[15], [x10], #1
### op load [POSTINC] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
ld1 {v1.b}[0], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
ld1 {v1.b}[15], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ldr q1, [x10], #-256
### op load [POSTINC] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
ldr q1, [x10], #255
### op load [POSTINC] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1 {v1.8h}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:UINT16{BCAST} agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ld1r {v1.8h}, [x10], #2
### op load [POSTINC] adreg:REGISTER:VEC:UINT16{BCAST} agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1r {v1.8h}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
ld1 {v1.h}[0], [x10], #2
### op load [POSTINC] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
ld1 {v1.h}[7], [x10], #2
### op load [POSTINC] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
ld1 {v1.h}[0], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
ld1 {v1.h}[7], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ldr q1, [x10], #-256
### op load [POSTINC] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
ldr q1, [x10], #255
### op load [POSTINC] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1 {v1.4s}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ld1r {v1.4s}, [x10], #4
### op load [POSTINC] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1r {v1.4s}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
ld1 {v1.s}[0], [x10], #4
### op load [POSTINC] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
ld1 {v1.s}[3], [x10], #4
### op load [POSTINC] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
ld1 {v1.s}[0], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
ld1 {v1.s}[3], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ldr q1, [x10], #-256
### op load [POSTINC] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
ldr q1, [x10], #255
### op load [POSTINC] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1 {v1.2d}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ld1r {v1.2d}, [x10], #8
### op load [POSTINC] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1r {v1.2d}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
ld1 {v1.d}[0], [x10], #8
### op load [POSTINC] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
ld1 {v1.d}[1], [x10], #8
### op load [POSTINC] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
ld1 {v1.d}[0], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
ld1 {v1.d}[1], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ldr q1, [x10], #-256
### op load [POSTINC] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
ldr q1, [x10], #255
### op load [POSTINC] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1 {v1.16b}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:UINT8{BCAST} agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
ld1r {v1.16b}, [x10], #1
### op load [POSTINC] adreg:REGISTER:VEC:UINT8{BCAST} agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ld1r {v1.16b}, [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
ld1 {v1.b}[0], [x10], #1
### op load [POSTINC] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
ld1 {v1.b}[15], [x10], #1
### op load [POSTINC] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
ld1 {v1.b}[0], [x10], x11
### op load [POSTINC] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
ld1 {v1.b}[15], [x10], x11
### op load [STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE {nstructs:4}
ld4 {v1.2d, v2.2d, v3.2d, v4.2d}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE {nstructs:3}
ld3 {v1.2d, v2.2d, v3.2d}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE {nstructs:2}
ld2 {v1.2d, v2.2d}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{BCAST} cdreg:REGISTER:VEC:DOUBLE{BCAST} ddreg:REGISTER:VEC:DOUBLE{BCAST} {nstructs:4}
ld4r {v1.2d, v2.2d, v3.2d, v4.2d}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{BCAST} cdreg:REGISTER:VEC:DOUBLE{BCAST} {nstructs:3}
ld3r {v1.2d, v2.2d, v3.2d}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{BCAST} {nstructs:2}
ld2r {v1.2d, v2.2d}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.d, v2.d}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
ld2 {v1.d, v2.d}[1], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.d, v2.d, v3.d}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
ld3 {v1.d, v2.d, v3.d}[1], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE{ILANE} ddreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.d, v2.d, v3.d, v4.d}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE{ILANE} ddreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
ld4 {v1.d, v2.d, v3.d, v4.d}[1], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 {nstructs:4}
ld4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 {nstructs:3}
ld3 {v1.16b, v2.16b, v3.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3 {nstructs:2}
ld2 {v1.16b, v2.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E4M3{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{BCAST} cdreg:REGISTER:VEC:FP8E4M3{BCAST} ddreg:REGISTER:VEC:FP8E4M3{BCAST} {nstructs:4}
ld4r {v1.16b, v2.16b, v3.16b, v4.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E4M3{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{BCAST} cdreg:REGISTER:VEC:FP8E4M3{BCAST} {nstructs:3}
ld3r {v1.16b, v2.16b, v3.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E4M3{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{BCAST} {nstructs:2}
ld2r {v1.16b, v2.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.b, v2.b}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
ld2 {v1.b, v2.b}[15], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.b, v2.b, v3.b}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
ld3 {v1.b, v2.b, v3.b}[15], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:FP8E4M3{ILANE} ddreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.b, v2.b, v3.b, v4.b}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:FP8E4M3{ILANE} ddreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
ld4 {v1.b, v2.b, v3.b, v4.b}[15], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 {nstructs:4}
ld4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 {nstructs:3}
ld3 {v1.16b, v2.16b, v3.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2 {nstructs:2}
ld2 {v1.16b, v2.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E5M2{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{BCAST} cdreg:REGISTER:VEC:FP8E5M2{BCAST} ddreg:REGISTER:VEC:FP8E5M2{BCAST} {nstructs:4}
ld4r {v1.16b, v2.16b, v3.16b, v4.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E5M2{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{BCAST} cdreg:REGISTER:VEC:FP8E5M2{BCAST} {nstructs:3}
ld3r {v1.16b, v2.16b, v3.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E5M2{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{BCAST} {nstructs:2}
ld2r {v1.16b, v2.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.b, v2.b}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
ld2 {v1.b, v2.b}[15], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.b, v2.b, v3.b}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
ld3 {v1.b, v2.b, v3.b}[15], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:FP8E5M2{ILANE} ddreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.b, v2.b, v3.b, v4.b}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:FP8E5M2{ILANE} ddreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
ld4 {v1.b, v2.b, v3.b, v4.b}[15], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF {nstructs:4}
ld4 {v1.8h, v2.8h, v3.8h, v4.8h}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF {nstructs:3}
ld3 {v1.8h, v2.8h, v3.8h}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF {nstructs:2}
ld2 {v1.8h, v2.8h}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:HALF{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{BCAST} cdreg:REGISTER:VEC:HALF{BCAST} ddreg:REGISTER:VEC:HALF{BCAST} {nstructs:4}
ld4r {v1.8h, v2.8h, v3.8h, v4.8h}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:HALF{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{BCAST} cdreg:REGISTER:VEC:HALF{BCAST} {nstructs:3}
ld3r {v1.8h, v2.8h, v3.8h}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:HALF{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{BCAST} {nstructs:2}
ld2r {v1.8h, v2.8h}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.h, v2.h}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
ld2 {v1.h, v2.h}[7], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.h, v2.h, v3.h}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
ld3 {v1.h, v2.h, v3.h}[7], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF{ILANE} ddreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.h, v2.h, v3.h, v4.h}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF{ILANE} ddreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
ld4 {v1.h, v2.h, v3.h, v4.h}[7], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE {nstructs:4}
ld4 {v1.4s, v2.4s, v3.4s, v4.4s}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {nstructs:3}
ld3 {v1.4s, v2.4s, v3.4s}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE {nstructs:2}
ld2 {v1.4s, v2.4s}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{BCAST} cdreg:REGISTER:VEC:SINGLE{BCAST} ddreg:REGISTER:VEC:SINGLE{BCAST} {nstructs:4}
ld4r {v1.4s, v2.4s, v3.4s, v4.4s}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{BCAST} cdreg:REGISTER:VEC:SINGLE{BCAST} {nstructs:3}
ld3r {v1.4s, v2.4s, v3.4s}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{BCAST} {nstructs:2}
ld2r {v1.4s, v2.4s}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.s, v2.s}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
ld2 {v1.s, v2.s}[3], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.s, v2.s, v3.s}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
ld3 {v1.s, v2.s, v3.s}[3], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE{ILANE} ddreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.s, v2.s, v3.s, v4.s}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE{ILANE} ddreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
ld4 {v1.s, v2.s, v3.s, v4.s}[3], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 {nstructs:4}
ld4 {v1.8h, v2.8h, v3.8h, v4.8h}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 {nstructs:3}
ld3 {v1.8h, v2.8h, v3.8h}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16 {nstructs:2}
ld2 {v1.8h, v2.8h}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT16{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{BCAST} cdreg:REGISTER:VEC:SINT16{BCAST} ddreg:REGISTER:VEC:SINT16{BCAST} {nstructs:4}
ld4r {v1.8h, v2.8h, v3.8h, v4.8h}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT16{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{BCAST} cdreg:REGISTER:VEC:SINT16{BCAST} {nstructs:3}
ld3r {v1.8h, v2.8h, v3.8h}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT16{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{BCAST} {nstructs:2}
ld2r {v1.8h, v2.8h}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.h, v2.h}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
ld2 {v1.h, v2.h}[7], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.h, v2.h, v3.h}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
ld3 {v1.h, v2.h, v3.h}[7], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16{ILANE} ddreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.h, v2.h, v3.h, v4.h}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16{ILANE} ddreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
ld4 {v1.h, v2.h, v3.h, v4.h}[7], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 {nstructs:4}
ld4 {v1.4s, v2.4s, v3.4s, v4.4s}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {nstructs:3}
ld3 {v1.4s, v2.4s, v3.4s}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32 {nstructs:2}
ld2 {v1.4s, v2.4s}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{BCAST} cdreg:REGISTER:VEC:SINT32{BCAST} ddreg:REGISTER:VEC:SINT32{BCAST} {nstructs:4}
ld4r {v1.4s, v2.4s, v3.4s, v4.4s}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{BCAST} cdreg:REGISTER:VEC:SINT32{BCAST} {nstructs:3}
ld3r {v1.4s, v2.4s, v3.4s}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{BCAST} {nstructs:2}
ld2r {v1.4s, v2.4s}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.s, v2.s}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
ld2 {v1.s, v2.s}[3], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.s, v2.s, v3.s}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
ld3 {v1.s, v2.s, v3.s}[3], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32{ILANE} ddreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.s, v2.s, v3.s, v4.s}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32{ILANE} ddreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
ld4 {v1.s, v2.s, v3.s, v4.s}[3], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 {nstructs:4}
ld4 {v1.2d, v2.2d, v3.2d, v4.2d}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 {nstructs:3}
ld3 {v1.2d, v2.2d, v3.2d}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64 {nstructs:2}
ld2 {v1.2d, v2.2d}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{BCAST} cdreg:REGISTER:VEC:SINT64{BCAST} ddreg:REGISTER:VEC:SINT64{BCAST} {nstructs:4}
ld4r {v1.2d, v2.2d, v3.2d, v4.2d}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{BCAST} cdreg:REGISTER:VEC:SINT64{BCAST} {nstructs:3}
ld3r {v1.2d, v2.2d, v3.2d}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{BCAST} {nstructs:2}
ld2r {v1.2d, v2.2d}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.d, v2.d}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
ld2 {v1.d, v2.d}[1], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.d, v2.d, v3.d}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
ld3 {v1.d, v2.d, v3.d}[1], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64{ILANE} ddreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.d, v2.d, v3.d, v4.d}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64{ILANE} ddreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
ld4 {v1.d, v2.d, v3.d, v4.d}[1], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 {nstructs:4}
ld4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {nstructs:3}
ld3 {v1.16b, v2.16b, v3.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8 {nstructs:2}
ld2 {v1.16b, v2.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT8{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{BCAST} cdreg:REGISTER:VEC:SINT8{BCAST} ddreg:REGISTER:VEC:SINT8{BCAST} {nstructs:4}
ld4r {v1.16b, v2.16b, v3.16b, v4.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT8{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{BCAST} cdreg:REGISTER:VEC:SINT8{BCAST} {nstructs:3}
ld3r {v1.16b, v2.16b, v3.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT8{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{BCAST} {nstructs:2}
ld2r {v1.16b, v2.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.b, v2.b}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
ld2 {v1.b, v2.b}[15], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.b, v2.b, v3.b}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
ld3 {v1.b, v2.b, v3.b}[15], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8{ILANE} ddreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.b, v2.b, v3.b, v4.b}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8{ILANE} ddreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
ld4 {v1.b, v2.b, v3.b, v4.b}[15], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 {nstructs:4}
ld4 {v1.8h, v2.8h, v3.8h, v4.8h}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 {nstructs:3}
ld3 {v1.8h, v2.8h, v3.8h}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16 {nstructs:2}
ld2 {v1.8h, v2.8h}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT16{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{BCAST} cdreg:REGISTER:VEC:UINT16{BCAST} ddreg:REGISTER:VEC:UINT16{BCAST} {nstructs:4}
ld4r {v1.8h, v2.8h, v3.8h, v4.8h}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT16{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{BCAST} cdreg:REGISTER:VEC:UINT16{BCAST} {nstructs:3}
ld3r {v1.8h, v2.8h, v3.8h}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT16{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{BCAST} {nstructs:2}
ld2r {v1.8h, v2.8h}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.h, v2.h}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
ld2 {v1.h, v2.h}[7], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} cdreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.h, v2.h, v3.h}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} cdreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
ld3 {v1.h, v2.h, v3.h}[7], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} cdreg:REGISTER:VEC:UINT16{ILANE} ddreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.h, v2.h, v3.h, v4.h}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} cdreg:REGISTER:VEC:UINT16{ILANE} ddreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
ld4 {v1.h, v2.h, v3.h, v4.h}[7], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 {nstructs:4}
ld4 {v1.4s, v2.4s, v3.4s, v4.4s}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {nstructs:3}
ld3 {v1.4s, v2.4s, v3.4s}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32 {nstructs:2}
ld2 {v1.4s, v2.4s}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{BCAST} cdreg:REGISTER:VEC:UINT32{BCAST} ddreg:REGISTER:VEC:UINT32{BCAST} {nstructs:4}
ld4r {v1.4s, v2.4s, v3.4s, v4.4s}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{BCAST} cdreg:REGISTER:VEC:UINT32{BCAST} {nstructs:3}
ld3r {v1.4s, v2.4s, v3.4s}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{BCAST} {nstructs:2}
ld2r {v1.4s, v2.4s}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.s, v2.s}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
ld2 {v1.s, v2.s}[3], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} cdreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.s, v2.s, v3.s}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} cdreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
ld3 {v1.s, v2.s, v3.s}[3], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} cdreg:REGISTER:VEC:UINT32{ILANE} ddreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.s, v2.s, v3.s, v4.s}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} cdreg:REGISTER:VEC:UINT32{ILANE} ddreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
ld4 {v1.s, v2.s, v3.s, v4.s}[3], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 {nstructs:4}
ld4 {v1.2d, v2.2d, v3.2d, v4.2d}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 {nstructs:3}
ld3 {v1.2d, v2.2d, v3.2d}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64 {nstructs:2}
ld2 {v1.2d, v2.2d}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{BCAST} cdreg:REGISTER:VEC:UINT64{BCAST} ddreg:REGISTER:VEC:UINT64{BCAST} {nstructs:4}
ld4r {v1.2d, v2.2d, v3.2d, v4.2d}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{BCAST} cdreg:REGISTER:VEC:UINT64{BCAST} {nstructs:3}
ld3r {v1.2d, v2.2d, v3.2d}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{BCAST} {nstructs:2}
ld2r {v1.2d, v2.2d}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.d, v2.d}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
ld2 {v1.d, v2.d}[1], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} cdreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.d, v2.d, v3.d}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} cdreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
ld3 {v1.d, v2.d, v3.d}[1], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} cdreg:REGISTER:VEC:UINT64{ILANE} ddreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.d, v2.d, v3.d, v4.d}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} cdreg:REGISTER:VEC:UINT64{ILANE} ddreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
ld4 {v1.d, v2.d, v3.d, v4.d}[1], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 {nstructs:4}
ld4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {nstructs:3}
ld3 {v1.16b, v2.16b, v3.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8 {nstructs:2}
ld2 {v1.16b, v2.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT8{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{BCAST} cdreg:REGISTER:VEC:UINT8{BCAST} ddreg:REGISTER:VEC:UINT8{BCAST} {nstructs:4}
ld4r {v1.16b, v2.16b, v3.16b, v4.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT8{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{BCAST} cdreg:REGISTER:VEC:UINT8{BCAST} {nstructs:3}
ld3r {v1.16b, v2.16b, v3.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT8{BCAST} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{BCAST} {nstructs:2}
ld2r {v1.16b, v2.16b}, [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
ld2 {v1.b, v2.b}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
ld2 {v1.b, v2.b}[15], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
ld3 {v1.b, v2.b, v3.b}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
ld3 {v1.b, v2.b, v3.b}[15], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT8{ILANE} ddreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
ld4 {v1.b, v2.b, v3.b, v4.b}[0], [x10]
### op load [STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT8{ILANE} ddreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
ld4 {v1.b, v2.b, v3.b, v4.b}[15], [x10]
### op load [VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [VOFFSET] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
ldr q1, [x10, #-256]
### op load [VOFFSET] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
ldr q1, [x10, #65520]
### op load [] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64
ldr d1, [x10]
### op load [] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64
ldr b1, [x10]
### op load [] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64
ldr b1, [x10]
### op load [] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64
ldr h1, [x10]
### op load [] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64
ldr s1, [x10]
### op load [] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64
ldrh w10, [x11]
### op load [] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64
ldr w10, [x11]
### op load [] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64
ldr x10, [x11]
### op load [] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64
ldrb w10, [x11]
### op load [] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64
ldrh w10, [x11]
### op load [] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64
ldr w10, [x11]
### op load [] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64
ldr x10, [x11]
### op load [] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64
ldrb w10, [x11]
### op load [] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64
ld1 {v1.2d}, [x10]
### op load [] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64
ld1r {v1.2d}, [x10]
### op load [] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
ld1 {v1.d}[0], [x10]
### op load [] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
ld1 {v1.d}[1], [x10]
### op load [] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64
ld1 {v1.16b}, [x10]
### op load [] adreg:REGISTER:VEC:FP8E4M3{BCAST} agreg:REGISTER:GP:UINT64
ld1r {v1.16b}, [x10]
### op load [] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
ld1 {v1.b}[0], [x10]
### op load [] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
ld1 {v1.b}[15], [x10]
### op load [] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64
ld1 {v1.16b}, [x10]
### op load [] adreg:REGISTER:VEC:FP8E5M2{BCAST} agreg:REGISTER:GP:UINT64
ld1r {v1.16b}, [x10]
### op load [] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
ld1 {v1.b}[0], [x10]
### op load [] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
ld1 {v1.b}[15], [x10]
### op load [] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64
ld1 {v1.8h}, [x10]
### op load [] adreg:REGISTER:VEC:HALF{BCAST} agreg:REGISTER:GP:UINT64
ld1r {v1.8h}, [x10]
### op load [] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
ld1 {v1.h}[0], [x10]
### op load [] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
ld1 {v1.h}[7], [x10]
### op load [] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64
ld1 {v1.4s}, [x10]
### op load [] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64
ld1r {v1.4s}, [x10]
### op load [] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
ld1 {v1.s}[0], [x10]
### op load [] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
ld1 {v1.s}[3], [x10]
### op load [] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64
ld1 {v1.8h}, [x10]
### op load [] adreg:REGISTER:VEC:SINT16{BCAST} agreg:REGISTER:GP:UINT64
ld1r {v1.8h}, [x10]
### op load [] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
ld1 {v1.h}[0], [x10]
### op load [] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
ld1 {v1.h}[7], [x10]
### op load [] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64
ld1 {v1.4s}, [x10]
### op load [] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64
ld1r {v1.4s}, [x10]
### op load [] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
ld1 {v1.s}[0], [x10]
### op load [] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
ld1 {v1.s}[3], [x10]
### op load [] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64
ld1 {v1.2d}, [x10]
### op load [] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64
ld1r {v1.2d}, [x10]
### op load [] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
ld1 {v1.d}[0], [x10]
### op load [] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
ld1 {v1.d}[1], [x10]
### op load [] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64
ld1 {v1.16b}, [x10]
### op load [] adreg:REGISTER:VEC:SINT8{BCAST} agreg:REGISTER:GP:UINT64
ld1r {v1.16b}, [x10]
### op load [] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
ld1 {v1.b}[0], [x10]
### op load [] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
ld1 {v1.b}[15], [x10]
### op load [] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64
ld1 {v1.8h}, [x10]
### op load [] adreg:REGISTER:VEC:UINT16{BCAST} agreg:REGISTER:GP:UINT64
ld1r {v1.8h}, [x10]
### op load [] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
ld1 {v1.h}[0], [x10]
### op load [] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
ld1 {v1.h}[7], [x10]
### op load [] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64
ld1 {v1.4s}, [x10]
### op load [] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64
ld1r {v1.4s}, [x10]
### op load [] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
ld1 {v1.s}[0], [x10]
### op load [] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
ld1 {v1.s}[3], [x10]
### op load [] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64
ld1 {v1.2d}, [x10]
### op load [] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64
ld1r {v1.2d}, [x10]
### op load [] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
ld1 {v1.d}[0], [x10]
### op load [] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
ld1 {v1.d}[1], [x10]
### op load [] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64
ld1 {v1.16b}, [x10]
### op load [] adreg:REGISTER:VEC:UINT8{BCAST} agreg:REGISTER:GP:UINT64
ld1r {v1.16b}, [x10]
### op load [] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
ld1 {v1.b}[0], [x10]
### op load [] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
ld1 {v1.b}[15], [x10]
### op move [BITS] adreg:REGISTER:GP:UINT16 bdreg:REGISTER:FP:HALF
fmov h1,w10
### op move [BITS] adreg:REGISTER:GP:UINT32 bdreg:REGISTER:FP:SINGLE
fmov s1,w10
### op move [BITS] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:FP:DOUBLE
fmov d1,x10
### op move [PERMUTE] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE {bits:64,pattern:trn_even,segment:None}
trn1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE {bits:64,pattern:trn_odd,segment:None}
trn2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE {bits:64,pattern:uzp_even,segment:None}
uzp1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE {bits:64,pattern:uzp_odd,segment:None}
uzp2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE {bits:64,pattern:zip_hi,segment:None}
zip2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE {bits:64,pattern:zip_lo,segment:None}
zip1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF {bits:16,pattern:trn_even,segment:None}
trn1 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF {bits:16,pattern:trn_odd,segment:None}
trn2 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF {bits:16,pattern:uzp_even,segment:None}
uzp1 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF {bits:16,pattern:uzp_odd,segment:None}
uzp2 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF {bits:16,pattern:zip_hi,segment:None}
zip2 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF {bits:16,pattern:zip_lo,segment:None}
zip1 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF {bits:32,pattern:trn_even,segment:None}
trn1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF {bits:32,pattern:trn_odd,segment:None}
trn2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF {bits:32,pattern:uzp_even,segment:None}
uzp1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF {bits:32,pattern:uzp_odd,segment:None}
uzp2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF {bits:32,pattern:zip_hi,segment:None}
zip2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF {bits:32,pattern:zip_lo,segment:None}
zip1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF {bits:64,pattern:trn_even,segment:None}
trn1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF {bits:64,pattern:trn_odd,segment:None}
trn2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF {bits:64,pattern:uzp_even,segment:None}
uzp1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF {bits:64,pattern:uzp_odd,segment:None}
uzp2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF {bits:64,pattern:zip_hi,segment:None}
zip2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF {bits:64,pattern:zip_lo,segment:None}
zip1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {bits:32,pattern:trn_even,segment:None}
trn1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {bits:32,pattern:trn_odd,segment:None}
trn2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {bits:32,pattern:uzp_even,segment:None}
uzp1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {bits:32,pattern:uzp_odd,segment:None}
uzp2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {bits:32,pattern:zip_hi,segment:None}
zip2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {bits:32,pattern:zip_lo,segment:None}
zip1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {bits:64,pattern:trn_even,segment:None}
trn1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {bits:64,pattern:trn_odd,segment:None}
trn2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {bits:64,pattern:uzp_even,segment:None}
uzp1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {bits:64,pattern:uzp_odd,segment:None}
uzp2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {bits:64,pattern:zip_hi,segment:None}
zip2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {bits:64,pattern:zip_lo,segment:None}
zip1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 {bits:16,pattern:trn_even,segment:None}
trn1 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 {bits:16,pattern:trn_odd,segment:None}
trn2 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 {bits:16,pattern:uzp_even,segment:None}
uzp1 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 {bits:16,pattern:uzp_odd,segment:None}
uzp2 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 {bits:16,pattern:zip_hi,segment:None}
zip2 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 {bits:16,pattern:zip_lo,segment:None}
zip1 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 {bits:32,pattern:trn_even,segment:None}
trn1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 {bits:32,pattern:trn_odd,segment:None}
trn2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 {bits:32,pattern:uzp_even,segment:None}
uzp1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 {bits:32,pattern:uzp_odd,segment:None}
uzp2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 {bits:32,pattern:zip_hi,segment:None}
zip2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 {bits:32,pattern:zip_lo,segment:None}
zip1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 {bits:64,pattern:trn_even,segment:None}
trn1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 {bits:64,pattern:trn_odd,segment:None}
trn2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 {bits:64,pattern:uzp_even,segment:None}
uzp1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 {bits:64,pattern:uzp_odd,segment:None}
uzp2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 {bits:64,pattern:zip_hi,segment:None}
zip2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 {bits:64,pattern:zip_lo,segment:None}
zip1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {bits:32,pattern:trn_even,segment:None}
trn1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {bits:32,pattern:trn_odd,segment:None}
trn2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {bits:32,pattern:uzp_even,segment:None}
uzp1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {bits:32,pattern:uzp_odd,segment:None}
uzp2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {bits:32,pattern:zip_hi,segment:None}
zip2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {bits:32,pattern:zip_lo,segment:None}
zip1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {bits:64,pattern:trn_even,segment:None}
trn1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {bits:64,pattern:trn_odd,segment:None}
trn2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {bits:64,pattern:uzp_even,segment:None}
uzp1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {bits:64,pattern:uzp_odd,segment:None}
uzp2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {bits:64,pattern:zip_hi,segment:None}
zip2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {bits:64,pattern:zip_lo,segment:None}
zip1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 {bits:64,pattern:trn_even,segment:None}
trn1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 {bits:64,pattern:trn_odd,segment:None}
trn2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 {bits:64,pattern:uzp_even,segment:None}
uzp1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 {bits:64,pattern:uzp_odd,segment:None}
uzp2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 {bits:64,pattern:zip_hi,segment:None}
zip2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 {bits:64,pattern:zip_lo,segment:None}
zip1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:16,pattern:trn_even,segment:None}
trn1 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:16,pattern:trn_odd,segment:None}
trn2 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:16,pattern:uzp_even,segment:None}
uzp1 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:16,pattern:uzp_odd,segment:None}
uzp2 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:16,pattern:zip_hi,segment:None}
zip2 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:16,pattern:zip_lo,segment:None}
zip1 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:32,pattern:trn_even,segment:None}
trn1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:32,pattern:trn_odd,segment:None}
trn2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:32,pattern:uzp_even,segment:None}
uzp1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:32,pattern:uzp_odd,segment:None}
uzp2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:32,pattern:zip_hi,segment:None}
zip2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:32,pattern:zip_lo,segment:None}
zip1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:64,pattern:trn_even,segment:None}
trn1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:64,pattern:trn_odd,segment:None}
trn2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:64,pattern:uzp_even,segment:None}
uzp1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:64,pattern:uzp_odd,segment:None}
uzp2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:64,pattern:zip_hi,segment:None}
zip2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:64,pattern:zip_lo,segment:None}
zip1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:8,pattern:trn_even,segment:None}
trn1 v3.16b,v1.16b,v2.16b
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:8,pattern:trn_odd,segment:None}
trn2 v3.16b,v1.16b,v2.16b
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:8,pattern:uzp_even,segment:None}
uzp1 v3.16b,v1.16b,v2.16b
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:8,pattern:uzp_odd,segment:None}
uzp2 v3.16b,v1.16b,v2.16b
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:8,pattern:zip_hi,segment:None}
zip2 v3.16b,v1.16b,v2.16b
### op move [PERMUTE] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {bits:8,pattern:zip_lo,segment:None}
zip1 v3.16b,v1.16b,v2.16b
### op move [PERMUTE] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 {bits:16,pattern:trn_even,segment:None}
trn1 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 {bits:16,pattern:trn_odd,segment:None}
trn2 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 {bits:16,pattern:uzp_even,segment:None}
uzp1 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 {bits:16,pattern:uzp_odd,segment:None}
uzp2 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 {bits:16,pattern:zip_hi,segment:None}
zip2 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 {bits:16,pattern:zip_lo,segment:None}
zip1 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 {bits:32,pattern:trn_even,segment:None}
trn1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 {bits:32,pattern:trn_odd,segment:None}
trn2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 {bits:32,pattern:uzp_even,segment:None}
uzp1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 {bits:32,pattern:uzp_odd,segment:None}
uzp2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 {bits:32,pattern:zip_hi,segment:None}
zip2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 {bits:32,pattern:zip_lo,segment:None}
zip1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 {bits:64,pattern:trn_even,segment:None}
trn1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 {bits:64,pattern:trn_odd,segment:None}
trn2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 {bits:64,pattern:uzp_even,segment:None}
uzp1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 {bits:64,pattern:uzp_odd,segment:None}
uzp2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 {bits:64,pattern:zip_hi,segment:None}
zip2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 {bits:64,pattern:zip_lo,segment:None}
zip1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {bits:32,pattern:trn_even,segment:None}
trn1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {bits:32,pattern:trn_odd,segment:None}
trn2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {bits:32,pattern:uzp_even,segment:None}
uzp1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {bits:32,pattern:uzp_odd,segment:None}
uzp2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {bits:32,pattern:zip_hi,segment:None}
zip2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {bits:32,pattern:zip_lo,segment:None}
zip1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {bits:64,pattern:trn_even,segment:None}
trn1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {bits:64,pattern:trn_odd,segment:None}
trn2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {bits:64,pattern:uzp_even,segment:None}
uzp1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {bits:64,pattern:uzp_odd,segment:None}
uzp2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {bits:64,pattern:zip_hi,segment:None}
zip2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {bits:64,pattern:zip_lo,segment:None}
zip1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 {bits:64,pattern:trn_even,segment:None}
trn1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 {bits:64,pattern:trn_odd,segment:None}
trn2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 {bits:64,pattern:uzp_even,segment:None}
uzp1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 {bits:64,pattern:uzp_odd,segment:None}
uzp2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 {bits:64,pattern:zip_hi,segment:None}
zip2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 {bits:64,pattern:zip_lo,segment:None}
zip1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:16,pattern:trn_even,segment:None}
trn1 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:16,pattern:trn_odd,segment:None}
trn2 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:16,pattern:uzp_even,segment:None}
uzp1 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:16,pattern:uzp_odd,segment:None}
uzp2 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:16,pattern:zip_hi,segment:None}
zip2 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:16,pattern:zip_lo,segment:None}
zip1 v3.8h,v1.8h,v2.8h
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:32,pattern:trn_even,segment:None}
trn1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:32,pattern:trn_odd,segment:None}
trn2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:32,pattern:uzp_even,segment:None}
uzp1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:32,pattern:uzp_odd,segment:None}
uzp2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:32,pattern:zip_hi,segment:None}
zip2 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:32,pattern:zip_lo,segment:None}
zip1 v3.4s,v1.4s,v2.4s
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:64,pattern:trn_even,segment:None}
trn1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:64,pattern:trn_odd,segment:None}
trn2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:64,pattern:uzp_even,segment:None}
uzp1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:64,pattern:uzp_odd,segment:None}
uzp2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:64,pattern:zip_hi,segment:None}
zip2 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:64,pattern:zip_lo,segment:None}
zip1 v3.2d,v1.2d,v2.2d
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:8,pattern:trn_even,segment:None}
trn1 v3.16b,v1.16b,v2.16b
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:8,pattern:trn_odd,segment:None}
trn2 v3.16b,v1.16b,v2.16b
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:8,pattern:uzp_even,segment:None}
uzp1 v3.16b,v1.16b,v2.16b
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:8,pattern:uzp_odd,segment:None}
uzp2 v3.16b,v1.16b,v2.16b
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:8,pattern:zip_hi,segment:None}
zip2 v3.16b,v1.16b,v2.16b
### op move [PERMUTE] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {bits:8,pattern:zip_lo,segment:None}
zip1 v3.16b,v1.16b,v2.16b
### op move [] adreg:REGISTER:FP:DOUBLE bdreg:REGISTER:FP:DOUBLE
fmov d2,d1
### op move [] adreg:REGISTER:FP:DOUBLE bdreg:REGISTER:VEC:DOUBLE{BCAST}
dup v1.2d,v1.d[0]
### op move [] adreg:REGISTER:FP:DOUBLE bdreg:REGISTER:VEC:DOUBLE{ILANE} bdreg_lane:IMMEDIATE:-:-
ins v1.d[0],v1.d[0]
### op move [] adreg:REGISTER:FP:DOUBLE bdreg:REGISTER:VEC:DOUBLE{ILANE} bdreg_lane:IMMEDIATE:-:- @far
ins v1.d[1],v1.d[0]
### op move [] adreg:REGISTER:FP:HALF bdreg:REGISTER:FP:HALF
fmov h2,h1
### op move [] adreg:REGISTER:FP:HALF bdreg:REGISTER:VEC:HALF{BCAST}
dup v1.8h,v1.h[0]
### op move [] adreg:REGISTER:FP:HALF bdreg:REGISTER:VEC:HALF{ILANE} bdreg_lane:IMMEDIATE:-:-
ins v1.h[0],v1.h[0]
### op move [] adreg:REGISTER:FP:HALF bdreg:REGISTER:VEC:HALF{ILANE} bdreg_lane:IMMEDIATE:-:- @far
ins v1.h[7],v1.h[0]
### op move [] adreg:REGISTER:FP:SINGLE bdreg:REGISTER:FP:SINGLE
fmov s2,s1
### op move [] adreg:REGISTER:FP:SINGLE bdreg:REGISTER:VEC:SINGLE{BCAST}
dup v1.4s,v1.s[0]
### op move [] adreg:REGISTER:FP:SINGLE bdreg:REGISTER:VEC:SINGLE{ILANE} bdreg_lane:IMMEDIATE:-:-
ins v1.s[0],v1.s[0]
### op move [] adreg:REGISTER:FP:SINGLE bdreg:REGISTER:VEC:SINGLE{ILANE} bdreg_lane:IMMEDIATE:-:- @far
ins v1.s[3],v1.s[0]
### op move [] adreg:REGISTER:GP:SINT16 bdreg:REGISTER:VEC:SINT16{BCAST}
dup v1.8h,w10
### op move [] adreg:REGISTER:GP:SINT16 bdreg:REGISTER:VEC:SINT16{ILANE} bdreg_lane:IMMEDIATE:-:-
ins v1.h[0],w10
### op move [] adreg:REGISTER:GP:SINT16 bdreg:REGISTER:VEC:SINT16{ILANE} bdreg_lane:IMMEDIATE:-:- @far
ins v1.h[7],w10
### op move [] adreg:REGISTER:GP:SINT32 bdreg:REGISTER:VEC:SINT32{BCAST}
dup v1.4s,w10
### op move [] adreg:REGISTER:GP:SINT32 bdreg:REGISTER:VEC:SINT32{ILANE} bdreg_lane:IMMEDIATE:-:-
ins v1.s[0],w10
### op move [] adreg:REGISTER:GP:SINT32 bdreg:REGISTER:VEC:SINT32{ILANE} bdreg_lane:IMMEDIATE:-:- @far
ins v1.s[3],w10
### op move [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64
mov x11,x10
### op move [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:VEC:SINT64{BCAST}
dup v1.2d,x10
### op move [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:VEC:SINT64{ILANE} bdreg_lane:IMMEDIATE:-:-
ins v1.d[0],x10
### op move [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:VEC:SINT64{ILANE} bdreg_lane:IMMEDIATE:-:- @far
ins v1.d[1],x10
### op move [] adreg:REGISTER:GP:SINT8 bdreg:REGISTER:VEC:SINT8{BCAST}
dup v1.16b,w10
### op move [] adreg:REGISTER:GP:SINT8 bdreg:REGISTER:VEC:SINT8{ILANE} bdreg_lane:IMMEDIATE:-:-
ins v1.b[0],w10
### op move [] adreg:REGISTER:GP:SINT8 bdreg:REGISTER:VEC:SINT8{ILANE} bdreg_lane:IMMEDIATE:-:- @far
ins v1.b[15],w10
### op move [] adreg:REGISTER:GP:UINT16 bdreg:REGISTER:VEC:UINT16{BCAST}
dup v1.8h,w10
### op move [] adreg:REGISTER:GP:UINT16 bdreg:REGISTER:VEC:UINT16{ILANE} bdreg_lane:IMMEDIATE:-:-
ins v1.h[0],w10
### op move [] adreg:REGISTER:GP:UINT16 bdreg:REGISTER:VEC:UINT16{ILANE} bdreg_lane:IMMEDIATE:-:- @far
ins v1.h[7],w10
### op move [] adreg:REGISTER:GP:UINT32 bdreg:REGISTER:VEC:UINT32{BCAST}
dup v1.4s,w10
### op move [] adreg:REGISTER:GP:UINT32 bdreg:REGISTER:VEC:UINT32{ILANE} bdreg_lane:IMMEDIATE:-:-
ins v1.s[0],w10
### op move [] adreg:REGISTER:GP:UINT32 bdreg:REGISTER:VEC:UINT32{ILANE} bdreg_lane:IMMEDIATE:-:- @far
ins v1.s[3],w10
### op move [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64
mov x11,x10
### op move [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{BCAST}
dup v1.2d,x10
### op move [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} bdreg_lane:IMMEDIATE:-:-
ins v1.d[0],x10
### op move [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} bdreg_lane:IMMEDIATE:-:- @far
ins v1.d[1],x10
### op move [] adreg:REGISTER:GP:UINT8 bdreg:REGISTER:VEC:UINT8{BCAST}
dup v1.16b,w10
### op move [] adreg:REGISTER:GP:UINT8 bdreg:REGISTER:VEC:UINT8{ILANE} bdreg_lane:IMMEDIATE:-:-
ins v1.b[0],w10
### op move [] adreg:REGISTER:GP:UINT8 bdreg:REGISTER:VEC:UINT8{ILANE} bdreg_lane:IMMEDIATE:-:- @far
ins v1.b[15],w10
### op move [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE
mov v2.16b,v1.16b
### op move [] adreg:REGISTER:VEC:DOUBLE{ILANEROT} bdreg:REGISTER:VEC:DOUBLE adreg_irot:IMMEDIATE:-:-
ext v2.16b,v1.16b,v1.16b,#8
### op move [] adreg:REGISTER:VEC:DOUBLE{ILANEROT} bdreg:REGISTER:VEC:DOUBLE adreg_irot:IMMEDIATE:-:- @far
ext v2.16b,v1.16b,v1.16b,#8
### op move [] adreg:REGISTER:VEC:DOUBLE{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:DOUBLE adreg_irot:IMMEDIATE:-:-
ext v2.16b,v1.16b,v1.16b,#8
### op move [] adreg:REGISTER:VEC:DOUBLE{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:DOUBLE adreg_irot:IMMEDIATE:-:- @far
ext v2.16b,v1.16b,v1.16b,#8
### op move [] adreg:REGISTER:VEC:DOUBLE{ILANE} bdreg:REGISTER:VEC:DOUBLE{BCAST} adreg_lane:IMMEDIATE:-:-
dup v2.2d,v1.d[0]
### op move [] adreg:REGISTER:VEC:DOUBLE{ILANE} bdreg:REGISTER:VEC:DOUBLE{BCAST} adreg_lane:IMMEDIATE:-:- @far
dup v2.2d,v1.d[1]
### op move [] adreg:REGISTER:VEC:DOUBLE{ILANE} bdreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:-
ins v2.d[0],v1.d[0]
### op move [] adreg:REGISTER:VEC:DOUBLE{ILANE} bdreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- @far
ins v2.d[1],v1.d[1]
### op move [] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF
mov v2.16b,v1.16b
### op move [] adreg:REGISTER:VEC:HALF{ILANEROT} bdreg:REGISTER:VEC:HALF adreg_irot:IMMEDIATE:-:-
ext v2.16b,v1.16b,v1.16b,#14
### op move [] adreg:REGISTER:VEC:HALF{ILANEROT} bdreg:REGISTER:VEC:HALF adreg_irot:IMMEDIATE:-:- @far
ext v2.16b,v1.16b,v1.16b,#2
### op move [] adreg:REGISTER:VEC:HALF{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:HALF adreg_irot:IMMEDIATE:-:-
ext v2.16b,v1.16b,v1.16b,#14
### op move [] adreg:REGISTER:VEC:HALF{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:HALF adreg_irot:IMMEDIATE:-:- @far
ext v2.16b,v1.16b,v1.16b,#2
### op move [] adreg:REGISTER:VEC:HALF{ILANE} bdreg:REGISTER:VEC:HALF{BCAST} adreg_lane:IMMEDIATE:-:-
dup v2.8h,v1.h[0]
### op move [] adreg:REGISTER:VEC:HALF{ILANE} bdreg:REGISTER:VEC:HALF{BCAST} adreg_lane:IMMEDIATE:-:- @far
dup v2.8h,v1.h[7]
### op move [] adreg:REGISTER:VEC:HALF{ILANE} bdreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:-
ins v2.h[0],v1.h[0]
### op move [] adreg:REGISTER:VEC:HALF{ILANE} bdreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- @far
ins v2.h[7],v1.h[7]
### op move [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE
mov v2.16b,v1.16b
### op move [] adreg:REGISTER:VEC:SINGLE{ILANEROT} bdreg:REGISTER:VEC:SINGLE adreg_irot:IMMEDIATE:-:-
ext v2.16b,v1.16b,v1.16b,#12
### op move [] adreg:REGISTER:VEC:SINGLE{ILANEROT} bdreg:REGISTER:VEC:SINGLE adreg_irot:IMMEDIATE:-:- @far
ext v2.16b,v1.16b,v1.16b,#4
### op move [] adreg:REGISTER:VEC:SINGLE{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINGLE adreg_irot:IMMEDIATE:-:-
ext v2.16b,v1.16b,v1.16b,#12
### op move [] adreg:REGISTER:VEC:SINGLE{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINGLE adreg_irot:IMMEDIATE:-:- @far
ext v2.16b,v1.16b,v1.16b,#4
### op move [] adreg:REGISTER:VEC:SINGLE{ILANE} bdreg:REGISTER:VEC:SINGLE{BCAST} adreg_lane:IMMEDIATE:-:-
dup v2.4s,v1.s[0]
### op move [] adreg:REGISTER:VEC:SINGLE{ILANE} bdreg:REGISTER:VEC:SINGLE{BCAST} adreg_lane:IMMEDIATE:-:- @far
dup v2.4s,v1.s[3]
### op move [] adreg:REGISTER:VEC:SINGLE{ILANE} bdreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:-
ins v2.s[0],v1.s[0]
### op move [] adreg:REGISTER:VEC:SINGLE{ILANE} bdreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- @far
ins v2.s[3],v1.s[3]
### op move [] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16
mov v2.16b,v1.16b
### op move [] adreg:REGISTER:VEC:SINT16{ILANEROT} bdreg:REGISTER:VEC:SINT16 adreg_irot:IMMEDIATE:-:-
ext v2.16b,v1.16b,v1.16b,#14
### op move [] adreg:REGISTER:VEC:SINT16{ILANEROT} bdreg:REGISTER:VEC:SINT16 adreg_irot:IMMEDIATE:-:- @far
ext v2.16b,v1.16b,v1.16b,#2
### op move [] adreg:REGISTER:VEC:SINT16{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINT16 adreg_irot:IMMEDIATE:-:-
ext v2.16b,v1.16b,v1.16b,#14
### op move [] adreg:REGISTER:VEC:SINT16{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINT16 adreg_irot:IMMEDIATE:-:- @far
ext v2.16b,v1.16b,v1.16b,#2
### op move [] adreg:REGISTER:VEC:SINT16{ILANE} bdreg:REGISTER:VEC:SINT16{BCAST} adreg_lane:IMMEDIATE:-:-
dup v2.8h,v1.h[0]
### op move [] adreg:REGISTER:VEC:SINT16{ILANE} bdreg:REGISTER:VEC:SINT16{BCAST} adreg_lane:IMMEDIATE:-:- @far
dup v2.8h,v1.h[7]
### op move [] adreg:REGISTER:VEC:SINT16{ILANE} bdreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:-
ins v2.h[0],v1.h[0]
### op move [] adreg:REGISTER:VEC:SINT16{ILANE} bdreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- @far
ins v2.h[7],v1.h[7]
### op move [] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32
mov v2.16b,v1.16b
### op move [] adreg:REGISTER:VEC:SINT32{ILANEROT} bdreg:REGISTER:VEC:SINT32 adreg_irot:IMMEDIATE:-:-
ext v2.16b,v1.16b,v1.16b,#12
### op move [] adreg:REGISTER:VEC:SINT32{ILANEROT} bdreg:REGISTER:VEC:SINT32 adreg_irot:IMMEDIATE:-:- @far
ext v2.16b,v1.16b,v1.16b,#4
### op move [] adreg:REGISTER:VEC:SINT32{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINT32 adreg_irot:IMMEDIATE:-:-
ext v2.16b,v1.16b,v1.16b,#12
### op move [] adreg:REGISTER:VEC:SINT32{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINT32 adreg_irot:IMMEDIATE:-:- @far
ext v2.16b,v1.16b,v1.16b,#4
### op move [] adreg:REGISTER:VEC:SINT32{ILANE} bdreg:REGISTER:VEC:SINT32{BCAST} adreg_lane:IMMEDIATE:-:-
dup v2.4s,v1.s[0]
### op move [] adreg:REGISTER:VEC:SINT32{ILANE} bdreg:REGISTER:VEC:SINT32{BCAST} adreg_lane:IMMEDIATE:-:- @far
dup v2.4s,v1.s[3]
### op move [] adreg:REGISTER:VEC:SINT32{ILANE} bdreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:-
ins v2.s[0],v1.s[0]
### op move [] adreg:REGISTER:VEC:SINT32{ILANE} bdreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- @far
ins v2.s[3],v1.s[3]
### op move [] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64
mov v2.16b,v1.16b
### op move [] adreg:REGISTER:VEC:SINT64{ILANEROT} bdreg:REGISTER:VEC:SINT64 adreg_irot:IMMEDIATE:-:-
ext v2.16b,v1.16b,v1.16b,#8
### op move [] adreg:REGISTER:VEC:SINT64{ILANEROT} bdreg:REGISTER:VEC:SINT64 adreg_irot:IMMEDIATE:-:- @far
ext v2.16b,v1.16b,v1.16b,#8
### op move [] adreg:REGISTER:VEC:SINT64{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINT64 adreg_irot:IMMEDIATE:-:-
ext v2.16b,v1.16b,v1.16b,#8
### op move [] adreg:REGISTER:VEC:SINT64{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINT64 adreg_irot:IMMEDIATE:-:- @far
ext v2.16b,v1.16b,v1.16b,#8
### op move [] adreg:REGISTER:VEC:SINT64{ILANE} bdreg:REGISTER:VEC:SINT64{BCAST} adreg_lane:IMMEDIATE:-:-
dup v2.2d,v1.d[0]
### op move [] adreg:REGISTER:VEC:SINT64{ILANE} bdreg:REGISTER:VEC:SINT64{BCAST} adreg_lane:IMMEDIATE:-:- @far
dup v2.2d,v1.d[1]
### op move [] adreg:REGISTER:VEC:SINT64{ILANE} bdreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:-
ins v2.d[0],v1.d[0]
### op move [] adreg:REGISTER:VEC:SINT64{ILANE} bdreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- @far
ins v2.d[1],v1.d[1]
### op move [] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8
mov v2.16b,v1.16b
### op move [] adreg:REGISTER:VEC:SINT8{ILANEROT} bdreg:REGISTER:VEC:SINT8 adreg_irot:IMMEDIATE:-:-
ext v2.16b,v1.16b,v1.16b,#15
### op move [] adreg:REGISTER:VEC:SINT8{ILANEROT} bdreg:REGISTER:VEC:SINT8 adreg_irot:IMMEDIATE:-:- @far
ext v2.16b,v1.16b,v1.16b,#1
### op move [] adreg:REGISTER:VEC:SINT8{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINT8 adreg_irot:IMMEDIATE:-:-
ext v2.16b,v1.16b,v1.16b,#15
### op move [] adreg:REGISTER:VEC:SINT8{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINT8 adreg_irot:IMMEDIATE:-:- @far
ext v2.16b,v1.16b,v1.16b,#1
### op move [] adreg:REGISTER:VEC:SINT8{ILANE} bdreg:REGISTER:VEC:SINT8{BCAST} adreg_lane:IMMEDIATE:-:-
dup v2.16b,v1.b[0]
### op move [] adreg:REGISTER:VEC:SINT8{ILANE} bdreg:REGISTER:VEC:SINT8{BCAST} adreg_lane:IMMEDIATE:-:- @far
dup v2.16b,v1.b[15]
### op move [] adreg:REGISTER:VEC:SINT8{ILANE} bdreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:-
ins v2.b[0],v1.b[0]
### op move [] adreg:REGISTER:VEC:SINT8{ILANE} bdreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- @far
ins v2.b[15],v1.b[15]
### op move [] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16
mov v2.16b,v1.16b
### op move [] adreg:REGISTER:VEC:UINT16{ILANEROT} bdreg:REGISTER:VEC:UINT16 adreg_irot:IMMEDIATE:-:-
ext v2.16b,v1.16b,v1.16b,#14
### op move [] adreg:REGISTER:VEC:UINT16{ILANEROT} bdreg:REGISTER:VEC:UINT16 adreg_irot:IMMEDIATE:-:- @far
ext v2.16b,v1.16b,v1.16b,#2
### op move [] adreg:REGISTER:VEC:UINT16{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:UINT16 adreg_irot:IMMEDIATE:-:-
ext v2.16b,v1.16b,v1.16b,#14
### op move [] adreg:REGISTER:VEC:UINT16{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:UINT16 adreg_irot:IMMEDIATE:-:- @far
ext v2.16b,v1.16b,v1.16b,#2
### op move [] adreg:REGISTER:VEC:UINT16{ILANE} bdreg:REGISTER:VEC:UINT16{BCAST} adreg_lane:IMMEDIATE:-:-
dup v2.8h,v1.h[0]
### op move [] adreg:REGISTER:VEC:UINT16{ILANE} bdreg:REGISTER:VEC:UINT16{BCAST} adreg_lane:IMMEDIATE:-:- @far
dup v2.8h,v1.h[7]
### op move [] adreg:REGISTER:VEC:UINT16{ILANE} bdreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:-
ins v2.h[0],v1.h[0]
### op move [] adreg:REGISTER:VEC:UINT16{ILANE} bdreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- @far
ins v2.h[7],v1.h[7]
### op move [] adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32
mov v2.16b,v1.16b
### op move [] adreg:REGISTER:VEC:UINT32{ILANEROT} bdreg:REGISTER:VEC:UINT32 adreg_irot:IMMEDIATE:-:-
ext v2.16b,v1.16b,v1.16b,#12
### op move [] adreg:REGISTER:VEC:UINT32{ILANEROT} bdreg:REGISTER:VEC:UINT32 adreg_irot:IMMEDIATE:-:- @far
ext v2.16b,v1.16b,v1.16b,#4
### op move [] adreg:REGISTER:VEC:UINT32{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:UINT32 adreg_irot:IMMEDIATE:-:-
ext v2.16b,v1.16b,v1.16b,#12
### op move [] adreg:REGISTER:VEC:UINT32{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:UINT32 adreg_irot:IMMEDIATE:-:- @far
ext v2.16b,v1.16b,v1.16b,#4
### op move [] adreg:REGISTER:VEC:UINT32{ILANE} bdreg:REGISTER:VEC:UINT32{BCAST} adreg_lane:IMMEDIATE:-:-
dup v2.4s,v1.s[0]
### op move [] adreg:REGISTER:VEC:UINT32{ILANE} bdreg:REGISTER:VEC:UINT32{BCAST} adreg_lane:IMMEDIATE:-:- @far
dup v2.4s,v1.s[3]
### op move [] adreg:REGISTER:VEC:UINT32{ILANE} bdreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:-
ins v2.s[0],v1.s[0]
### op move [] adreg:REGISTER:VEC:UINT32{ILANE} bdreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- @far
ins v2.s[3],v1.s[3]
### op move [] adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64
mov v2.16b,v1.16b
### op move [] adreg:REGISTER:VEC:UINT64{ILANEROT} bdreg:REGISTER:VEC:UINT64 adreg_irot:IMMEDIATE:-:-
ext v2.16b,v1.16b,v1.16b,#8
### op move [] adreg:REGISTER:VEC:UINT64{ILANEROT} bdreg:REGISTER:VEC:UINT64 adreg_irot:IMMEDIATE:-:- @far
ext v2.16b,v1.16b,v1.16b,#8
### op move [] adreg:REGISTER:VEC:UINT64{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:UINT64 adreg_irot:IMMEDIATE:-:-
ext v2.16b,v1.16b,v1.16b,#8
### op move [] adreg:REGISTER:VEC:UINT64{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:UINT64 adreg_irot:IMMEDIATE:-:- @far
ext v2.16b,v1.16b,v1.16b,#8
### op move [] adreg:REGISTER:VEC:UINT64{ILANE} bdreg:REGISTER:VEC:UINT64{BCAST} adreg_lane:IMMEDIATE:-:-
dup v2.2d,v1.d[0]
### op move [] adreg:REGISTER:VEC:UINT64{ILANE} bdreg:REGISTER:VEC:UINT64{BCAST} adreg_lane:IMMEDIATE:-:- @far
dup v2.2d,v1.d[1]
### op move [] adreg:REGISTER:VEC:UINT64{ILANE} bdreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:-
ins v2.d[0],v1.d[0]
### op move [] adreg:REGISTER:VEC:UINT64{ILANE} bdreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- @far
ins v2.d[1],v1.d[1]
### op move [] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8
mov v2.16b,v1.16b
### op move [] adreg:REGISTER:VEC:UINT8{ILANEROT} bdreg:REGISTER:VEC:UINT8 adreg_irot:IMMEDIATE:-:-
ext v2.16b,v1.16b,v1.16b,#15
### op move [] adreg:REGISTER:VEC:UINT8{ILANEROT} bdreg:REGISTER:VEC:UINT8 adreg_irot:IMMEDIATE:-:- @far
ext v2.16b,v1.16b,v1.16b,#1
### op move [] adreg:REGISTER:VEC:UINT8{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:UINT8 adreg_irot:IMMEDIATE:-:-
ext v2.16b,v1.16b,v1.16b,#15
### op move [] adreg:REGISTER:VEC:UINT8{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:UINT8 adreg_irot:IMMEDIATE:-:- @far
ext v2.16b,v1.16b,v1.16b,#1
### op move [] adreg:REGISTER:VEC:UINT8{ILANE} bdreg:REGISTER:VEC:UINT8{BCAST} adreg_lane:IMMEDIATE:-:-
dup v2.16b,v1.b[0]
### op move [] adreg:REGISTER:VEC:UINT8{ILANE} bdreg:REGISTER:VEC:UINT8{BCAST} adreg_lane:IMMEDIATE:-:- @far
dup v2.16b,v1.b[15]
### op move [] adreg:REGISTER:VEC:UINT8{ILANE} bdreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:-
ins v2.b[0],v1.b[0]
### op move [] adreg:REGISTER:VEC:UINT8{ILANE} bdreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- @far
ins v2.b[15],v1.b[15]
### op mul [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64
mul x12,x10,x11
### op mul [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64
mul x12,x10,x11
### op mul [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE
fmul v3.2d,v1.2d,v2.2d
### op mul [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE bdreg_lane:IMMEDIATE:-:-
fmul v3.2d,v1.2d,v2.d[0]
### op mul [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE bdreg_lane:IMMEDIATE:-:- @far
fmul v3.2d,v1.2d,v2.d[1]
### op mul [] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF
fmul v3.8h,v1.8h,v2.8h
### op mul [] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:-
fmul v3.8h,v1.8h,v2.h[0]
### op mul [] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- @far
fmul v3.8h,v1.8h,v2.h[7]
### op mul [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE
fmul v3.4s,v1.4s,v2.4s
### op mul [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:-
fmul v3.4s,v1.4s,v2.s[0]
### op mul [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- @far
fmul v3.4s,v1.4s,v2.s[3]
### op mul [] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16
mul v3.8h,v1.8h,v2.8h
### op mul [] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:-
mul v3.8h,v1.8h,v2.h[0]
### op mul [] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- @far
mul v3.8h,v1.8h,v2.h[7]
### op mul [] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32
mul v3.4s,v1.4s,v2.4s
### op mul [] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:-
mul v3.4s,v1.4s,v2.s[0]
### op mul [] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- @far
mul v3.4s,v1.4s,v2.s[3]
### op mul [] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64
mul v3.2d,v1.2d,v2.2d
### op mul [] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64 bdreg_lane:IMMEDIATE:-:-
mul v3.2d,v1.2d,v2.d[0]
### op mul [] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64 bdreg_lane:IMMEDIATE:-:- @far
mul v3.2d,v1.2d,v2.d[1]
### op mul [] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8
mul v3.16b,v1.16b,v2.16b
### op mul [] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:-
mul v3.16b,v1.16b,v2.b[0]
### op mul [] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:- @far
mul v3.16b,v1.16b,v2.b[15]
### op prefetch [GOFFSET] agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
prfm PLDL1KEEP, [x10, x11]
### op prefetch [IOFFSET] agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
prfm PLDL1KEEP, [x10]
### op prefetch [] agreg:REGISTER:GP:UINT64
prfm PLDL1KEEP, [x10]
### op set [CONST] dreg:REGISTER:FP:DOUBLE {constant:one}
fmov d1,#1.0
### op set [CONST] dreg:REGISTER:FP:DOUBLE {constant:zero}
fmov d1,xzr
### op set [CONST] dreg:REGISTER:FP:HALF {constant:one}
fmov h1,#1.0
### op set [CONST] dreg:REGISTER:FP:HALF {constant:zero}
fmov h1,wzr
### op set [CONST] dreg:REGISTER:FP:SINGLE {constant:one}
fmov s1,#1.0
### op set [CONST] dreg:REGISTER:FP:SINGLE {constant:zero}
fmov s1,wzr
### op set [CONST] dreg:REGISTER:GP:SINT64 value:IMMEDIATE:-:-
mov x10,#-9223372036854775808
### op set [CONST] dreg:REGISTER:GP:SINT64 value:IMMEDIATE:-:- @far
mov x10,#18446744073709551615
### op set [CONST] dreg:REGISTER:GP:SINT64 {constant:one}
mov x10,#1
### op set [CONST] dreg:REGISTER:GP:SINT64 {constant:zero}
mov x10,#0
### op set [CONST] dreg:REGISTER:GP:UINT64 value:IMMEDIATE:-:-
mov x10,#-9223372036854775808
### op set [CONST] dreg:REGISTER:GP:UINT64 value:IMMEDIATE:-:- @far
mov x10,#18446744073709551615
### op set [CONST] dreg:REGISTER:GP:UINT64 {constant:one}
mov x10,#1
### op set [CONST] dreg:REGISTER:GP:UINT64 {constant:zero}
mov x10,#0
### op set [CONST] dreg:REGISTER:VEC:DOUBLE {constant:one}
fmov v1.2d,#1.0
### op set [CONST] dreg:REGISTER:VEC:DOUBLE {constant:zero}
dup v1.2d,xzr
### op set [CONST] dreg:REGISTER:VEC:FP8E4M3 {constant:zero}
dup v1.16b,wzr
### op set [CONST] dreg:REGISTER:VEC:FP8E5M2 {constant:zero}
dup v1.16b,wzr
### op set [CONST] dreg:REGISTER:VEC:HALF {constant:one}
fmov v1.8h,#1.0
### op set [CONST] dreg:REGISTER:VEC:HALF {constant:zero}
dup v1.8h,wzr
### op set [CONST] dreg:REGISTER:VEC:SINGLE {constant:one}
fmov v1.4s,#1.0
### op set [CONST] dreg:REGISTER:VEC:SINGLE {constant:zero}
dup v1.4s,wzr
### op set [CONST] dreg:REGISTER:VEC:SINT16 {constant:one}
movi v1.8h,#1
### op set [CONST] dreg:REGISTER:VEC:SINT32 {constant:one}
movi v1.4s,#1
### op set [CONST] dreg:REGISTER:VEC:SINT8 {constant:one}
movi v1.16b,#1
### op set [CONST] dreg:REGISTER:VEC:UINT16 {constant:one}
movi v1.8h,#1
### op set [CONST] dreg:REGISTER:VEC:UINT32 {constant:one}
movi v1.4s,#1
### op set [CONST] dreg:REGISTER:VEC:UINT8 {constant:one}
movi v1.16b,#1
### op set [PARAM,VLEN] param:NAME:-:-
mov %[p],#16
### op set [VLEN] dreg:REGISTER:GP:UINT64
mov x10,#2
### op shift [SHL] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64
lsl x12,x10,x11
### op shift [SHL] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:-
lsl x11,x10,#0
### op shift [SHL] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:- @far
lsl x11,x10,#63
### op shift [SHL] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64
lsl x12,x10,x11
### op shift [SHL] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:-
lsl x11,x10,#0
### op shift [SHL] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:- @far
lsl x11,x10,#63
### op shift [SHR] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64
lsr x12,x10,x11
### op shift [SHR] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:-
lsr x11,x10,#0
### op shift [SHR] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:- @far
lsr x11,x10,#63
### op shift [SHR] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64
lsr x12,x10,x11
### op shift [SHR] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:-
lsr x11,x10,#0
### op shift [SHR] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:- @far
lsr x11,x10,#63
### op store [GOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
str d1, [x10, x11]
### op store [GOFFSET] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
str b1, [x10, x11]
### op store [GOFFSET] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
str b1, [x10, x11]
### op store [GOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
str h1, [x10, x11]
### op store [GOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
str s1, [x10, x11]
### op store [GOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
strh w10, [x11, x12]
### op store [GOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
str w10, [x11, x12]
### op store [GOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
str x10, [x11, x12]
### op store [GOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
strb w10, [x11, x12]
### op store [GOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
strh w10, [x11, x12]
### op store [GOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
str w10, [x11, x12]
### op store [GOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
str x10, [x11, x12]
### op store [GOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
strb w10, [x11, x12]
### op store [IOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
str d1, [x10]
### op store [IOFFSET] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
str b1, [x10]
### op store [IOFFSET] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
str b1, [x10]
### op store [IOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
str h1, [x10]
### op store [IOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
str s1, [x10]
### op store [IOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
strh w10, [x11]
### op store [IOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
str w10, [x11]
### op store [IOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
str x10, [x11]
### op store [IOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
strb w10, [x11]
### op store [IOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
strh w10, [x11]
### op store [IOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
str w10, [x11]
### op store [IOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
str x10, [x11]
### op store [IOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
strb w10, [x11]
### op store [IOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
str q1, [x10]
### op store [IOFFSET] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
str q1, [x10]
### op store [IOFFSET] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
str q1, [x10]
### op store [IOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
str q1, [x10]
### op store [IOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
str q1, [x10]
### op store [IOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
str q1, [x10]
### op store [IOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
str q1, [x10]
### op store [IOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
str q1, [x10]
### op store [IOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
str q1, [x10]
### op store [IOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
str q1, [x10]
### op store [IOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
str q1, [x10]
### op store [IOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
str q1, [x10]
### op store [IOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:-
str q1, [x10]
### op store [PARAM] adreg:REGISTER:FP:DOUBLE param:NAME:-:-
str d1, %[p]
### op store [PARAM] adreg:REGISTER:FP:FP8E4M3 param:NAME:-:-
str b1, %[p]
### op store [PARAM] adreg:REGISTER:FP:FP8E5M2 param:NAME:-:-
str b1, %[p]
### op store [PARAM] adreg:REGISTER:FP:HALF param:NAME:-:-
str h1, %[p]
### op store [PARAM] adreg:REGISTER:FP:SINGLE param:NAME:-:-
str s1, %[p]
### op store [PARAM] adreg:REGISTER:GP:SINT16 param:NAME:-:-
strh w10, %[p]
### op store [PARAM] adreg:REGISTER:GP:SINT32 param:NAME:-:-
str w10, %[p]
### op store [PARAM] adreg:REGISTER:GP:SINT64 param:NAME:-:-
str x10, %[p]
### op store [PARAM] adreg:REGISTER:GP:SINT8 param:NAME:-:-
strb w10, %[p]
### op store [PARAM] adreg:REGISTER:GP:UINT16 param:NAME:-:-
strh w10, %[p]
### op store [PARAM] adreg:REGISTER:GP:UINT32 param:NAME:-:-
str w10, %[p]
### op store [PARAM] adreg:REGISTER:GP:UINT64 param:NAME:-:-
str x10, %[p]
### op store [PARAM] adreg:REGISTER:GP:UINT8 param:NAME:-:-
strb w10, %[p]
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE iinc:IMMEDIATE:-:- {nstructs:4}
st4 {v1.2d, v2.2d, v3.2d, v4.2d}, [x10], #64
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.2d, v2.2d, v3.2d, v4.2d}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE iinc:IMMEDIATE:-:- {nstructs:3}
st3 {v1.2d, v2.2d, v3.2d}, [x10], #48
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.2d, v2.2d, v3.2d}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE iinc:IMMEDIATE:-:- {nstructs:2}
st2 {v1.2d, v2.2d}, [x10], #32
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.2d, v2.2d}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.d, v2.d}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
st2 {v1.d, v2.d}[1], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.d, v2.d, v3.d}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
st3 {v1.d, v2.d, v3.d}[1], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE{ILANE} ddreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.d, v2.d, v3.d, v4.d}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE{ILANE} ddreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
st4 {v1.d, v2.d, v3.d, v4.d}[1], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 iinc:IMMEDIATE:-:- {nstructs:4}
st4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], #64
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 iinc:IMMEDIATE:-:- {nstructs:3}
st3 {v1.16b, v2.16b, v3.16b}, [x10], #48
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.16b, v2.16b, v3.16b}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3 iinc:IMMEDIATE:-:- {nstructs:2}
st2 {v1.16b, v2.16b}, [x10], #32
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3 increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.16b, v2.16b}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.b, v2.b}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
st2 {v1.b, v2.b}[15], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.b, v2.b, v3.b}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
st3 {v1.b, v2.b, v3.b}[15], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:FP8E4M3{ILANE} ddreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.b, v2.b, v3.b, v4.b}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:FP8E4M3{ILANE} ddreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
st4 {v1.b, v2.b, v3.b, v4.b}[15], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 iinc:IMMEDIATE:-:- {nstructs:4}
st4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], #64
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 iinc:IMMEDIATE:-:- {nstructs:3}
st3 {v1.16b, v2.16b, v3.16b}, [x10], #48
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.16b, v2.16b, v3.16b}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2 iinc:IMMEDIATE:-:- {nstructs:2}
st2 {v1.16b, v2.16b}, [x10], #32
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2 increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.16b, v2.16b}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.b, v2.b}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
st2 {v1.b, v2.b}[15], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.b, v2.b, v3.b}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
st3 {v1.b, v2.b, v3.b}[15], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:FP8E5M2{ILANE} ddreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.b, v2.b, v3.b, v4.b}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:FP8E5M2{ILANE} ddreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
st4 {v1.b, v2.b, v3.b, v4.b}[15], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF iinc:IMMEDIATE:-:- {nstructs:4}
st4 {v1.8h, v2.8h, v3.8h, v4.8h}, [x10], #64
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.8h, v2.8h, v3.8h, v4.8h}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF iinc:IMMEDIATE:-:- {nstructs:3}
st3 {v1.8h, v2.8h, v3.8h}, [x10], #48
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.8h, v2.8h, v3.8h}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF iinc:IMMEDIATE:-:- {nstructs:2}
st2 {v1.8h, v2.8h}, [x10], #32
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.8h, v2.8h}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.h, v2.h}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
st2 {v1.h, v2.h}[7], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.h, v2.h, v3.h}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
st3 {v1.h, v2.h, v3.h}[7], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF{ILANE} ddreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.h, v2.h, v3.h, v4.h}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF{ILANE} ddreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
st4 {v1.h, v2.h, v3.h, v4.h}[7], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE iinc:IMMEDIATE:-:- {nstructs:4}
st4 {v1.4s, v2.4s, v3.4s, v4.4s}, [x10], #64
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.4s, v2.4s, v3.4s, v4.4s}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE iinc:IMMEDIATE:-:- {nstructs:3}
st3 {v1.4s, v2.4s, v3.4s}, [x10], #48
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.4s, v2.4s, v3.4s}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE iinc:IMMEDIATE:-:- {nstructs:2}
st2 {v1.4s, v2.4s}, [x10], #32
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.4s, v2.4s}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.s, v2.s}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
st2 {v1.s, v2.s}[3], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.s, v2.s, v3.s}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
st3 {v1.s, v2.s, v3.s}[3], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE{ILANE} ddreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.s, v2.s, v3.s, v4.s}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE{ILANE} ddreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
st4 {v1.s, v2.s, v3.s, v4.s}[3], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 iinc:IMMEDIATE:-:- {nstructs:4}
st4 {v1.8h, v2.8h, v3.8h, v4.8h}, [x10], #64
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.8h, v2.8h, v3.8h, v4.8h}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 iinc:IMMEDIATE:-:- {nstructs:3}
st3 {v1.8h, v2.8h, v3.8h}, [x10], #48
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.8h, v2.8h, v3.8h}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16 iinc:IMMEDIATE:-:- {nstructs:2}
st2 {v1.8h, v2.8h}, [x10], #32
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16 increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.8h, v2.8h}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.h, v2.h}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
st2 {v1.h, v2.h}[7], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.h, v2.h, v3.h}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
st3 {v1.h, v2.h, v3.h}[7], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16{ILANE} ddreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.h, v2.h, v3.h, v4.h}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16{ILANE} ddreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
st4 {v1.h, v2.h, v3.h, v4.h}[7], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 iinc:IMMEDIATE:-:- {nstructs:4}
st4 {v1.4s, v2.4s, v3.4s, v4.4s}, [x10], #64
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.4s, v2.4s, v3.4s, v4.4s}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 iinc:IMMEDIATE:-:- {nstructs:3}
st3 {v1.4s, v2.4s, v3.4s}, [x10], #48
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.4s, v2.4s, v3.4s}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32 iinc:IMMEDIATE:-:- {nstructs:2}
st2 {v1.4s, v2.4s}, [x10], #32
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32 increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.4s, v2.4s}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.s, v2.s}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
st2 {v1.s, v2.s}[3], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.s, v2.s, v3.s}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
st3 {v1.s, v2.s, v3.s}[3], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32{ILANE} ddreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.s, v2.s, v3.s, v4.s}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32{ILANE} ddreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
st4 {v1.s, v2.s, v3.s, v4.s}[3], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 iinc:IMMEDIATE:-:- {nstructs:4}
st4 {v1.2d, v2.2d, v3.2d, v4.2d}, [x10], #64
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.2d, v2.2d, v3.2d, v4.2d}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 iinc:IMMEDIATE:-:- {nstructs:3}
st3 {v1.2d, v2.2d, v3.2d}, [x10], #48
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.2d, v2.2d, v3.2d}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64 iinc:IMMEDIATE:-:- {nstructs:2}
st2 {v1.2d, v2.2d}, [x10], #32
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64 increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.2d, v2.2d}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.d, v2.d}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
st2 {v1.d, v2.d}[1], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.d, v2.d, v3.d}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
st3 {v1.d, v2.d, v3.d}[1], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64{ILANE} ddreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.d, v2.d, v3.d, v4.d}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64{ILANE} ddreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
st4 {v1.d, v2.d, v3.d, v4.d}[1], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 iinc:IMMEDIATE:-:- {nstructs:4}
st4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], #64
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 iinc:IMMEDIATE:-:- {nstructs:3}
st3 {v1.16b, v2.16b, v3.16b}, [x10], #48
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.16b, v2.16b, v3.16b}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8 iinc:IMMEDIATE:-:- {nstructs:2}
st2 {v1.16b, v2.16b}, [x10], #32
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8 increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.16b, v2.16b}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.b, v2.b}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
st2 {v1.b, v2.b}[15], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.b, v2.b, v3.b}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
st3 {v1.b, v2.b, v3.b}[15], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8{ILANE} ddreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.b, v2.b, v3.b, v4.b}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8{ILANE} ddreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
st4 {v1.b, v2.b, v3.b, v4.b}[15], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 iinc:IMMEDIATE:-:- {nstructs:4}
st4 {v1.8h, v2.8h, v3.8h, v4.8h}, [x10], #64
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.8h, v2.8h, v3.8h, v4.8h}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 iinc:IMMEDIATE:-:- {nstructs:3}
st3 {v1.8h, v2.8h, v3.8h}, [x10], #48
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.8h, v2.8h, v3.8h}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16 iinc:IMMEDIATE:-:- {nstructs:2}
st2 {v1.8h, v2.8h}, [x10], #32
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16 increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.8h, v2.8h}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.h, v2.h}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
st2 {v1.h, v2.h}[7], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} cdreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.h, v2.h, v3.h}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} cdreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
st3 {v1.h, v2.h, v3.h}[7], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} cdreg:REGISTER:VEC:UINT16{ILANE} ddreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.h, v2.h, v3.h, v4.h}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} cdreg:REGISTER:VEC:UINT16{ILANE} ddreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
st4 {v1.h, v2.h, v3.h, v4.h}[7], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 iinc:IMMEDIATE:-:- {nstructs:4}
st4 {v1.4s, v2.4s, v3.4s, v4.4s}, [x10], #64
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.4s, v2.4s, v3.4s, v4.4s}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 iinc:IMMEDIATE:-:- {nstructs:3}
st3 {v1.4s, v2.4s, v3.4s}, [x10], #48
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.4s, v2.4s, v3.4s}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32 iinc:IMMEDIATE:-:- {nstructs:2}
st2 {v1.4s, v2.4s}, [x10], #32
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32 increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.4s, v2.4s}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.s, v2.s}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
st2 {v1.s, v2.s}[3], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} cdreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.s, v2.s, v3.s}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} cdreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
st3 {v1.s, v2.s, v3.s}[3], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} cdreg:REGISTER:VEC:UINT32{ILANE} ddreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.s, v2.s, v3.s, v4.s}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} cdreg:REGISTER:VEC:UINT32{ILANE} ddreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
st4 {v1.s, v2.s, v3.s, v4.s}[3], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 iinc:IMMEDIATE:-:- {nstructs:4}
st4 {v1.2d, v2.2d, v3.2d, v4.2d}, [x10], #64
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.2d, v2.2d, v3.2d, v4.2d}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 iinc:IMMEDIATE:-:- {nstructs:3}
st3 {v1.2d, v2.2d, v3.2d}, [x10], #48
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.2d, v2.2d, v3.2d}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64 iinc:IMMEDIATE:-:- {nstructs:2}
st2 {v1.2d, v2.2d}, [x10], #32
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64 increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.2d, v2.2d}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.d, v2.d}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
st2 {v1.d, v2.d}[1], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} cdreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.d, v2.d, v3.d}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} cdreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
st3 {v1.d, v2.d, v3.d}[1], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} cdreg:REGISTER:VEC:UINT64{ILANE} ddreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.d, v2.d, v3.d, v4.d}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} cdreg:REGISTER:VEC:UINT64{ILANE} ddreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
st4 {v1.d, v2.d, v3.d, v4.d}[1], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 iinc:IMMEDIATE:-:- {nstructs:4}
st4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], #64
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 iinc:IMMEDIATE:-:- {nstructs:3}
st3 {v1.16b, v2.16b, v3.16b}, [x10], #48
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.16b, v2.16b, v3.16b}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8 iinc:IMMEDIATE:-:- {nstructs:2}
st2 {v1.16b, v2.16b}, [x10], #32
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8 increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.16b, v2.16b}, [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2}
st2 {v1.b, v2.b}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:2} @far
st2 {v1.b, v2.b}[15], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3}
st3 {v1.b, v2.b, v3.b}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:3} @far
st3 {v1.b, v2.b, v3.b}[15], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT8{ILANE} ddreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4}
st4 {v1.b, v2.b, v3.b, v4.b}[0], [x10], x11
### op store [POSTINC,STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT8{ILANE} ddreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 {nstructs:4} @far
st4 {v1.b, v2.b, v3.b, v4.b}[15], [x10], x11
### op store [POSTINC] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
str d1, [x10], #-256
### op store [POSTINC] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
str d1, [x10], #255
### op store [POSTINC] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
str d1, [x10], x11
### op store [POSTINC] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
str b1, [x10], #-256
### op store [POSTINC] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
str b1, [x10], #255
### op store [POSTINC] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
str b1, [x10], x11
### op store [POSTINC] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
str b1, [x10], #-256
### op store [POSTINC] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
str b1, [x10], #255
### op store [POSTINC] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
str b1, [x10], x11
### op store [POSTINC] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
str h1, [x10], #-256
### op store [POSTINC] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
str h1, [x10], #255
### op store [POSTINC] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
str h1, [x10], x11
### op store [POSTINC] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
str s1, [x10], #-256
### op store [POSTINC] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
str s1, [x10], #255
### op store [POSTINC] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
str s1, [x10], x11
### op store [POSTINC] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
strh w10, [x11], #-256
### op store [POSTINC] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
strh w10, [x11], #255
### op store [POSTINC] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
strh w10, [x11], x12
### op store [POSTINC] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
str w10, [x11], #-256
### op store [POSTINC] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
str w10, [x11], #255
### op store [POSTINC] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
str w10, [x11], x12
### op store [POSTINC] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
str x10, [x11], #-256
### op store [POSTINC] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
str x10, [x11], #255
### op store [POSTINC] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
str x10, [x11], x12
### op store [POSTINC] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
strb w10, [x11], #-256
### op store [POSTINC] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
strb w10, [x11], #255
### op store [POSTINC] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
strb w10, [x11], x12
### op store [POSTINC] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
strh w10, [x11], #-256
### op store [POSTINC] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
strh w10, [x11], #255
### op store [POSTINC] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
strh w10, [x11], x12
### op store [POSTINC] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
str w10, [x11], #-256
### op store [POSTINC] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
str w10, [x11], #255
### op store [POSTINC] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
str w10, [x11], x12
### op store [POSTINC] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
str x10, [x11], #-256
### op store [POSTINC] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
str x10, [x11], #255
### op store [POSTINC] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
str x10, [x11], x12
### op store [POSTINC] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
strb w10, [x11], #-256
### op store [POSTINC] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
strb w10, [x11], #255
### op store [POSTINC] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
strb w10, [x11], x12
### op store [POSTINC] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
str q1, [x10], #-256
### op store [POSTINC] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
str q1, [x10], #255
### op store [POSTINC] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
st1 {v1.2d}, [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
st1 {v1.d}[0], [x10], #8
### op store [POSTINC] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
st1 {v1.d}[1], [x10], #8
### op store [POSTINC] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
st1 {v1.d}[0], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
st1 {v1.d}[1], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
str q1, [x10], #-256
### op store [POSTINC] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
str q1, [x10], #255
### op store [POSTINC] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
st1 {v1.16b}, [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
st1 {v1.b}[0], [x10], #1
### op store [POSTINC] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
st1 {v1.b}[15], [x10], #1
### op store [POSTINC] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
st1 {v1.b}[0], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
st1 {v1.b}[15], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
str q1, [x10], #-256
### op store [POSTINC] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
str q1, [x10], #255
### op store [POSTINC] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
st1 {v1.16b}, [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
st1 {v1.b}[0], [x10], #1
### op store [POSTINC] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
st1 {v1.b}[15], [x10], #1
### op store [POSTINC] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
st1 {v1.b}[0], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
st1 {v1.b}[15], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
str q1, [x10], #-256
### op store [POSTINC] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
str q1, [x10], #255
### op store [POSTINC] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
st1 {v1.8h}, [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
st1 {v1.h}[0], [x10], #2
### op store [POSTINC] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
st1 {v1.h}[7], [x10], #2
### op store [POSTINC] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
st1 {v1.h}[0], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
st1 {v1.h}[7], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
str q1, [x10], #-256
### op store [POSTINC] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
str q1, [x10], #255
### op store [POSTINC] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
st1 {v1.4s}, [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
st1 {v1.s}[0], [x10], #4
### op store [POSTINC] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
st1 {v1.s}[3], [x10], #4
### op store [POSTINC] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
st1 {v1.s}[0], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
st1 {v1.s}[3], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
str q1, [x10], #-256
### op store [POSTINC] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
str q1, [x10], #255
### op store [POSTINC] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
st1 {v1.8h}, [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
st1 {v1.h}[0], [x10], #2
### op store [POSTINC] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
st1 {v1.h}[7], [x10], #2
### op store [POSTINC] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
st1 {v1.h}[0], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
st1 {v1.h}[7], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
str q1, [x10], #-256
### op store [POSTINC] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
str q1, [x10], #255
### op store [POSTINC] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
st1 {v1.4s}, [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
st1 {v1.s}[0], [x10], #4
### op store [POSTINC] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
st1 {v1.s}[3], [x10], #4
### op store [POSTINC] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
st1 {v1.s}[0], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
st1 {v1.s}[3], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
str q1, [x10], #-256
### op store [POSTINC] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
str q1, [x10], #255
### op store [POSTINC] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
st1 {v1.2d}, [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
st1 {v1.d}[0], [x10], #8
### op store [POSTINC] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
st1 {v1.d}[1], [x10], #8
### op store [POSTINC] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
st1 {v1.d}[0], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
st1 {v1.d}[1], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
str q1, [x10], #-256
### op store [POSTINC] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
str q1, [x10], #255
### op store [POSTINC] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
st1 {v1.16b}, [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
st1 {v1.b}[0], [x10], #1
### op store [POSTINC] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
st1 {v1.b}[15], [x10], #1
### op store [POSTINC] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
st1 {v1.b}[0], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
st1 {v1.b}[15], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
str q1, [x10], #-256
### op store [POSTINC] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
str q1, [x10], #255
### op store [POSTINC] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
st1 {v1.8h}, [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
st1 {v1.h}[0], [x10], #2
### op store [POSTINC] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
st1 {v1.h}[7], [x10], #2
### op store [POSTINC] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
st1 {v1.h}[0], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
st1 {v1.h}[7], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
str q1, [x10], #-256
### op store [POSTINC] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
str q1, [x10], #255
### op store [POSTINC] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
st1 {v1.4s}, [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
st1 {v1.s}[0], [x10], #4
### op store [POSTINC] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
st1 {v1.s}[3], [x10], #4
### op store [POSTINC] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
st1 {v1.s}[0], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
st1 {v1.s}[3], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
str q1, [x10], #-256
### op store [POSTINC] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
str q1, [x10], #255
### op store [POSTINC] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
st1 {v1.2d}, [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
st1 {v1.d}[0], [x10], #8
### op store [POSTINC] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
st1 {v1.d}[1], [x10], #8
### op store [POSTINC] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
st1 {v1.d}[0], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
st1 {v1.d}[1], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:-
str q1, [x10], #-256
### op store [POSTINC] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:- @far
str q1, [x10], #255
### op store [POSTINC] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
st1 {v1.16b}, [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:-
st1 {v1.b}[0], [x10], #1
### op store [POSTINC] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- iinc:IMMEDIATE:-:- @far
st1 {v1.b}[15], [x10], #1
### op store [POSTINC] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64
st1 {v1.b}[0], [x10], x11
### op store [POSTINC] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- increg:REGISTER:GP:UINT64 @far
st1 {v1.b}[15], [x10], x11
### op store [STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE {nstructs:4}
st4 {v1.2d, v2.2d, v3.2d, v4.2d}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE {nstructs:3}
st3 {v1.2d, v2.2d, v3.2d}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE {nstructs:2}
st2 {v1.2d, v2.2d}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
st2 {v1.d, v2.d}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
st2 {v1.d, v2.d}[1], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
st3 {v1.d, v2.d, v3.d}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
st3 {v1.d, v2.d, v3.d}[1], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE{ILANE} ddreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
st4 {v1.d, v2.d, v3.d, v4.d}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:DOUBLE{ILANE} cdreg:REGISTER:VEC:DOUBLE{ILANE} ddreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
st4 {v1.d, v2.d, v3.d, v4.d}[1], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 {nstructs:4}
st4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 {nstructs:3}
st3 {v1.16b, v2.16b, v3.16b}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3 {nstructs:2}
st2 {v1.16b, v2.16b}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
st2 {v1.b, v2.b}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
st2 {v1.b, v2.b}[15], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
st3 {v1.b, v2.b, v3.b}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
st3 {v1.b, v2.b, v3.b}[15], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:FP8E4M3{ILANE} ddreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
st4 {v1.b, v2.b, v3.b, v4.b}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E4M3{ILANE} cdreg:REGISTER:VEC:FP8E4M3{ILANE} ddreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
st4 {v1.b, v2.b, v3.b, v4.b}[15], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 {nstructs:4}
st4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 {nstructs:3}
st3 {v1.16b, v2.16b, v3.16b}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2 {nstructs:2}
st2 {v1.16b, v2.16b}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
st2 {v1.b, v2.b}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
st2 {v1.b, v2.b}[15], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
st3 {v1.b, v2.b, v3.b}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
st3 {v1.b, v2.b, v3.b}[15], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:FP8E5M2{ILANE} ddreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
st4 {v1.b, v2.b, v3.b, v4.b}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:FP8E5M2{ILANE} cdreg:REGISTER:VEC:FP8E5M2{ILANE} ddreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
st4 {v1.b, v2.b, v3.b, v4.b}[15], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF {nstructs:4}
st4 {v1.8h, v2.8h, v3.8h, v4.8h}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF {nstructs:3}
st3 {v1.8h, v2.8h, v3.8h}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF {nstructs:2}
st2 {v1.8h, v2.8h}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
st2 {v1.h, v2.h}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
st2 {v1.h, v2.h}[7], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
st3 {v1.h, v2.h, v3.h}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
st3 {v1.h, v2.h, v3.h}[7], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF{ILANE} ddreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
st4 {v1.h, v2.h, v3.h, v4.h}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:HALF{ILANE} cdreg:REGISTER:VEC:HALF{ILANE} ddreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
st4 {v1.h, v2.h, v3.h, v4.h}[7], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE {nstructs:4}
st4 {v1.4s, v2.4s, v3.4s, v4.4s}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {nstructs:3}
st3 {v1.4s, v2.4s, v3.4s}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE {nstructs:2}
st2 {v1.4s, v2.4s}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
st2 {v1.s, v2.s}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
st2 {v1.s, v2.s}[3], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
st3 {v1.s, v2.s, v3.s}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
st3 {v1.s, v2.s, v3.s}[3], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE{ILANE} ddreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
st4 {v1.s, v2.s, v3.s, v4.s}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINGLE{ILANE} cdreg:REGISTER:VEC:SINGLE{ILANE} ddreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
st4 {v1.s, v2.s, v3.s, v4.s}[3], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 {nstructs:4}
st4 {v1.8h, v2.8h, v3.8h, v4.8h}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 {nstructs:3}
st3 {v1.8h, v2.8h, v3.8h}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16 {nstructs:2}
st2 {v1.8h, v2.8h}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
st2 {v1.h, v2.h}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
st2 {v1.h, v2.h}[7], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
st3 {v1.h, v2.h, v3.h}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
st3 {v1.h, v2.h, v3.h}[7], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16{ILANE} ddreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
st4 {v1.h, v2.h, v3.h, v4.h}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT16{ILANE} cdreg:REGISTER:VEC:SINT16{ILANE} ddreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
st4 {v1.h, v2.h, v3.h, v4.h}[7], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 {nstructs:4}
st4 {v1.4s, v2.4s, v3.4s, v4.4s}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {nstructs:3}
st3 {v1.4s, v2.4s, v3.4s}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32 {nstructs:2}
st2 {v1.4s, v2.4s}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
st2 {v1.s, v2.s}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
st2 {v1.s, v2.s}[3], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
st3 {v1.s, v2.s, v3.s}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
st3 {v1.s, v2.s, v3.s}[3], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32{ILANE} ddreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
st4 {v1.s, v2.s, v3.s, v4.s}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT32{ILANE} cdreg:REGISTER:VEC:SINT32{ILANE} ddreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
st4 {v1.s, v2.s, v3.s, v4.s}[3], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 {nstructs:4}
st4 {v1.2d, v2.2d, v3.2d, v4.2d}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 {nstructs:3}
st3 {v1.2d, v2.2d, v3.2d}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64 {nstructs:2}
st2 {v1.2d, v2.2d}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
st2 {v1.d, v2.d}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
st2 {v1.d, v2.d}[1], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
st3 {v1.d, v2.d, v3.d}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
st3 {v1.d, v2.d, v3.d}[1], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64{ILANE} ddreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
st4 {v1.d, v2.d, v3.d, v4.d}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT64{ILANE} cdreg:REGISTER:VEC:SINT64{ILANE} ddreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
st4 {v1.d, v2.d, v3.d, v4.d}[1], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 {nstructs:4}
st4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {nstructs:3}
st3 {v1.16b, v2.16b, v3.16b}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8 {nstructs:2}
st2 {v1.16b, v2.16b}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
st2 {v1.b, v2.b}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
st2 {v1.b, v2.b}[15], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
st3 {v1.b, v2.b, v3.b}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
st3 {v1.b, v2.b, v3.b}[15], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8{ILANE} ddreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
st4 {v1.b, v2.b, v3.b, v4.b}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:SINT8{ILANE} cdreg:REGISTER:VEC:SINT8{ILANE} ddreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
st4 {v1.b, v2.b, v3.b, v4.b}[15], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 {nstructs:4}
st4 {v1.8h, v2.8h, v3.8h, v4.8h}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 {nstructs:3}
st3 {v1.8h, v2.8h, v3.8h}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16 {nstructs:2}
st2 {v1.8h, v2.8h}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
st2 {v1.h, v2.h}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
st2 {v1.h, v2.h}[7], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} cdreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
st3 {v1.h, v2.h, v3.h}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} cdreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
st3 {v1.h, v2.h, v3.h}[7], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} cdreg:REGISTER:VEC:UINT16{ILANE} ddreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
st4 {v1.h, v2.h, v3.h, v4.h}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT16{ILANE} cdreg:REGISTER:VEC:UINT16{ILANE} ddreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
st4 {v1.h, v2.h, v3.h, v4.h}[7], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 {nstructs:4}
st4 {v1.4s, v2.4s, v3.4s, v4.4s}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {nstructs:3}
st3 {v1.4s, v2.4s, v3.4s}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32 {nstructs:2}
st2 {v1.4s, v2.4s}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
st2 {v1.s, v2.s}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
st2 {v1.s, v2.s}[3], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} cdreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
st3 {v1.s, v2.s, v3.s}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} cdreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
st3 {v1.s, v2.s, v3.s}[3], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} cdreg:REGISTER:VEC:UINT32{ILANE} ddreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
st4 {v1.s, v2.s, v3.s, v4.s}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT32{ILANE} cdreg:REGISTER:VEC:UINT32{ILANE} ddreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
st4 {v1.s, v2.s, v3.s, v4.s}[3], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 {nstructs:4}
st4 {v1.2d, v2.2d, v3.2d, v4.2d}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 {nstructs:3}
st3 {v1.2d, v2.2d, v3.2d}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64 {nstructs:2}
st2 {v1.2d, v2.2d}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
st2 {v1.d, v2.d}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
st2 {v1.d, v2.d}[1], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} cdreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
st3 {v1.d, v2.d, v3.d}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} cdreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
st3 {v1.d, v2.d, v3.d}[1], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} cdreg:REGISTER:VEC:UINT64{ILANE} ddreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
st4 {v1.d, v2.d, v3.d, v4.d}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{ILANE} cdreg:REGISTER:VEC:UINT64{ILANE} ddreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
st4 {v1.d, v2.d, v3.d, v4.d}[1], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 {nstructs:4}
st4 {v1.16b, v2.16b, v3.16b, v4.16b}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {nstructs:3}
st3 {v1.16b, v2.16b, v3.16b}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8 {nstructs:2}
st2 {v1.16b, v2.16b}, [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2}
st2 {v1.b, v2.b}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- {nstructs:2} @far
st2 {v1.b, v2.b}[15], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3}
st3 {v1.b, v2.b, v3.b}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- {nstructs:3} @far
st3 {v1.b, v2.b, v3.b}[15], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT8{ILANE} ddreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4}
st4 {v1.b, v2.b, v3.b, v4.b}[0], [x10]
### op store [STRUCT] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT8{ILANE} cdreg:REGISTER:VEC:UINT8{ILANE} ddreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- bdreg_lane:IMMEDIATE:-:- cdreg_lane:IMMEDIATE:-:- ddreg_lane:IMMEDIATE:-:- {nstructs:4} @far
st4 {v1.b, v2.b, v3.b, v4.b}[15], [x10]
### op store [VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [VOFFSET] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:-
str q1, [x10, #-256]
### op store [VOFFSET] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 voffset:IMMEDIATE:-:- adreg_lane:IMMEDIATE:-:- @far
str q1, [x10, #65520]
### op store [] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64
str d1, [x10]
### op store [] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64
str b1, [x10]
### op store [] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64
str b1, [x10]
### op store [] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64
str h1, [x10]
### op store [] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64
str s1, [x10]
### op store [] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64
strh w10, [x11]
### op store [] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64
str w10, [x11]
### op store [] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64
str x10, [x11]
### op store [] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64
strb w10, [x11]
### op store [] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64
strh w10, [x11]
### op store [] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64
str w10, [x11]
### op store [] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64
str x10, [x11]
### op store [] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64
strb w10, [x11]
### op store [] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64
st1 {v1.2d}, [x10]
### op store [] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
st1 {v1.d}[0], [x10]
### op store [] adreg:REGISTER:VEC:DOUBLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
st1 {v1.d}[1], [x10]
### op store [] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64
st1 {v1.16b}, [x10]
### op store [] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
st1 {v1.b}[0], [x10]
### op store [] adreg:REGISTER:VEC:FP8E4M3{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
st1 {v1.b}[15], [x10]
### op store [] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64
st1 {v1.16b}, [x10]
### op store [] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
st1 {v1.b}[0], [x10]
### op store [] adreg:REGISTER:VEC:FP8E5M2{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
st1 {v1.b}[15], [x10]
### op store [] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64
st1 {v1.8h}, [x10]
### op store [] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
st1 {v1.h}[0], [x10]
### op store [] adreg:REGISTER:VEC:HALF{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
st1 {v1.h}[7], [x10]
### op store [] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64
st1 {v1.4s}, [x10]
### op store [] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
st1 {v1.s}[0], [x10]
### op store [] adreg:REGISTER:VEC:SINGLE{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
st1 {v1.s}[3], [x10]
### op store [] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64
st1 {v1.8h}, [x10]
### op store [] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
st1 {v1.h}[0], [x10]
### op store [] adreg:REGISTER:VEC:SINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
st1 {v1.h}[7], [x10]
### op store [] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64
st1 {v1.4s}, [x10]
### op store [] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
st1 {v1.s}[0], [x10]
### op store [] adreg:REGISTER:VEC:SINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
st1 {v1.s}[3], [x10]
### op store [] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64
st1 {v1.2d}, [x10]
### op store [] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
st1 {v1.d}[0], [x10]
### op store [] adreg:REGISTER:VEC:SINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
st1 {v1.d}[1], [x10]
### op store [] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64
st1 {v1.16b}, [x10]
### op store [] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
st1 {v1.b}[0], [x10]
### op store [] adreg:REGISTER:VEC:SINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
st1 {v1.b}[15], [x10]
### op store [] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64
st1 {v1.8h}, [x10]
### op store [] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
st1 {v1.h}[0], [x10]
### op store [] adreg:REGISTER:VEC:UINT16{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
st1 {v1.h}[7], [x10]
### op store [] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64
st1 {v1.4s}, [x10]
### op store [] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
st1 {v1.s}[0], [x10]
### op store [] adreg:REGISTER:VEC:UINT32{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
st1 {v1.s}[3], [x10]
### op store [] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64
st1 {v1.2d}, [x10]
### op store [] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
st1 {v1.d}[0], [x10]
### op store [] adreg:REGISTER:VEC:UINT64{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
st1 {v1.d}[1], [x10]
### op store [] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64
st1 {v1.16b}, [x10]
### op store [] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:-
st1 {v1.b}[0], [x10]
### op store [] adreg:REGISTER:VEC:UINT8{ILANE} agreg:REGISTER:GP:UINT64 adreg_lane:IMMEDIATE:-:- @far
st1 {v1.b}[15], [x10]
### op sub [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64
sub x12,x10,x11
### op sub [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64{ISHIFT} cdreg:REGISTER:GP:SINT64 bdreg_shift:IMMEDIATE:-:-
sub x12,x10,x11
### op sub [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64{ISHIFT} cdreg:REGISTER:GP:SINT64 bdreg_shift:IMMEDIATE:-:- @far
sub x12,x10,x11, LSL #63
### op sub [] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:-
sub x11,x10,#-4095
### op sub [] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:- @far
sub x11,x10,#4095
### op sub [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64
sub x12,x10,x11
### op sub [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64{ISHIFT} cdreg:REGISTER:GP:UINT64 bdreg_shift:IMMEDIATE:-:-
sub x12,x10,x11
### op sub [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64{ISHIFT} cdreg:REGISTER:GP:UINT64 bdreg_shift:IMMEDIATE:-:- @far
sub x12,x10,x11, LSL #63
### op sub [] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:-
sub x11,x10,#-4095
### op sub [] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:- @far
sub x11,x10,#4095
