### method align(bytes=64)
.balign 64
### method asmfile_annotations()
.section .note.GNU-stack,"",%progbits
### method c_simd_size_function()
static inline size_t get_simd_size() {
    size_t byte_size = 0;
    __asm__ volatile(
        ".inst 0x04bf5820\n\t"    /* rdsvl x0, #1 */
        "mov %[byte_size], x0\n\t"
    : [byte_size] "=r" (byte_size)
    :
    : "x0"
    );
    return byte_size;
}
### method cb(cmp=NE, label=notequal, reg1=x0, reg2=x1)
cmp x0,x1
b.ne .notequal
### method compiler_flags()
['-march=armv9-a+sme+sve2+bf16+sve-b16b16+fp8fma+i8mm+sme2+sme-f64f64+sme-i16i64+sme-f16f16+sme-b16b16+sme-f8f16+sme-f8f32']
### method create_callconv(name=default)
<asmgen.callconv.callconv.callconv object>
### method enabled_features()
{B16B16, BF16, F16F16, F64F64, F8F16, F8F32, FA64, FP8FMA, I16I64, I8MM, SME2, SME_B16B16, SVE2}
### method freg(dt=DOUBLE, reg_idx=0)
d0
### method freg(dt=HALF, reg_idx=0)
h0
### method freg(dt=SINGLE, reg_idx=0)
s0
### method get_param_value(name=dummy)
dummy
### method get_parameters()
['SVE2', 'BF16', 'B16B16', 'FP8FMA', 'I8MM', 'SME2', 'F64F64', 'I16I64', 'F16F16', 'SME_B16B16', 'F8F16', 'F8F32', 'FA64']
### method greg(reg_idx=0)
x0
### method is_vla()
True
### method isaclear()
None
### method isadata()

### method isaendquirks(dt=DOUBLE, rt=<asmgen.registers.reg_tracker object>)
smstop
### method isaendquirks(dt=HALF, rt=<asmgen.registers.reg_tracker object>)
smstop
### method isaendquirks(dt=SINGLE, rt=<asmgen.registers.reg_tracker object>)
smstop
### method isaquirks(dt=DOUBLE, rt=<asmgen.registers.reg_tracker object>)
smstart
ptrue p0.d
ptrue pn8.d
### method isaquirks(dt=HALF, rt=<asmgen.registers.reg_tracker object>)
smstart
ptrue p0.h
ptrue pn8.h
### method isaquirks(dt=SINGLE, rt=<asmgen.registers.reg_tracker object>)
smstart
ptrue p0.s
ptrue pn8.s
### method jfzero(dt=DOUBLE, freg1=s0, freg2=s1, greg=x0, label=someloop)
fcmp s0,#0.0
b.eq .someloop
### method jfzero(dt=HALF, freg1=s0, freg2=s1, greg=x0, label=someloop)
fcmp s0,#0.0
b.eq .someloop
### method jfzero(dt=SINGLE, freg1=s0, freg2=s1, greg=x0, label=someloop)
fcmp s0,#0.0
b.eq .someloop
### method jump(label=someloop)
b .someloop
### method jvzero(dt=DOUBLE, freg=s2, greg=x0, label=someloop, vreg1=z0, vreg2=z1)
fcmne p1.d,z0.d,p0/z,#0,0
ptest p0, p1.b
b.any .someloop
### method jvzero(dt=HALF, freg=s2, greg=x0, label=someloop, vreg1=z0, vreg2=z1)
fcmne p1.d,z0.h,p0/z,#0,0
ptest p0, p1.b
b.any .someloop
### method jvzero(dt=SINGLE, freg=s2, greg=x0, label=someloop, vreg1=z0, vreg2=z1)
fcmne p1.d,z0.s,p0/z,#0,0
ptest p0, p1.b
b.any .someloop
### method jzero(label=someloop, reg=x0)
cmp x0,0
b.eq .someloop
### method kiterkleft(kleftreg=x1, kreg=x0, tmpreg=x2, unroll=4)
and x1,x0,#3
lsr x0,x0,#2
### method label(label=label)
.label:
### method labelstr(label=label)
.label
### method loopbegin(label=someloop, reg=x0)
.someloop:
sub x0,x0,1
### method loopbegin_nz(label=someloop, labelskip=someloop_nz, reg=x0)
cmp x0,0
b.eq .someloop_nz
.someloop:
sub x0,x0,1
### method loopend(label=someloop, reg=x0)
cmp x0,0
b.ne .someloop
### method max_fregs()
32
### method max_gregs()
32
### method max_tregs(dt=DOUBLE)
8
### method max_tregs(dt=HALF)
2
### method max_tregs(dt=SINGLE)
4
### method max_vregs()
32
### method nop()
nop
### method ret()
ret
### method simd_size
!NotImplementedError: sme is vector-length-agnostic: its vector length is known at run time only (set with VLEN, c_simd_size_function)
### method supported_on_host()
False
### method supportedby_cpuinfo(cpuinfo=invalid_isa)
False
### method tile_types()
[('treg8', 1), ('treg16', 2), ('treg32', 4), ('treg64', 8)]
### method treg(dt=DOUBLE, reg_idx=0)
za0
### method treg(dt=HALF, reg_idx=0)
za0
### method treg(dt=SINGLE, reg_idx=0)
za0
### method treg_tag(dt=DOUBLE)
treg64
### method treg_tag(dt=HALF)
treg16
### method treg_tag(dt=SINGLE)
treg32
### method vreg(reg_idx=0)
z0
### op add [MASK] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 amreg:REGISTER:MASK:BF16
!KeyError: <asm_data_type.BF16: 5>
### op add [MASK] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE amreg:REGISTER:MASK:DOUBLE
fadd z1.d,p1/m,z1.d,z2.d
### op add [MASK] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF amreg:REGISTER:MASK:HALF
fadd z1.h,p1/m,z1.h,z2.h
### op add [MASK] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE amreg:REGISTER:MASK:SINGLE
fadd z1.s,p1/m,z1.s,z2.s
### op add [MASK] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 amreg:REGISTER:MASK:SINT16
add z1.h,p1/m,z1.h,z2.h
### op add [MASK] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 amreg:REGISTER:MASK:SINT32
add z1.s,p1/m,z1.s,z2.s
### op add [MASK] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 amreg:REGISTER:MASK:SINT64
add z1.d,p1/m,z1.d,z2.d
### op add [MASK] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 amreg:REGISTER:MASK:SINT8
add z1.b,p1/m,z1.b,z2.b
### op add [VOFFSET] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:-
addvl x11,x10,#-32
### op add [VOFFSET] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:- @far
addvl x11,x10,#31
### op add [VOFFSET] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:-
addvl x11,x10,#-32
### op add [VOFFSET] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:- @far
addvl x11,x10,#31
### op add [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64
add x12,x10,x11
### op add [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64{ISHIFT} cdreg:REGISTER:GP:SINT64 bdreg_shift:IMMEDIATE:-:-
add x12,x10,x11
### op add [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64{ISHIFT} cdreg:REGISTER:GP:SINT64 bdreg_shift:IMMEDIATE:-:- @far
add x12,x10,x11, LSL #63
### op add [] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:-
add x11,x10,#-4095
### op add [] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:- @far
add x11,x10,#4095
### op add [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64
add x12,x10,x11
### op add [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64{ISHIFT} cdreg:REGISTER:GP:UINT64 bdreg_shift:IMMEDIATE:-:-
add x12,x10,x11
### op add [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64{ISHIFT} cdreg:REGISTER:GP:UINT64 bdreg_shift:IMMEDIATE:-:- @far
add x12,x10,x11, LSL #63
### op add [] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:-
add x11,x10,#-4095
### op add [] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:- @far
add x11,x10,#4095
### op add [] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16
!KeyError: <asm_data_type.BF16: 5>
### op add [] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16{BLOCKLANE} cdreg:REGISTER:VEC:BF16 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8}
!KeyError: <asm_data_type.BF16: 5>
### op add [] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16{BLOCKLANE} cdreg:REGISTER:VEC:BF16 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8} @far
!KeyError: <asm_data_type.BF16: 5>
### op add [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE
fadd z3.d,z1.d,z2.d
### op add [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE{BLOCKLANE} cdreg:REGISTER:VEC:DOUBLE bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:2}
fadd z3.d,z1.d,z2.d[0]
### op add [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE{BLOCKLANE} cdreg:REGISTER:VEC:DOUBLE bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:2} @far
fadd z3.d,z1.d,z2.d[1]
### op add [] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF
fadd z3.h,z1.h,z2.h
### op add [] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8}
fadd z3.h,z1.h,z2.h[0]
### op add [] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8} @far
fadd z3.h,z1.h,z2.h[7]
### op add [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE
fadd z3.s,z1.s,z2.s
### op add [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:4}
fadd z3.s,z1.s,z2.s[0]
### op add [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:4} @far
fadd z3.s,z1.s,z2.s[3]
### op add [] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{BLOCKLANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8}
add z3.h,z1.h,z2.h[0]
### op add [] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{BLOCKLANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8} @far
add z3.h,z1.h,z2.h[7]
### op add [] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32{BLOCKLANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:4}
add z3.s,z1.s,z2.s[0]
### op add [] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32{BLOCKLANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:4} @far
add z3.s,z1.s,z2.s[3]
### op add [] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64{BLOCKLANE} cdreg:REGISTER:VEC:SINT64 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:2}
add z3.d,z1.d,z2.d[0]
### op add [] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64{BLOCKLANE} cdreg:REGISTER:VEC:SINT64 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:2} @far
add z3.d,z1.d,z2.d[1]
### op add [] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:16}
add z3.b,z1.b,z2.b[0]
### op add [] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:16} @far
add z3.b,z1.b,z2.b[15]
### op fma [MASK,NP] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 amreg:REGISTER:MASK:BF16
!KeyError: <asm_data_type.BF16: 5>
### op fma [MASK,NP] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE amreg:REGISTER:MASK:DOUBLE
fmls z3.d,p1/m,z1.d,z2.d
### op fma [MASK,NP] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF amreg:REGISTER:MASK:HALF
fmls z3.h,p1/m,z1.h,z2.h
### op fma [MASK,NP] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE amreg:REGISTER:MASK:SINGLE
fmls z3.s,p1/m,z1.s,z2.s
### op fma [MASK,NP] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 amreg:REGISTER:MASK:SINT16
mls z3.h,p1/m,z1.h,z2.h
### op fma [MASK,NP] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 amreg:REGISTER:MASK:SINT32
mls z3.s,p1/m,z1.s,z2.s
### op fma [MASK,NP] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 amreg:REGISTER:MASK:SINT64
mls z3.d,p1/m,z1.d,z2.d
### op fma [MASK,NP] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 amreg:REGISTER:MASK:SINT8
mls z3.b,p1/m,z1.b,z2.b
### op fma [MASK] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 amreg:REGISTER:MASK:BF16
!KeyError: <asm_data_type.BF16: 5>
### op fma [MASK] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE amreg:REGISTER:MASK:DOUBLE
fmla z3.d,p1/m,z1.d,z2.d
### op fma [MASK] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF amreg:REGISTER:MASK:HALF
fmla z3.h,p1/m,z1.h,z2.h
### op fma [MASK] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE amreg:REGISTER:MASK:SINGLE
fmla z3.s,p1/m,z1.s,z2.s
### op fma [MASK] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 amreg:REGISTER:MASK:SINT16
mla z3.h,p1/m,z1.h,z2.h
### op fma [MASK] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 amreg:REGISTER:MASK:SINT32
mla z3.s,p1/m,z1.s,z2.s
### op fma [MASK] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 amreg:REGISTER:MASK:SINT64
mla z3.d,p1/m,z1.d,z2.d
### op fma [MASK] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 amreg:REGISTER:MASK:SINT8
mla z3.b,p1/m,z1.b,z2.b
### op fma [NP,PART] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
!KeyError: <asm_data_type.BF16: 5>
### op fma [NP,PART] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
!KeyError: <asm_data_type.BF16: 5>
### op fma [NP,PART] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:8,widening_method:SPLIT_INTERLEAVED}
!KeyError: <asm_data_type.BF16: 5>
### op fma [NP,PART] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:8,widening_method:SPLIT_INTERLEAVED} @far
!KeyError: <asm_data_type.BF16: 5>
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlslb z3.h,z1.b,z2.b
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlslt z3.h,z1.b,z2.b
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlsllbb z3.s,z1.b,z2.b
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlslltt z3.s,z1.b,z2.b
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
fmlslb z3.h,z1.b,z2.b[0]
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
fmlslt z3.h,z1.b,z2.b[15]
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
fmlsllbb z3.s,z1.b,z2.b[0]
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
fmlslltt z3.s,z1.b,z2.b[15]
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlslb z3.h,z1.b,z2.b
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlslt z3.h,z1.b,z2.b
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlsllbb z3.s,z1.b,z2.b
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlslltt z3.s,z1.b,z2.b
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
fmlslb z3.h,z1.b,z2.b[0]
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
fmlslt z3.h,z1.b,z2.b[15]
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
fmlsllbb z3.s,z1.b,z2.b[0]
### op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
fmlslltt z3.s,z1.b,z2.b[15]
### op fma [NP,PART] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlslb z3.s,z1.h,z2.h
### op fma [NP,PART] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlslt z3.s,z1.h,z2.h
### op fma [NP,PART] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:8,widening_method:SPLIT_INTERLEAVED}
fmlslb z3.s,z1.h,z2.h[0]
### op fma [NP,PART] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:8,widening_method:SPLIT_INTERLEAVED} @far
fmlslt z3.s,z1.h,z2.h[7]
### op fma [NP,PART] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
smlslb z3.s,z1.h,z2.h
### op fma [NP,PART] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
smlslt z3.s,z1.h,z2.h
### op fma [NP,PART] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{BLOCKLANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:8,widening_method:SPLIT_INTERLEAVED}
smlslb z3.s,z1.h,z2.h[0]
### op fma [NP,PART] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{BLOCKLANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:8,widening_method:SPLIT_INTERLEAVED} @far
smlslt z3.s,z1.h,z2.h[7]
### op fma [NP,PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT16 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
smlslb z3.h,z1.b,z2.b
### op fma [NP,PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT16 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
smlslt z3.h,z1.b,z2.b
### op fma [NP,PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
smlsllbb z3.s,z1.b,z2.b
### op fma [NP,PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
smlslltt z3.s,z1.b,z2.b
### op fma [NP,PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
smlslb z3.h,z1.b,z2.b[0]
### op fma [NP,PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
smlslt z3.h,z1.b,z2.b[15]
### op fma [NP,PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
smlsllbb z3.s,z1.b,z2.b[0]
### op fma [NP,PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
smlslltt z3.s,z1.b,z2.b[15]
### op fma [NP,PART] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
umlslb z3.s,z1.h,z2.h
### op fma [NP,PART] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
umlslt z3.s,z1.h,z2.h
### op fma [NP,PART] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16{BLOCKLANE} cdreg:REGISTER:VEC:UINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:8,widening_method:SPLIT_INTERLEAVED}
umlslb z3.s,z1.h,z2.h[0]
### op fma [NP,PART] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16{BLOCKLANE} cdreg:REGISTER:VEC:UINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:8,widening_method:SPLIT_INTERLEAVED} @far
umlslt z3.s,z1.h,z2.h[7]
### op fma [NP,PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT16 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
umlslb z3.h,z1.b,z2.b
### op fma [NP,PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT16 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
umlslt z3.h,z1.b,z2.b
### op fma [NP,PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
umlsllbb z3.s,z1.b,z2.b
### op fma [NP,PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
umlslltt z3.s,z1.b,z2.b
### op fma [NP,PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{BLOCKLANE} cdreg:REGISTER:VEC:UINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
umlslb z3.h,z1.b,z2.b[0]
### op fma [NP,PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{BLOCKLANE} cdreg:REGISTER:VEC:UINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
umlslt z3.h,z1.b,z2.b[15]
### op fma [NP,PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{BLOCKLANE} cdreg:REGISTER:VEC:UINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
umlsllbb z3.s,z1.b,z2.b[0]
### op fma [NP,PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{BLOCKLANE} cdreg:REGISTER:VEC:UINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
umlslltt z3.s,z1.b,z2.b[15]
### op fma [NP] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16{BLOCKLANE} cdreg:REGISTER:VEC:BF16 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8}
!KeyError: <asm_data_type.BF16: 5>
### op fma [NP] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16{BLOCKLANE} cdreg:REGISTER:VEC:BF16 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8} @far
!KeyError: <asm_data_type.BF16: 5>
### op fma [NP] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE{BLOCKLANE} cdreg:REGISTER:VEC:DOUBLE bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:2}
fmls z3.d,z1.d,z2.d[0]
### op fma [NP] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE{BLOCKLANE} cdreg:REGISTER:VEC:DOUBLE bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:2} @far
fmls z3.d,z1.d,z2.d[1]
### op fma [NP] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8}
fmls z3.h,z1.h,z2.h[0]
### op fma [NP] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8} @far
fmls z3.h,z1.h,z2.h[7]
### op fma [NP] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:4}
fmls z3.s,z1.s,z2.s[0]
### op fma [NP] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:4} @far
fmls z3.s,z1.s,z2.s[3]
### op fma [NP] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{BLOCKLANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8}
mls z3.h,z1.h,z2.h[0]
### op fma [NP] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{BLOCKLANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8} @far
mls z3.h,z1.h,z2.h[7]
### op fma [NP] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32{BLOCKLANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:4}
mls z3.s,z1.s,z2.s[0]
### op fma [NP] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32{BLOCKLANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:4} @far
mls z3.s,z1.s,z2.s[3]
### op fma [NP] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64{BLOCKLANE} cdreg:REGISTER:VEC:SINT64 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:2}
mls z3.d,z1.d,z2.d[0]
### op fma [NP] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64{BLOCKLANE} cdreg:REGISTER:VEC:SINT64 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:2} @far
mls z3.d,z1.d,z2.d[1]
### op fma [NP] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:16}
mls z3.b,z1.b,z2.b[0]
### op fma [NP] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:16} @far
mls z3.b,z1.b,z2.b[15]
### op fma [PART] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
!KeyError: <asm_data_type.BF16: 5>
### op fma [PART] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
!KeyError: <asm_data_type.BF16: 5>
### op fma [PART] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:8,widening_method:SPLIT_INTERLEAVED}
!KeyError: <asm_data_type.BF16: 5>
### op fma [PART] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:8,widening_method:SPLIT_INTERLEAVED} @far
!KeyError: <asm_data_type.BF16: 5>
### op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlalb z3.h,z1.b,z2.b
### op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlalt z3.h,z1.b,z2.b
### op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlallbb z3.s,z1.b,z2.b
### op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlalltt z3.s,z1.b,z2.b
### op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
fmlalb z3.h,z1.b,z2.b[0]
### op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
fmlalt z3.h,z1.b,z2.b[15]
### op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
fmlallbb z3.s,z1.b,z2.b[0]
### op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
fmlalltt z3.s,z1.b,z2.b[15]
### op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlalb z3.h,z1.b,z2.b
### op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlalt z3.h,z1.b,z2.b
### op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlallbb z3.s,z1.b,z2.b
### op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlalltt z3.s,z1.b,z2.b
### op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
fmlalb z3.h,z1.b,z2.b[0]
### op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
fmlalt z3.h,z1.b,z2.b[15]
### op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
fmlallbb z3.s,z1.b,z2.b[0]
### op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
fmlalltt z3.s,z1.b,z2.b[15]
### op fma [PART] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
fmlalb z3.s,z1.h,z2.h
### op fma [PART] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
fmlalt z3.s,z1.h,z2.h
### op fma [PART] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:8,widening_method:SPLIT_INTERLEAVED}
fmlalb z3.s,z1.h,z2.h[0]
### op fma [PART] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:8,widening_method:SPLIT_INTERLEAVED} @far
fmlalt z3.s,z1.h,z2.h[7]
### op fma [PART] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
smlalb z3.s,z1.h,z2.h
### op fma [PART] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
smlalt z3.s,z1.h,z2.h
### op fma [PART] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{BLOCKLANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:8,widening_method:SPLIT_INTERLEAVED}
smlalb z3.s,z1.h,z2.h[0]
### op fma [PART] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{BLOCKLANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:8,widening_method:SPLIT_INTERLEAVED} @far
smlalt z3.s,z1.h,z2.h[7]
### op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT16 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
smlalb z3.h,z1.b,z2.b
### op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT16 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
smlalt z3.h,z1.b,z2.b
### op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
smlallbb z3.s,z1.b,z2.b
### op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
smlalltt z3.s,z1.b,z2.b
### op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
smlalb z3.h,z1.b,z2.b[0]
### op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
smlalt z3.h,z1.b,z2.b[15]
### op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
smlallbb z3.s,z1.b,z2.b[0]
### op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
smlalltt z3.s,z1.b,z2.b[15]
### op fma [PART] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
umlalb z3.s,z1.h,z2.h
### op fma [PART] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
umlalt z3.s,z1.h,z2.h
### op fma [PART] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16{BLOCKLANE} cdreg:REGISTER:VEC:UINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:8,widening_method:SPLIT_INTERLEAVED}
umlalb z3.s,z1.h,z2.h[0]
### op fma [PART] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16{BLOCKLANE} cdreg:REGISTER:VEC:UINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:8,widening_method:SPLIT_INTERLEAVED} @far
umlalt z3.s,z1.h,z2.h[7]
### op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT16 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
umlalb z3.h,z1.b,z2.b
### op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT16 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
umlalt z3.h,z1.b,z2.b
### op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
umlallbb z3.s,z1.b,z2.b
### op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
umlalltt z3.s,z1.b,z2.b
### op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{BLOCKLANE} cdreg:REGISTER:VEC:UINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
umlalb z3.h,z1.b,z2.b[0]
### op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{BLOCKLANE} cdreg:REGISTER:VEC:UINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
umlalt z3.h,z1.b,z2.b[15]
### op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{BLOCKLANE} cdreg:REGISTER:VEC:UINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
umlallbb z3.s,z1.b,z2.b[0]
### op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{BLOCKLANE} cdreg:REGISTER:VEC:UINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
umlalltt z3.s,z1.b,z2.b[15]
### op fma [] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16{BLOCKLANE} cdreg:REGISTER:VEC:BF16 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8}
!KeyError: <asm_data_type.BF16: 5>
### op fma [] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16{BLOCKLANE} cdreg:REGISTER:VEC:BF16 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8} @far
!KeyError: <asm_data_type.BF16: 5>
### op fma [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE{BLOCKLANE} cdreg:REGISTER:VEC:DOUBLE bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:2}
fmla z3.d,z1.d,z2.d[0]
### op fma [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE{BLOCKLANE} cdreg:REGISTER:VEC:DOUBLE bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:2} @far
fmla z3.d,z1.d,z2.d[1]
### op fma [] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8}
fmla z3.h,z1.h,z2.h[0]
### op fma [] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8} @far
fmla z3.h,z1.h,z2.h[7]
### op fma [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:4}
fmla z3.s,z1.s,z2.s[0]
### op fma [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:4} @far
fmla z3.s,z1.s,z2.s[3]
### op fma [] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{BLOCKLANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8}
mla z3.h,z1.h,z2.h[0]
### op fma [] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{BLOCKLANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8} @far
mla z3.h,z1.h,z2.h[7]
### op fma [] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32{BLOCKLANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:4}
mla z3.s,z1.s,z2.s[0]
### op fma [] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32{BLOCKLANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:4} @far
mla z3.s,z1.s,z2.s[3]
### op fma [] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64{BLOCKLANE} cdreg:REGISTER:VEC:SINT64 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:2}
mla z3.d,z1.d,z2.d[0]
### op fma [] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64{BLOCKLANE} cdreg:REGISTER:VEC:SINT64 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:2} @far
mla z3.d,z1.d,z2.d[1]
### op fma [] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:16}
mla z3.b,z1.b,z2.b[0]
### op fma [] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:16} @far
mla z3.b,z1.b,z2.b[15]
### op fopa [MASK,NP] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:TILE:BF16 amreg:REGISTER:MASK:BF16 bmreg:REGISTER:MASK:BF16
!KeyError: <asm_data_type.BF16: 5>
### op fopa [MASK,NP] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:TILE:SINGLE amreg:REGISTER:MASK:BF16 bmreg:REGISTER:MASK:BF16 {widening_method:DOT_NEIGHBOURS}
!KeyError: <asm_data_type.BF16: 5>
### op fopa [MASK,NP] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:TILE:DOUBLE amreg:REGISTER:MASK:DOUBLE bmreg:REGISTER:MASK:DOUBLE
fmops za0.d,p1/m,p2/m,z1.d,z2.d
### op fopa [MASK,NP] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:TILE:HALF amreg:REGISTER:MASK:FP8E4M3 bmreg:REGISTER:MASK:FP8E4M3 {widening_method:DOT_NEIGHBOURS}
fmops za0.h,p1/m,p2/m,z1.b,z2.b
### op fopa [MASK,NP] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:TILE:SINGLE amreg:REGISTER:MASK:FP8E4M3 bmreg:REGISTER:MASK:FP8E4M3 {widening_method:DOT_NEIGHBOURS}
fmops za0.s,p1/m,p2/m,z1.b,z2.b
### op fopa [MASK,NP] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:TILE:HALF amreg:REGISTER:MASK:FP8E5M2 bmreg:REGISTER:MASK:FP8E5M2 {widening_method:DOT_NEIGHBOURS}
fmops za0.h,p1/m,p2/m,z1.b,z2.b
### op fopa [MASK,NP] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:TILE:SINGLE amreg:REGISTER:MASK:FP8E5M2 bmreg:REGISTER:MASK:FP8E5M2 {widening_method:DOT_NEIGHBOURS}
fmops za0.s,p1/m,p2/m,z1.b,z2.b
### op fopa [MASK,NP] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:TILE:HALF amreg:REGISTER:MASK:HALF bmreg:REGISTER:MASK:HALF
fmops za0.h,p1/m,p2/m,z1.h,z2.h
### op fopa [MASK,NP] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:TILE:SINGLE amreg:REGISTER:MASK:HALF bmreg:REGISTER:MASK:HALF {widening_method:DOT_NEIGHBOURS}
fmops za0.s,p1/m,p2/m,z1.h,z2.h
### op fopa [MASK,NP] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:TILE:SINGLE amreg:REGISTER:MASK:SINGLE bmreg:REGISTER:MASK:SINGLE
fmops za0.s,p1/m,p2/m,z1.s,z2.s
### op fopa [MASK,NP] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:TILE:SINT32 amreg:REGISTER:MASK:SINT16 bmreg:REGISTER:MASK:SINT16 {widening_method:DOT_NEIGHBOURS}
smops za0.s,p1/m,p2/m,z1.h,z2.h
### op fopa [MASK,NP] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:TILE:SINT64 amreg:REGISTER:MASK:SINT16 bmreg:REGISTER:MASK:UINT16 {widening_method:DOT_NEIGHBOURS}
sumops za0.d,p1/m,p2/m,z1.h,z2.h
### op fopa [MASK,NP] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:TILE:SINT32 amreg:REGISTER:MASK:SINT8 bmreg:REGISTER:MASK:SINT8 {widening_method:DOT_NEIGHBOURS}
smops za0.s,p1/m,p2/m,z1.b,z2.b
### op fopa [MASK,NP] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:TILE:SINT32 amreg:REGISTER:MASK:SINT8 bmreg:REGISTER:MASK:UINT8 {widening_method:DOT_NEIGHBOURS}
sumops za0.s,p1/m,p2/m,z1.b,z2.b
### op fopa [MASK,NP] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:TILE:SINT64 amreg:REGISTER:MASK:UINT16 bmreg:REGISTER:MASK:SINT16 {widening_method:DOT_NEIGHBOURS}
usmops za0.d,p1/m,p2/m,z1.h,z2.h
### op fopa [MASK,NP] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:TILE:UINT32 amreg:REGISTER:MASK:UINT16 bmreg:REGISTER:MASK:UINT16 {widening_method:DOT_NEIGHBOURS}
umops za0.s,p1/m,p2/m,z1.h,z2.h
### op fopa [MASK,NP] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:TILE:SINT32 amreg:REGISTER:MASK:UINT8 bmreg:REGISTER:MASK:SINT8 {widening_method:DOT_NEIGHBOURS}
usmops za0.s,p1/m,p2/m,z1.b,z2.b
### op fopa [MASK,NP] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:TILE:UINT32 amreg:REGISTER:MASK:UINT8 bmreg:REGISTER:MASK:UINT8 {widening_method:DOT_NEIGHBOURS}
umops za0.s,p1/m,p2/m,z1.b,z2.b
### op fopa [MASK] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:TILE:BF16 amreg:REGISTER:MASK:BF16 bmreg:REGISTER:MASK:BF16
!KeyError: <asm_data_type.BF16: 5>
### op fopa [MASK] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:TILE:SINGLE amreg:REGISTER:MASK:BF16 bmreg:REGISTER:MASK:BF16 {widening_method:DOT_NEIGHBOURS}
!KeyError: <asm_data_type.BF16: 5>
### op fopa [MASK] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:TILE:DOUBLE amreg:REGISTER:MASK:DOUBLE bmreg:REGISTER:MASK:DOUBLE
fmopa za0.d,p1/m,p2/m,z1.d,z2.d
### op fopa [MASK] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:TILE:HALF amreg:REGISTER:MASK:FP8E4M3 bmreg:REGISTER:MASK:FP8E4M3 {widening_method:DOT_NEIGHBOURS}
fmopa za0.h,p1/m,p2/m,z1.b,z2.b
### op fopa [MASK] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:TILE:SINGLE amreg:REGISTER:MASK:FP8E4M3 bmreg:REGISTER:MASK:FP8E4M3 {widening_method:DOT_NEIGHBOURS}
fmopa za0.s,p1/m,p2/m,z1.b,z2.b
### op fopa [MASK] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:TILE:HALF amreg:REGISTER:MASK:FP8E5M2 bmreg:REGISTER:MASK:FP8E5M2 {widening_method:DOT_NEIGHBOURS}
fmopa za0.h,p1/m,p2/m,z1.b,z2.b
### op fopa [MASK] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:TILE:SINGLE amreg:REGISTER:MASK:FP8E5M2 bmreg:REGISTER:MASK:FP8E5M2 {widening_method:DOT_NEIGHBOURS}
fmopa za0.s,p1/m,p2/m,z1.b,z2.b
### op fopa [MASK] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:TILE:HALF amreg:REGISTER:MASK:HALF bmreg:REGISTER:MASK:HALF
fmopa za0.h,p1/m,p2/m,z1.h,z2.h
### op fopa [MASK] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:TILE:SINGLE amreg:REGISTER:MASK:HALF bmreg:REGISTER:MASK:HALF {widening_method:DOT_NEIGHBOURS}
fmopa za0.s,p1/m,p2/m,z1.h,z2.h
### op fopa [MASK] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:TILE:SINGLE amreg:REGISTER:MASK:SINGLE bmreg:REGISTER:MASK:SINGLE
fmopa za0.s,p1/m,p2/m,z1.s,z2.s
### op fopa [MASK] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:TILE:SINT32 amreg:REGISTER:MASK:SINT16 bmreg:REGISTER:MASK:SINT16 {widening_method:DOT_NEIGHBOURS}
smopa za0.s,p1/m,p2/m,z1.h,z2.h
### op fopa [MASK] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:TILE:SINT64 amreg:REGISTER:MASK:SINT16 bmreg:REGISTER:MASK:UINT16 {widening_method:DOT_NEIGHBOURS}
sumopa za0.d,p1/m,p2/m,z1.h,z2.h
### op fopa [MASK] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:TILE:SINT32 amreg:REGISTER:MASK:SINT8 bmreg:REGISTER:MASK:SINT8 {widening_method:DOT_NEIGHBOURS}
smopa za0.s,p1/m,p2/m,z1.b,z2.b
### op fopa [MASK] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:TILE:SINT32 amreg:REGISTER:MASK:SINT8 bmreg:REGISTER:MASK:UINT8 {widening_method:DOT_NEIGHBOURS}
sumopa za0.s,p1/m,p2/m,z1.b,z2.b
### op fopa [MASK] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:TILE:SINT64 amreg:REGISTER:MASK:UINT16 bmreg:REGISTER:MASK:SINT16 {widening_method:DOT_NEIGHBOURS}
usmopa za0.d,p1/m,p2/m,z1.h,z2.h
### op fopa [MASK] adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:TILE:UINT32 amreg:REGISTER:MASK:UINT16 bmreg:REGISTER:MASK:UINT16 {widening_method:DOT_NEIGHBOURS}
umopa za0.s,p1/m,p2/m,z1.h,z2.h
### op fopa [MASK] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:TILE:SINT32 amreg:REGISTER:MASK:UINT8 bmreg:REGISTER:MASK:SINT8 {widening_method:DOT_NEIGHBOURS}
usmopa za0.s,p1/m,p2/m,z1.b,z2.b
### op fopa [MASK] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:TILE:UINT32 amreg:REGISTER:MASK:UINT8 bmreg:REGISTER:MASK:UINT8 {widening_method:DOT_NEIGHBOURS}
umopa za0.s,p1/m,p2/m,z1.b,z2.b
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 ddreg:REGISTER:VEC:BF16 offreg:REGISTER:GP:SINT64 {nvectors:4}
ldnt1h {z1.h, z5.h, z9.h, z13.h}, p8/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 offreg:REGISTER:GP:SINT64 {nvectors:2}
ldnt1h {z1.h, z9.h}, p8/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE offreg:REGISTER:GP:SINT64 {nvectors:4}
ldnt1d {z1.d, z5.d, z9.d, z13.d}, p8/z, [x10, x11, lsl #3]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE offreg:REGISTER:GP:SINT64 {nvectors:2}
ldnt1d {z1.d, z9.d}, p8/z, [x10, x11, lsl #3]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 offreg:REGISTER:GP:SINT64 {nvectors:4}
ldnt1b {z1.b, z5.b, z9.b, z13.b}, p8/z, [x10, x11]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 offreg:REGISTER:GP:SINT64 {nvectors:2}
ldnt1b {z1.b, z9.b}, p8/z, [x10, x11]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 offreg:REGISTER:GP:SINT64 {nvectors:4}
ldnt1b {z1.b, z5.b, z9.b, z13.b}, p8/z, [x10, x11]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 offreg:REGISTER:GP:SINT64 {nvectors:2}
ldnt1b {z1.b, z9.b}, p8/z, [x10, x11]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF offreg:REGISTER:GP:SINT64 {nvectors:4}
ldnt1h {z1.h, z5.h, z9.h, z13.h}, p8/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF offreg:REGISTER:GP:SINT64 {nvectors:2}
ldnt1h {z1.h, z9.h}, p8/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE offreg:REGISTER:GP:SINT64 {nvectors:4}
ldnt1w {z1.s, z5.s, z9.s, z13.s}, p8/z, [x10, x11, lsl #2]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE offreg:REGISTER:GP:SINT64 {nvectors:2}
ldnt1w {z1.s, z9.s}, p8/z, [x10, x11, lsl #2]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 offreg:REGISTER:GP:SINT64 {nvectors:4}
ldnt1h {z1.h, z5.h, z9.h, z13.h}, p8/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 offreg:REGISTER:GP:SINT64 {nvectors:2}
ldnt1h {z1.h, z9.h}, p8/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 offreg:REGISTER:GP:SINT64 {nvectors:4}
ldnt1w {z1.s, z5.s, z9.s, z13.s}, p8/z, [x10, x11, lsl #2]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 offreg:REGISTER:GP:SINT64 {nvectors:2}
ldnt1w {z1.s, z9.s}, p8/z, [x10, x11, lsl #2]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 offreg:REGISTER:GP:SINT64 {nvectors:4}
ldnt1d {z1.d, z5.d, z9.d, z13.d}, p8/z, [x10, x11, lsl #3]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 offreg:REGISTER:GP:SINT64 {nvectors:2}
ldnt1d {z1.d, z9.d}, p8/z, [x10, x11, lsl #3]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 offreg:REGISTER:GP:SINT64 {nvectors:4}
ldnt1b {z1.b, z5.b, z9.b, z13.b}, p8/z, [x10, x11]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 offreg:REGISTER:GP:SINT64 {nvectors:2}
ldnt1b {z1.b, z9.b}, p8/z, [x10, x11]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 offreg:REGISTER:GP:SINT64 {nvectors:4}
ldnt1h {z1.h, z5.h, z9.h, z13.h}, p8/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 offreg:REGISTER:GP:SINT64 {nvectors:2}
ldnt1h {z1.h, z9.h}, p8/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 offreg:REGISTER:GP:SINT64 {nvectors:4}
ldnt1w {z1.s, z5.s, z9.s, z13.s}, p8/z, [x10, x11, lsl #2]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 offreg:REGISTER:GP:SINT64 {nvectors:2}
ldnt1w {z1.s, z9.s}, p8/z, [x10, x11, lsl #2]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 offreg:REGISTER:GP:SINT64 {nvectors:4}
ldnt1d {z1.d, z5.d, z9.d, z13.d}, p8/z, [x10, x11, lsl #3]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 offreg:REGISTER:GP:SINT64 {nvectors:2}
ldnt1d {z1.d, z9.d}, p8/z, [x10, x11, lsl #3]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 offreg:REGISTER:GP:SINT64 {nvectors:4}
ldnt1b {z1.b, z5.b, z9.b, z13.b}, p8/z, [x10, x11]
### op load [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 offreg:REGISTER:GP:SINT64 {nvectors:2}
ldnt1b {z1.b, z9.b}, p8/z, [x10, x11]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 ddreg:REGISTER:VEC:BF16 offreg:REGISTER:GP:SINT64 {nstructs:4}
ld4h {z1.h, z2.h, z3.h, z4.h}, p1/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 offreg:REGISTER:GP:SINT64 {nstructs:3}
ld3h {z1.h, z2.h, z3.h}, p1/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 offreg:REGISTER:GP:SINT64 {nstructs:2}
ld2h {z1.h, z2.h}, p1/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE offreg:REGISTER:GP:SINT64 {nstructs:4}
ld4d {z1.d, z2.d, z3.d, z4.d}, p1/z, [x10, x11, lsl #3]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE offreg:REGISTER:GP:SINT64 {nstructs:3}
ld3d {z1.d, z2.d, z3.d}, p1/z, [x10, x11, lsl #3]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE offreg:REGISTER:GP:SINT64 {nstructs:2}
ld2d {z1.d, z2.d}, p1/z, [x10, x11, lsl #3]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 offreg:REGISTER:GP:SINT64 {nstructs:4}
ld4b {z1.b, z2.b, z3.b, z4.b}, p1/z, [x10, x11]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 offreg:REGISTER:GP:SINT64 {nstructs:3}
ld3b {z1.b, z2.b, z3.b}, p1/z, [x10, x11]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 offreg:REGISTER:GP:SINT64 {nstructs:2}
ld2b {z1.b, z2.b}, p1/z, [x10, x11]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 offreg:REGISTER:GP:SINT64 {nstructs:4}
ld4b {z1.b, z2.b, z3.b, z4.b}, p1/z, [x10, x11]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 offreg:REGISTER:GP:SINT64 {nstructs:3}
ld3b {z1.b, z2.b, z3.b}, p1/z, [x10, x11]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 offreg:REGISTER:GP:SINT64 {nstructs:2}
ld2b {z1.b, z2.b}, p1/z, [x10, x11]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF offreg:REGISTER:GP:SINT64 {nstructs:4}
ld4h {z1.h, z2.h, z3.h, z4.h}, p1/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF offreg:REGISTER:GP:SINT64 {nstructs:3}
ld3h {z1.h, z2.h, z3.h}, p1/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF offreg:REGISTER:GP:SINT64 {nstructs:2}
ld2h {z1.h, z2.h}, p1/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE offreg:REGISTER:GP:SINT64 {nstructs:4}
ld4w {z1.s, z2.s, z3.s, z4.s}, p1/z, [x10, x11, lsl #2]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE offreg:REGISTER:GP:SINT64 {nstructs:3}
ld3w {z1.s, z2.s, z3.s}, p1/z, [x10, x11, lsl #2]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE offreg:REGISTER:GP:SINT64 {nstructs:2}
ld2w {z1.s, z2.s}, p1/z, [x10, x11, lsl #2]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 offreg:REGISTER:GP:SINT64 {nstructs:4}
ld4h {z1.h, z2.h, z3.h, z4.h}, p1/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 offreg:REGISTER:GP:SINT64 {nstructs:3}
ld3h {z1.h, z2.h, z3.h}, p1/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 offreg:REGISTER:GP:SINT64 {nstructs:2}
ld2h {z1.h, z2.h}, p1/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 offreg:REGISTER:GP:SINT64 {nstructs:4}
ld4w {z1.s, z2.s, z3.s, z4.s}, p1/z, [x10, x11, lsl #2]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 offreg:REGISTER:GP:SINT64 {nstructs:3}
ld3w {z1.s, z2.s, z3.s}, p1/z, [x10, x11, lsl #2]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 offreg:REGISTER:GP:SINT64 {nstructs:2}
ld2w {z1.s, z2.s}, p1/z, [x10, x11, lsl #2]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 offreg:REGISTER:GP:SINT64 {nstructs:4}
ld4d {z1.d, z2.d, z3.d, z4.d}, p1/z, [x10, x11, lsl #3]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 offreg:REGISTER:GP:SINT64 {nstructs:3}
ld3d {z1.d, z2.d, z3.d}, p1/z, [x10, x11, lsl #3]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 offreg:REGISTER:GP:SINT64 {nstructs:2}
ld2d {z1.d, z2.d}, p1/z, [x10, x11, lsl #3]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 offreg:REGISTER:GP:SINT64 {nstructs:4}
ld4b {z1.b, z2.b, z3.b, z4.b}, p1/z, [x10, x11]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 offreg:REGISTER:GP:SINT64 {nstructs:3}
ld3b {z1.b, z2.b, z3.b}, p1/z, [x10, x11]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 offreg:REGISTER:GP:SINT64 {nstructs:2}
ld2b {z1.b, z2.b}, p1/z, [x10, x11]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 offreg:REGISTER:GP:SINT64 {nstructs:4}
ld4h {z1.h, z2.h, z3.h, z4.h}, p1/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 offreg:REGISTER:GP:SINT64 {nstructs:3}
ld3h {z1.h, z2.h, z3.h}, p1/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 offreg:REGISTER:GP:SINT64 {nstructs:2}
ld2h {z1.h, z2.h}, p1/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 offreg:REGISTER:GP:SINT64 {nstructs:4}
ld4w {z1.s, z2.s, z3.s, z4.s}, p1/z, [x10, x11, lsl #2]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 offreg:REGISTER:GP:SINT64 {nstructs:3}
ld3w {z1.s, z2.s, z3.s}, p1/z, [x10, x11, lsl #2]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 offreg:REGISTER:GP:SINT64 {nstructs:2}
ld2w {z1.s, z2.s}, p1/z, [x10, x11, lsl #2]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 offreg:REGISTER:GP:SINT64 {nstructs:4}
ld4d {z1.d, z2.d, z3.d, z4.d}, p1/z, [x10, x11, lsl #3]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 offreg:REGISTER:GP:SINT64 {nstructs:3}
ld3d {z1.d, z2.d, z3.d}, p1/z, [x10, x11, lsl #3]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 offreg:REGISTER:GP:SINT64 {nstructs:2}
ld2d {z1.d, z2.d}, p1/z, [x10, x11, lsl #3]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 offreg:REGISTER:GP:SINT64 {nstructs:4}
ld4b {z1.b, z2.b, z3.b, z4.b}, p1/z, [x10, x11]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 offreg:REGISTER:GP:SINT64 {nstructs:3}
ld3b {z1.b, z2.b, z3.b}, p1/z, [x10, x11]
### op load [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 offreg:REGISTER:GP:SINT64 {nstructs:2}
ld2b {z1.b, z2.b}, p1/z, [x10, x11]
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 offreg:REGISTER:GP:SINT64
ld1h {z1.h}, p1/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE offreg:REGISTER:GP:SINT64
ld1d {z1.d}, p1/z, [x10, x11, lsl #3]
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 offreg:REGISTER:GP:SINT64
ld1b {z1.b}, p1/z, [x10, x11]
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 offreg:REGISTER:GP:SINT64
ld1b {z1.b}, p1/z, [x10, x11]
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF offreg:REGISTER:GP:SINT64
ld1h {z1.h}, p1/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE offreg:REGISTER:GP:SINT64
ld1w {z1.s}, p1/z, [x10, x11, lsl #2]
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 offreg:REGISTER:GP:SINT64
ld1h {z1.h}, p1/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 offreg:REGISTER:GP:SINT64
ld1w {z1.s}, p1/z, [x10, x11, lsl #2]
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 offreg:REGISTER:GP:SINT64
ld1d {z1.d}, p1/z, [x10, x11, lsl #3]
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 offreg:REGISTER:GP:SINT64
ld1b {z1.b}, p1/z, [x10, x11]
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 offreg:REGISTER:GP:SINT64
ld1h {z1.h}, p1/z, [x10, x11, lsl #1]
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 offreg:REGISTER:GP:SINT64
ld1w {z1.s}, p1/z, [x10, x11, lsl #2]
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 offreg:REGISTER:GP:SINT64
ld1d {z1.d}, p1/z, [x10, x11, lsl #3]
### op load [GOFFSET,MASK] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 offreg:REGISTER:GP:SINT64
ld1b {z1.b}, p1/z, [x10, x11]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:TILE:BF16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1h {za0v.h[w12, 0]}, p1/z, [x10, x13, lsl #1]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:TILE:BF16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1h {za0v.h[w12, 7]}, p1/z, [x10, x13, lsl #1]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:TILE:BF16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1h {za0h.h[w12, 0]}, p1/z, [x10, x13, lsl #1]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:TILE:BF16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1h {za0h.h[w12, 7]}, p1/z, [x10, x13, lsl #1]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:TILE:DOUBLE{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1d {za0v.d[w12, 0]}, p1/z, [x10, x13, lsl #3]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:TILE:DOUBLE{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1d {za0v.d[w12, 1]}, p1/z, [x10, x13, lsl #3]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:TILE:DOUBLE{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1d {za0h.d[w12, 0]}, p1/z, [x10, x13, lsl #3]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:TILE:DOUBLE{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1d {za0h.d[w12, 1]}, p1/z, [x10, x13, lsl #3]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:TILE:FP8E4M3{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1b {za0v.b[w12, 0]}, p1/z, [x10, x13]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:TILE:FP8E4M3{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1b {za0v.b[w12, 15]}, p1/z, [x10, x13]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:TILE:FP8E4M3{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1b {za0h.b[w12, 0]}, p1/z, [x10, x13]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:TILE:FP8E4M3{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1b {za0h.b[w12, 15]}, p1/z, [x10, x13]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:TILE:FP8E5M2{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1b {za0v.b[w12, 0]}, p1/z, [x10, x13]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:TILE:FP8E5M2{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1b {za0v.b[w12, 15]}, p1/z, [x10, x13]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:TILE:FP8E5M2{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1b {za0h.b[w12, 0]}, p1/z, [x10, x13]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:TILE:FP8E5M2{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1b {za0h.b[w12, 15]}, p1/z, [x10, x13]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:TILE:HALF{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1h {za0v.h[w12, 0]}, p1/z, [x10, x13, lsl #1]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:TILE:HALF{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1h {za0v.h[w12, 7]}, p1/z, [x10, x13, lsl #1]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:TILE:HALF{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1h {za0h.h[w12, 0]}, p1/z, [x10, x13, lsl #1]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:TILE:HALF{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1h {za0h.h[w12, 7]}, p1/z, [x10, x13, lsl #1]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:TILE:SINGLE{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1w {za0v.s[w12, 0]}, p1/z, [x10, x13, lsl #2]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:TILE:SINGLE{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1w {za0v.s[w12, 3]}, p1/z, [x10, x13, lsl #2]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:TILE:SINGLE{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1w {za0h.s[w12, 0]}, p1/z, [x10, x13, lsl #2]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:TILE:SINGLE{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1w {za0h.s[w12, 3]}, p1/z, [x10, x13, lsl #2]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:TILE:SINT16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1h {za0v.h[w12, 0]}, p1/z, [x10, x13, lsl #1]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:TILE:SINT16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1h {za0v.h[w12, 7]}, p1/z, [x10, x13, lsl #1]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:TILE:SINT16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1h {za0h.h[w12, 0]}, p1/z, [x10, x13, lsl #1]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:TILE:SINT16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1h {za0h.h[w12, 7]}, p1/z, [x10, x13, lsl #1]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:TILE:SINT32{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1w {za0v.s[w12, 0]}, p1/z, [x10, x13, lsl #2]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:TILE:SINT32{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1w {za0v.s[w12, 3]}, p1/z, [x10, x13, lsl #2]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:TILE:SINT32{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1w {za0h.s[w12, 0]}, p1/z, [x10, x13, lsl #2]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:TILE:SINT32{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1w {za0h.s[w12, 3]}, p1/z, [x10, x13, lsl #2]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:TILE:SINT64{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1d {za0v.d[w12, 0]}, p1/z, [x10, x13, lsl #3]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:TILE:SINT64{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1d {za0v.d[w12, 1]}, p1/z, [x10, x13, lsl #3]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:TILE:SINT64{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1d {za0h.d[w12, 0]}, p1/z, [x10, x13, lsl #3]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:TILE:SINT64{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1d {za0h.d[w12, 1]}, p1/z, [x10, x13, lsl #3]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:TILE:SINT8{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1b {za0v.b[w12, 0]}, p1/z, [x10, x13]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:TILE:SINT8{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1b {za0v.b[w12, 15]}, p1/z, [x10, x13]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:TILE:SINT8{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1b {za0h.b[w12, 0]}, p1/z, [x10, x13]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:TILE:SINT8{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1b {za0h.b[w12, 15]}, p1/z, [x10, x13]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:TILE:UINT16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1h {za0v.h[w12, 0]}, p1/z, [x10, x13, lsl #1]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:TILE:UINT16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1h {za0v.h[w12, 7]}, p1/z, [x10, x13, lsl #1]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:TILE:UINT16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1h {za0h.h[w12, 0]}, p1/z, [x10, x13, lsl #1]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:TILE:UINT16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1h {za0h.h[w12, 7]}, p1/z, [x10, x13, lsl #1]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:TILE:UINT32{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1w {za0v.s[w12, 0]}, p1/z, [x10, x13, lsl #2]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:TILE:UINT32{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1w {za0v.s[w12, 3]}, p1/z, [x10, x13, lsl #2]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:TILE:UINT32{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1w {za0h.s[w12, 0]}, p1/z, [x10, x13, lsl #2]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:TILE:UINT32{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1w {za0h.s[w12, 3]}, p1/z, [x10, x13, lsl #2]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:TILE:UINT64{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1d {za0v.d[w12, 0]}, p1/z, [x10, x13, lsl #3]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:TILE:UINT64{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1d {za0v.d[w12, 1]}, p1/z, [x10, x13, lsl #3]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:TILE:UINT64{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1d {za0h.d[w12, 0]}, p1/z, [x10, x13, lsl #3]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:TILE:UINT64{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1d {za0h.d[w12, 1]}, p1/z, [x10, x13, lsl #3]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:TILE:UINT8{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1b {za0v.b[w12, 0]}, p1/z, [x10, x13]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:TILE:UINT8{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1b {za0v.b[w12, 15]}, p1/z, [x10, x13]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:TILE:UINT8{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
ld1b {za0h.b[w12, 0]}, p1/z, [x10, x13]
### op load [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:TILE:UINT8{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
ld1b {za0h.b[w12, 15]}, p1/z, [x10, x13]
### op load [GOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldr d1, [x10, x11]
### op load [GOFFSET] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldr b1, [x10, x11]
### op load [GOFFSET] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldr b1, [x10, x11]
### op load [GOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldr h1, [x10, x11]
### op load [GOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldr s1, [x10, x11]
### op load [GOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldrh w10, [x11, x12]
### op load [GOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldr w10, [x11, x12]
### op load [GOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldr x10, [x11, x12]
### op load [GOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldrb w10, [x11, x12]
### op load [GOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldrh w10, [x11, x12]
### op load [GOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldr w10, [x11, x12]
### op load [GOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldr x10, [x11, x12]
### op load [GOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
ldrb w10, [x11, x12]
### op load [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE vidxreg:REGISTER:VEC:SINT64 ioffset:IMMEDIATE:-:- {it:INT64}
ld1d {z1.d}, p1/z, [z2.d, #0]
### op load [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE vidxreg:REGISTER:VEC:SINT64 ioffset:IMMEDIATE:-:- {it:INT64} @far
ld1d {z1.d}, p1/z, [z2.d, #248]
### op load [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE vidxreg:REGISTER:VEC:SINT32 ioffset:IMMEDIATE:-:- {it:INT32}
ld1w {z1.s}, p1/z, [z2.s, #0]
### op load [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE vidxreg:REGISTER:VEC:SINT32 ioffset:IMMEDIATE:-:- {it:INT32} @far
ld1w {z1.s}, p1/z, [z2.s, #124]
### op load [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 vidxreg:REGISTER:VEC:SINT32 ioffset:IMMEDIATE:-:- {it:INT32}
ld1w {z1.s}, p1/z, [z2.s, #0]
### op load [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 vidxreg:REGISTER:VEC:SINT32 ioffset:IMMEDIATE:-:- {it:INT32} @far
ld1w {z1.s}, p1/z, [z2.s, #124]
### op load [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 vidxreg:REGISTER:VEC:SINT64 ioffset:IMMEDIATE:-:- {it:INT64}
ld1d {z1.d}, p1/z, [z2.d, #0]
### op load [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 vidxreg:REGISTER:VEC:SINT64 ioffset:IMMEDIATE:-:- {it:INT64} @far
ld1d {z1.d}, p1/z, [z2.d, #248]
### op load [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 vidxreg:REGISTER:VEC:SINT32 ioffset:IMMEDIATE:-:- {it:INT32}
ld1w {z1.s}, p1/z, [z2.s, #0]
### op load [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 vidxreg:REGISTER:VEC:SINT32 ioffset:IMMEDIATE:-:- {it:INT32} @far
ld1w {z1.s}, p1/z, [z2.s, #124]
### op load [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 vidxreg:REGISTER:VEC:SINT64 ioffset:IMMEDIATE:-:- {it:INT64}
ld1d {z1.d}, p1/z, [z2.d, #0]
### op load [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 vidxreg:REGISTER:VEC:SINT64 ioffset:IMMEDIATE:-:- {it:INT64} @far
ld1d {z1.d}, p1/z, [z2.d, #248]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:BF16{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- {adreg_blocksize:8}
ld1rqh {z1.h}, p1/z, [x10, #-128]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:BF16{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- {adreg_blocksize:8} @far
ld1rqh {z1.h}, p1/z, [x10, #112]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:BF16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:-
ld1rh {z1.h}, p1/z, [x10, #0]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:BF16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 ioffset:IMMEDIATE:-:- @far
ld1rh {z1.h}, p1/z, [x10, #126]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:DOUBLE{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- {adreg_blocksize:2}
ld1rqd {z1.d}, p1/z, [x10, #-128]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:DOUBLE{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- {adreg_blocksize:2} @far
ld1rqd {z1.d}, p1/z, [x10, #112]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:-
ld1rd {z1.d}, p1/z, [x10, #0]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE ioffset:IMMEDIATE:-:- @far
ld1rd {z1.d}, p1/z, [x10, #504]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:FP8E4M3{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 ioffset:IMMEDIATE:-:- {adreg_blocksize:16}
ld1rqb {z1.b}, p1/z, [x10, #-128]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:FP8E4M3{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 ioffset:IMMEDIATE:-:- {adreg_blocksize:16} @far
ld1rqb {z1.b}, p1/z, [x10, #112]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:FP8E4M3{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 ioffset:IMMEDIATE:-:-
ld1rb {z1.b}, p1/z, [x10, #0]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:FP8E4M3{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 ioffset:IMMEDIATE:-:- @far
ld1rb {z1.b}, p1/z, [x10, #63]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:FP8E5M2{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 ioffset:IMMEDIATE:-:- {adreg_blocksize:16}
ld1rqb {z1.b}, p1/z, [x10, #-128]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:FP8E5M2{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 ioffset:IMMEDIATE:-:- {adreg_blocksize:16} @far
ld1rqb {z1.b}, p1/z, [x10, #112]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:FP8E5M2{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 ioffset:IMMEDIATE:-:-
ld1rb {z1.b}, p1/z, [x10, #0]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:FP8E5M2{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 ioffset:IMMEDIATE:-:- @far
ld1rb {z1.b}, p1/z, [x10, #63]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:HALF{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- {adreg_blocksize:8}
ld1rqh {z1.h}, p1/z, [x10, #-128]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:HALF{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- {adreg_blocksize:8} @far
ld1rqh {z1.h}, p1/z, [x10, #112]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:HALF{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:-
ld1rh {z1.h}, p1/z, [x10, #0]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:HALF{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF ioffset:IMMEDIATE:-:- @far
ld1rh {z1.h}, p1/z, [x10, #126]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINGLE{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- {adreg_blocksize:4}
ld1rqw {z1.s}, p1/z, [x10, #-128]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINGLE{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- {adreg_blocksize:4} @far
ld1rqw {z1.s}, p1/z, [x10, #112]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:-
ld1rw {z1.s}, p1/z, [x10, #0]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE ioffset:IMMEDIATE:-:- @far
ld1rw {z1.s}, p1/z, [x10, #252]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT16{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- {adreg_blocksize:8}
ld1rqh {z1.h}, p1/z, [x10, #-128]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT16{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- {adreg_blocksize:8} @far
ld1rqh {z1.h}, p1/z, [x10, #112]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:-
ld1rh {z1.h}, p1/z, [x10, #0]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 ioffset:IMMEDIATE:-:- @far
ld1rh {z1.h}, p1/z, [x10, #126]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT32{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- {adreg_blocksize:4}
ld1rqw {z1.s}, p1/z, [x10, #-128]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT32{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- {adreg_blocksize:4} @far
ld1rqw {z1.s}, p1/z, [x10, #112]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:-
ld1rw {z1.s}, p1/z, [x10, #0]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 ioffset:IMMEDIATE:-:- @far
ld1rw {z1.s}, p1/z, [x10, #252]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT64{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- {adreg_blocksize:2}
ld1rqd {z1.d}, p1/z, [x10, #-128]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT64{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- {adreg_blocksize:2} @far
ld1rqd {z1.d}, p1/z, [x10, #112]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:-
ld1rd {z1.d}, p1/z, [x10, #0]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 ioffset:IMMEDIATE:-:- @far
ld1rd {z1.d}, p1/z, [x10, #504]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT8{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- {adreg_blocksize:16}
ld1rqb {z1.b}, p1/z, [x10, #-128]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT8{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- {adreg_blocksize:16} @far
ld1rqb {z1.b}, p1/z, [x10, #112]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT8{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:-
ld1rb {z1.b}, p1/z, [x10, #0]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:SINT8{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 ioffset:IMMEDIATE:-:- @far
ld1rb {z1.b}, p1/z, [x10, #63]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT16{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- {adreg_blocksize:8}
ld1rqh {z1.h}, p1/z, [x10, #-128]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT16{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- {adreg_blocksize:8} @far
ld1rqh {z1.h}, p1/z, [x10, #112]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:-
ld1rh {z1.h}, p1/z, [x10, #0]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 ioffset:IMMEDIATE:-:- @far
ld1rh {z1.h}, p1/z, [x10, #126]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT32{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- {adreg_blocksize:4}
ld1rqw {z1.s}, p1/z, [x10, #-128]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT32{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- {adreg_blocksize:4} @far
ld1rqw {z1.s}, p1/z, [x10, #112]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:-
ld1rw {z1.s}, p1/z, [x10, #0]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 ioffset:IMMEDIATE:-:- @far
ld1rw {z1.s}, p1/z, [x10, #252]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT64{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- {adreg_blocksize:2}
ld1rqd {z1.d}, p1/z, [x10, #-128]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT64{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- {adreg_blocksize:2} @far
ld1rqd {z1.d}, p1/z, [x10, #112]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:-
ld1rd {z1.d}, p1/z, [x10, #0]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 ioffset:IMMEDIATE:-:- @far
ld1rd {z1.d}, p1/z, [x10, #504]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT8{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- {adreg_blocksize:16}
ld1rqb {z1.b}, p1/z, [x10, #-128]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT8{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- {adreg_blocksize:16} @far
ld1rqb {z1.b}, p1/z, [x10, #112]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT8{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:-
ld1rb {z1.b}, p1/z, [x10, #0]
### op load [IOFFSET,MASK] adreg:REGISTER:VEC:UINT8{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 ioffset:IMMEDIATE:-:- @far
ld1rb {z1.b}, p1/z, [x10, #63]
### op load [IOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldr d1, [x10]
### op load [IOFFSET] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldr b1, [x10]
### op load [IOFFSET] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldr b1, [x10]
### op load [IOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldr h1, [x10]
### op load [IOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldr s1, [x10]
### op load [IOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldrh w10, [x11]
### op load [IOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldr w10, [x11]
### op load [IOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldr x10, [x11]
### op load [IOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldrb w10, [x11]
### op load [IOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldrh w10, [x11]
### op load [IOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldr w10, [x11]
### op load [IOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldr x10, [x11]
### op load [IOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
ldrb w10, [x11]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 ddreg:REGISTER:VEC:BF16 voffset:IMMEDIATE:-:- {nvectors:4}
ldnt1h {z1.h, z5.h, z9.h, z13.h}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 ddreg:REGISTER:VEC:BF16 voffset:IMMEDIATE:-:- {nvectors:4} @far
ldnt1h {z1.h, z5.h, z9.h, z13.h}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 voffset:IMMEDIATE:-:- {nvectors:2}
ldnt1h {z1.h, z9.h}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 voffset:IMMEDIATE:-:- {nvectors:2} @far
ldnt1h {z1.h, z9.h}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE voffset:IMMEDIATE:-:- {nvectors:4}
ldnt1d {z1.d, z5.d, z9.d, z13.d}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE voffset:IMMEDIATE:-:- {nvectors:4} @far
ldnt1d {z1.d, z5.d, z9.d, z13.d}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE voffset:IMMEDIATE:-:- {nvectors:2}
ldnt1d {z1.d, z9.d}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE voffset:IMMEDIATE:-:- {nvectors:2} @far
ldnt1d {z1.d, z9.d}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 voffset:IMMEDIATE:-:- {nvectors:4}
ldnt1b {z1.b, z5.b, z9.b, z13.b}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 voffset:IMMEDIATE:-:- {nvectors:4} @far
ldnt1b {z1.b, z5.b, z9.b, z13.b}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 voffset:IMMEDIATE:-:- {nvectors:2}
ldnt1b {z1.b, z9.b}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 voffset:IMMEDIATE:-:- {nvectors:2} @far
ldnt1b {z1.b, z9.b}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 voffset:IMMEDIATE:-:- {nvectors:4}
ldnt1b {z1.b, z5.b, z9.b, z13.b}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 voffset:IMMEDIATE:-:- {nvectors:4} @far
ldnt1b {z1.b, z5.b, z9.b, z13.b}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 voffset:IMMEDIATE:-:- {nvectors:2}
ldnt1b {z1.b, z9.b}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 voffset:IMMEDIATE:-:- {nvectors:2} @far
ldnt1b {z1.b, z9.b}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF voffset:IMMEDIATE:-:- {nvectors:4}
ldnt1h {z1.h, z5.h, z9.h, z13.h}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF voffset:IMMEDIATE:-:- {nvectors:4} @far
ldnt1h {z1.h, z5.h, z9.h, z13.h}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF voffset:IMMEDIATE:-:- {nvectors:2}
ldnt1h {z1.h, z9.h}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF voffset:IMMEDIATE:-:- {nvectors:2} @far
ldnt1h {z1.h, z9.h}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE voffset:IMMEDIATE:-:- {nvectors:4}
ldnt1w {z1.s, z5.s, z9.s, z13.s}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE voffset:IMMEDIATE:-:- {nvectors:4} @far
ldnt1w {z1.s, z5.s, z9.s, z13.s}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE voffset:IMMEDIATE:-:- {nvectors:2}
ldnt1w {z1.s, z9.s}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE voffset:IMMEDIATE:-:- {nvectors:2} @far
ldnt1w {z1.s, z9.s}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 voffset:IMMEDIATE:-:- {nvectors:4}
ldnt1h {z1.h, z5.h, z9.h, z13.h}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 voffset:IMMEDIATE:-:- {nvectors:4} @far
ldnt1h {z1.h, z5.h, z9.h, z13.h}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 voffset:IMMEDIATE:-:- {nvectors:2}
ldnt1h {z1.h, z9.h}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 voffset:IMMEDIATE:-:- {nvectors:2} @far
ldnt1h {z1.h, z9.h}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 voffset:IMMEDIATE:-:- {nvectors:4}
ldnt1w {z1.s, z5.s, z9.s, z13.s}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 voffset:IMMEDIATE:-:- {nvectors:4} @far
ldnt1w {z1.s, z5.s, z9.s, z13.s}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 voffset:IMMEDIATE:-:- {nvectors:2}
ldnt1w {z1.s, z9.s}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 voffset:IMMEDIATE:-:- {nvectors:2} @far
ldnt1w {z1.s, z9.s}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 voffset:IMMEDIATE:-:- {nvectors:4}
ldnt1d {z1.d, z5.d, z9.d, z13.d}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 voffset:IMMEDIATE:-:- {nvectors:4} @far
ldnt1d {z1.d, z5.d, z9.d, z13.d}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 voffset:IMMEDIATE:-:- {nvectors:2}
ldnt1d {z1.d, z9.d}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 voffset:IMMEDIATE:-:- {nvectors:2} @far
ldnt1d {z1.d, z9.d}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 voffset:IMMEDIATE:-:- {nvectors:4}
ldnt1b {z1.b, z5.b, z9.b, z13.b}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 voffset:IMMEDIATE:-:- {nvectors:4} @far
ldnt1b {z1.b, z5.b, z9.b, z13.b}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 voffset:IMMEDIATE:-:- {nvectors:2}
ldnt1b {z1.b, z9.b}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 voffset:IMMEDIATE:-:- {nvectors:2} @far
ldnt1b {z1.b, z9.b}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 voffset:IMMEDIATE:-:- {nvectors:4}
ldnt1h {z1.h, z5.h, z9.h, z13.h}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 voffset:IMMEDIATE:-:- {nvectors:4} @far
ldnt1h {z1.h, z5.h, z9.h, z13.h}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 voffset:IMMEDIATE:-:- {nvectors:2}
ldnt1h {z1.h, z9.h}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 voffset:IMMEDIATE:-:- {nvectors:2} @far
ldnt1h {z1.h, z9.h}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 voffset:IMMEDIATE:-:- {nvectors:4}
ldnt1w {z1.s, z5.s, z9.s, z13.s}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 voffset:IMMEDIATE:-:- {nvectors:4} @far
ldnt1w {z1.s, z5.s, z9.s, z13.s}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 voffset:IMMEDIATE:-:- {nvectors:2}
ldnt1w {z1.s, z9.s}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 voffset:IMMEDIATE:-:- {nvectors:2} @far
ldnt1w {z1.s, z9.s}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 voffset:IMMEDIATE:-:- {nvectors:4}
ldnt1d {z1.d, z5.d, z9.d, z13.d}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 voffset:IMMEDIATE:-:- {nvectors:4} @far
ldnt1d {z1.d, z5.d, z9.d, z13.d}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 voffset:IMMEDIATE:-:- {nvectors:2}
ldnt1d {z1.d, z9.d}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 voffset:IMMEDIATE:-:- {nvectors:2} @far
ldnt1d {z1.d, z9.d}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 voffset:IMMEDIATE:-:- {nvectors:4}
ldnt1b {z1.b, z5.b, z9.b, z13.b}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 voffset:IMMEDIATE:-:- {nvectors:4} @far
ldnt1b {z1.b, z5.b, z9.b, z13.b}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 voffset:IMMEDIATE:-:- {nvectors:2}
ldnt1b {z1.b, z9.b}, p8/z, [x10, #-8, MUL VL]
### op load [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 voffset:IMMEDIATE:-:- {nvectors:2} @far
ldnt1b {z1.b, z9.b}, p8/z, [x10, #7, MUL VL]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 ddreg:REGISTER:VEC:BF16 {nvectors:4}
ldnt1h {z1.h, z5.h, z9.h, z13.h}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 {nvectors:2}
ldnt1h {z1.h, z9.h}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE {nvectors:4}
ldnt1d {z1.d, z5.d, z9.d, z13.d}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE {nvectors:2}
ldnt1d {z1.d, z9.d}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 {nvectors:4}
ldnt1b {z1.b, z5.b, z9.b, z13.b}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 {nvectors:2}
ldnt1b {z1.b, z9.b}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 {nvectors:4}
ldnt1b {z1.b, z5.b, z9.b, z13.b}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 {nvectors:2}
ldnt1b {z1.b, z9.b}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF {nvectors:4}
ldnt1h {z1.h, z5.h, z9.h, z13.h}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF {nvectors:2}
ldnt1h {z1.h, z9.h}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE {nvectors:4}
ldnt1w {z1.s, z5.s, z9.s, z13.s}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE {nvectors:2}
ldnt1w {z1.s, z9.s}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 {nvectors:4}
ldnt1h {z1.h, z5.h, z9.h, z13.h}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 {nvectors:2}
ldnt1h {z1.h, z9.h}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 {nvectors:4}
ldnt1w {z1.s, z5.s, z9.s, z13.s}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 {nvectors:2}
ldnt1w {z1.s, z9.s}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 {nvectors:4}
ldnt1d {z1.d, z5.d, z9.d, z13.d}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 {nvectors:2}
ldnt1d {z1.d, z9.d}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 {nvectors:4}
ldnt1b {z1.b, z5.b, z9.b, z13.b}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 {nvectors:2}
ldnt1b {z1.b, z9.b}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 {nvectors:4}
ldnt1h {z1.h, z5.h, z9.h, z13.h}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 {nvectors:2}
ldnt1h {z1.h, z9.h}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 {nvectors:4}
ldnt1w {z1.s, z5.s, z9.s, z13.s}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 {nvectors:2}
ldnt1w {z1.s, z9.s}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 {nvectors:4}
ldnt1d {z1.d, z5.d, z9.d, z13.d}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 {nvectors:2}
ldnt1d {z1.d, z9.d}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 {nvectors:4}
ldnt1b {z1.b, z5.b, z9.b, z13.b}, p8/z, [x10]
### op load [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 {nvectors:2}
ldnt1b {z1.b, z9.b}, p8/z, [x10]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 ddreg:REGISTER:VEC:BF16 voffset:IMMEDIATE:-:- {nstructs:4}
ld4h {z1.h, z2.h, z3.h, z4.h}, p1/z, [x10, #-32, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 ddreg:REGISTER:VEC:BF16 voffset:IMMEDIATE:-:- {nstructs:4} @far
ld4h {z1.h, z2.h, z3.h, z4.h}, p1/z, [x10, #28, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 voffset:IMMEDIATE:-:- {nstructs:3}
ld3h {z1.h, z2.h, z3.h}, p1/z, [x10, #-24, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 voffset:IMMEDIATE:-:- {nstructs:3} @far
ld3h {z1.h, z2.h, z3.h}, p1/z, [x10, #21, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 voffset:IMMEDIATE:-:- {nstructs:2}
ld2h {z1.h, z2.h}, p1/z, [x10, #-16, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 voffset:IMMEDIATE:-:- {nstructs:2} @far
ld2h {z1.h, z2.h}, p1/z, [x10, #14, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE voffset:IMMEDIATE:-:- {nstructs:4}
ld4d {z1.d, z2.d, z3.d, z4.d}, p1/z, [x10, #-32, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE voffset:IMMEDIATE:-:- {nstructs:4} @far
ld4d {z1.d, z2.d, z3.d, z4.d}, p1/z, [x10, #28, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE voffset:IMMEDIATE:-:- {nstructs:3}
ld3d {z1.d, z2.d, z3.d}, p1/z, [x10, #-24, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE voffset:IMMEDIATE:-:- {nstructs:3} @far
ld3d {z1.d, z2.d, z3.d}, p1/z, [x10, #21, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE voffset:IMMEDIATE:-:- {nstructs:2}
ld2d {z1.d, z2.d}, p1/z, [x10, #-16, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE voffset:IMMEDIATE:-:- {nstructs:2} @far
ld2d {z1.d, z2.d}, p1/z, [x10, #14, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 voffset:IMMEDIATE:-:- {nstructs:4}
ld4b {z1.b, z2.b, z3.b, z4.b}, p1/z, [x10, #-32, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 voffset:IMMEDIATE:-:- {nstructs:4} @far
ld4b {z1.b, z2.b, z3.b, z4.b}, p1/z, [x10, #28, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 voffset:IMMEDIATE:-:- {nstructs:3}
ld3b {z1.b, z2.b, z3.b}, p1/z, [x10, #-24, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 voffset:IMMEDIATE:-:- {nstructs:3} @far
ld3b {z1.b, z2.b, z3.b}, p1/z, [x10, #21, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 voffset:IMMEDIATE:-:- {nstructs:2}
ld2b {z1.b, z2.b}, p1/z, [x10, #-16, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 voffset:IMMEDIATE:-:- {nstructs:2} @far
ld2b {z1.b, z2.b}, p1/z, [x10, #14, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 voffset:IMMEDIATE:-:- {nstructs:4}
ld4b {z1.b, z2.b, z3.b, z4.b}, p1/z, [x10, #-32, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 voffset:IMMEDIATE:-:- {nstructs:4} @far
ld4b {z1.b, z2.b, z3.b, z4.b}, p1/z, [x10, #28, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 voffset:IMMEDIATE:-:- {nstructs:3}
ld3b {z1.b, z2.b, z3.b}, p1/z, [x10, #-24, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 voffset:IMMEDIATE:-:- {nstructs:3} @far
ld3b {z1.b, z2.b, z3.b}, p1/z, [x10, #21, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 voffset:IMMEDIATE:-:- {nstructs:2}
ld2b {z1.b, z2.b}, p1/z, [x10, #-16, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 voffset:IMMEDIATE:-:- {nstructs:2} @far
ld2b {z1.b, z2.b}, p1/z, [x10, #14, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF voffset:IMMEDIATE:-:- {nstructs:4}
ld4h {z1.h, z2.h, z3.h, z4.h}, p1/z, [x10, #-32, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF voffset:IMMEDIATE:-:- {nstructs:4} @far
ld4h {z1.h, z2.h, z3.h, z4.h}, p1/z, [x10, #28, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF voffset:IMMEDIATE:-:- {nstructs:3}
ld3h {z1.h, z2.h, z3.h}, p1/z, [x10, #-24, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF voffset:IMMEDIATE:-:- {nstructs:3} @far
ld3h {z1.h, z2.h, z3.h}, p1/z, [x10, #21, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF voffset:IMMEDIATE:-:- {nstructs:2}
ld2h {z1.h, z2.h}, p1/z, [x10, #-16, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF voffset:IMMEDIATE:-:- {nstructs:2} @far
ld2h {z1.h, z2.h}, p1/z, [x10, #14, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE voffset:IMMEDIATE:-:- {nstructs:4}
ld4w {z1.s, z2.s, z3.s, z4.s}, p1/z, [x10, #-32, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE voffset:IMMEDIATE:-:- {nstructs:4} @far
ld4w {z1.s, z2.s, z3.s, z4.s}, p1/z, [x10, #28, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE voffset:IMMEDIATE:-:- {nstructs:3}
ld3w {z1.s, z2.s, z3.s}, p1/z, [x10, #-24, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE voffset:IMMEDIATE:-:- {nstructs:3} @far
ld3w {z1.s, z2.s, z3.s}, p1/z, [x10, #21, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE voffset:IMMEDIATE:-:- {nstructs:2}
ld2w {z1.s, z2.s}, p1/z, [x10, #-16, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE voffset:IMMEDIATE:-:- {nstructs:2} @far
ld2w {z1.s, z2.s}, p1/z, [x10, #14, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 voffset:IMMEDIATE:-:- {nstructs:4}
ld4h {z1.h, z2.h, z3.h, z4.h}, p1/z, [x10, #-32, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 voffset:IMMEDIATE:-:- {nstructs:4} @far
ld4h {z1.h, z2.h, z3.h, z4.h}, p1/z, [x10, #28, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 voffset:IMMEDIATE:-:- {nstructs:3}
ld3h {z1.h, z2.h, z3.h}, p1/z, [x10, #-24, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 voffset:IMMEDIATE:-:- {nstructs:3} @far
ld3h {z1.h, z2.h, z3.h}, p1/z, [x10, #21, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 voffset:IMMEDIATE:-:- {nstructs:2}
ld2h {z1.h, z2.h}, p1/z, [x10, #-16, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 voffset:IMMEDIATE:-:- {nstructs:2} @far
ld2h {z1.h, z2.h}, p1/z, [x10, #14, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 voffset:IMMEDIATE:-:- {nstructs:4}
ld4w {z1.s, z2.s, z3.s, z4.s}, p1/z, [x10, #-32, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 voffset:IMMEDIATE:-:- {nstructs:4} @far
ld4w {z1.s, z2.s, z3.s, z4.s}, p1/z, [x10, #28, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 voffset:IMMEDIATE:-:- {nstructs:3}
ld3w {z1.s, z2.s, z3.s}, p1/z, [x10, #-24, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 voffset:IMMEDIATE:-:- {nstructs:3} @far
ld3w {z1.s, z2.s, z3.s}, p1/z, [x10, #21, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 voffset:IMMEDIATE:-:- {nstructs:2}
ld2w {z1.s, z2.s}, p1/z, [x10, #-16, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 voffset:IMMEDIATE:-:- {nstructs:2} @far
ld2w {z1.s, z2.s}, p1/z, [x10, #14, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 voffset:IMMEDIATE:-:- {nstructs:4}
ld4d {z1.d, z2.d, z3.d, z4.d}, p1/z, [x10, #-32, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 voffset:IMMEDIATE:-:- {nstructs:4} @far
ld4d {z1.d, z2.d, z3.d, z4.d}, p1/z, [x10, #28, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 voffset:IMMEDIATE:-:- {nstructs:3}
ld3d {z1.d, z2.d, z3.d}, p1/z, [x10, #-24, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 voffset:IMMEDIATE:-:- {nstructs:3} @far
ld3d {z1.d, z2.d, z3.d}, p1/z, [x10, #21, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 voffset:IMMEDIATE:-:- {nstructs:2}
ld2d {z1.d, z2.d}, p1/z, [x10, #-16, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 voffset:IMMEDIATE:-:- {nstructs:2} @far
ld2d {z1.d, z2.d}, p1/z, [x10, #14, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 voffset:IMMEDIATE:-:- {nstructs:4}
ld4b {z1.b, z2.b, z3.b, z4.b}, p1/z, [x10, #-32, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 voffset:IMMEDIATE:-:- {nstructs:4} @far
ld4b {z1.b, z2.b, z3.b, z4.b}, p1/z, [x10, #28, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 voffset:IMMEDIATE:-:- {nstructs:3}
ld3b {z1.b, z2.b, z3.b}, p1/z, [x10, #-24, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 voffset:IMMEDIATE:-:- {nstructs:3} @far
ld3b {z1.b, z2.b, z3.b}, p1/z, [x10, #21, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 voffset:IMMEDIATE:-:- {nstructs:2}
ld2b {z1.b, z2.b}, p1/z, [x10, #-16, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 voffset:IMMEDIATE:-:- {nstructs:2} @far
ld2b {z1.b, z2.b}, p1/z, [x10, #14, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 voffset:IMMEDIATE:-:- {nstructs:4}
ld4h {z1.h, z2.h, z3.h, z4.h}, p1/z, [x10, #-32, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 voffset:IMMEDIATE:-:- {nstructs:4} @far
ld4h {z1.h, z2.h, z3.h, z4.h}, p1/z, [x10, #28, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 voffset:IMMEDIATE:-:- {nstructs:3}
ld3h {z1.h, z2.h, z3.h}, p1/z, [x10, #-24, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 voffset:IMMEDIATE:-:- {nstructs:3} @far
ld3h {z1.h, z2.h, z3.h}, p1/z, [x10, #21, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 voffset:IMMEDIATE:-:- {nstructs:2}
ld2h {z1.h, z2.h}, p1/z, [x10, #-16, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 voffset:IMMEDIATE:-:- {nstructs:2} @far
ld2h {z1.h, z2.h}, p1/z, [x10, #14, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 voffset:IMMEDIATE:-:- {nstructs:4}
ld4w {z1.s, z2.s, z3.s, z4.s}, p1/z, [x10, #-32, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 voffset:IMMEDIATE:-:- {nstructs:4} @far
ld4w {z1.s, z2.s, z3.s, z4.s}, p1/z, [x10, #28, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 voffset:IMMEDIATE:-:- {nstructs:3}
ld3w {z1.s, z2.s, z3.s}, p1/z, [x10, #-24, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 voffset:IMMEDIATE:-:- {nstructs:3} @far
ld3w {z1.s, z2.s, z3.s}, p1/z, [x10, #21, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 voffset:IMMEDIATE:-:- {nstructs:2}
ld2w {z1.s, z2.s}, p1/z, [x10, #-16, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 voffset:IMMEDIATE:-:- {nstructs:2} @far
ld2w {z1.s, z2.s}, p1/z, [x10, #14, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 voffset:IMMEDIATE:-:- {nstructs:4}
ld4d {z1.d, z2.d, z3.d, z4.d}, p1/z, [x10, #-32, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 voffset:IMMEDIATE:-:- {nstructs:4} @far
ld4d {z1.d, z2.d, z3.d, z4.d}, p1/z, [x10, #28, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 voffset:IMMEDIATE:-:- {nstructs:3}
ld3d {z1.d, z2.d, z3.d}, p1/z, [x10, #-24, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 voffset:IMMEDIATE:-:- {nstructs:3} @far
ld3d {z1.d, z2.d, z3.d}, p1/z, [x10, #21, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 voffset:IMMEDIATE:-:- {nstructs:2}
ld2d {z1.d, z2.d}, p1/z, [x10, #-16, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 voffset:IMMEDIATE:-:- {nstructs:2} @far
ld2d {z1.d, z2.d}, p1/z, [x10, #14, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 voffset:IMMEDIATE:-:- {nstructs:4}
ld4b {z1.b, z2.b, z3.b, z4.b}, p1/z, [x10, #-32, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 voffset:IMMEDIATE:-:- {nstructs:4} @far
ld4b {z1.b, z2.b, z3.b, z4.b}, p1/z, [x10, #28, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 voffset:IMMEDIATE:-:- {nstructs:3}
ld3b {z1.b, z2.b, z3.b}, p1/z, [x10, #-24, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 voffset:IMMEDIATE:-:- {nstructs:3} @far
ld3b {z1.b, z2.b, z3.b}, p1/z, [x10, #21, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 voffset:IMMEDIATE:-:- {nstructs:2}
ld2b {z1.b, z2.b}, p1/z, [x10, #-16, MUL VL]
### op load [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 voffset:IMMEDIATE:-:- {nstructs:2} @far
ld2b {z1.b, z2.b}, p1/z, [x10, #14, MUL VL]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 ddreg:REGISTER:VEC:BF16 {nstructs:4}
ld4h {z1.h, z2.h, z3.h, z4.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 {nstructs:3}
ld3h {z1.h, z2.h, z3.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 {nstructs:2}
ld2h {z1.h, z2.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:BF16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16{BCAST} cdreg:REGISTER:VEC:BF16{BCAST} ddreg:REGISTER:VEC:BF16{BCAST} {nstructs:4}
ld4rh {z1.h, z2.h, z3.h, z4.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:BF16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16{BCAST} cdreg:REGISTER:VEC:BF16{BCAST} {nstructs:3}
ld3rh {z1.h, z2.h, z3.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:BF16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16{BCAST} {nstructs:2}
ld2rh {z1.h, z2.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE {nstructs:4}
ld4d {z1.d, z2.d, z3.d, z4.d}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE {nstructs:3}
ld3d {z1.d, z2.d, z3.d}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE {nstructs:2}
ld2d {z1.d, z2.d}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE{BCAST} cdreg:REGISTER:VEC:DOUBLE{BCAST} ddreg:REGISTER:VEC:DOUBLE{BCAST} {nstructs:4}
ld4rd {z1.d, z2.d, z3.d, z4.d}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE{BCAST} cdreg:REGISTER:VEC:DOUBLE{BCAST} {nstructs:3}
ld3rd {z1.d, z2.d, z3.d}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE{BCAST} {nstructs:2}
ld2rd {z1.d, z2.d}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 {nstructs:4}
ld4b {z1.b, z2.b, z3.b, z4.b}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 {nstructs:3}
ld3b {z1.b, z2.b, z3.b}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 {nstructs:2}
ld2b {z1.b, z2.b}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:FP8E4M3{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BCAST} cdreg:REGISTER:VEC:FP8E4M3{BCAST} ddreg:REGISTER:VEC:FP8E4M3{BCAST} {nstructs:4}
ld4rb {z1.b, z2.b, z3.b, z4.b}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:FP8E4M3{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BCAST} cdreg:REGISTER:VEC:FP8E4M3{BCAST} {nstructs:3}
ld3rb {z1.b, z2.b, z3.b}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:FP8E4M3{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BCAST} {nstructs:2}
ld2rb {z1.b, z2.b}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 {nstructs:4}
ld4b {z1.b, z2.b, z3.b, z4.b}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 {nstructs:3}
ld3b {z1.b, z2.b, z3.b}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 {nstructs:2}
ld2b {z1.b, z2.b}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:FP8E5M2{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BCAST} cdreg:REGISTER:VEC:FP8E5M2{BCAST} ddreg:REGISTER:VEC:FP8E5M2{BCAST} {nstructs:4}
ld4rb {z1.b, z2.b, z3.b, z4.b}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:FP8E5M2{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BCAST} cdreg:REGISTER:VEC:FP8E5M2{BCAST} {nstructs:3}
ld3rb {z1.b, z2.b, z3.b}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:FP8E5M2{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BCAST} {nstructs:2}
ld2rb {z1.b, z2.b}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF {nstructs:4}
ld4h {z1.h, z2.h, z3.h, z4.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF {nstructs:3}
ld3h {z1.h, z2.h, z3.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF {nstructs:2}
ld2h {z1.h, z2.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:HALF{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF{BCAST} cdreg:REGISTER:VEC:HALF{BCAST} ddreg:REGISTER:VEC:HALF{BCAST} {nstructs:4}
ld4rh {z1.h, z2.h, z3.h, z4.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:HALF{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF{BCAST} cdreg:REGISTER:VEC:HALF{BCAST} {nstructs:3}
ld3rh {z1.h, z2.h, z3.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:HALF{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF{BCAST} {nstructs:2}
ld2rh {z1.h, z2.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE {nstructs:4}
ld4w {z1.s, z2.s, z3.s, z4.s}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {nstructs:3}
ld3w {z1.s, z2.s, z3.s}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE {nstructs:2}
ld2w {z1.s, z2.s}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE{BCAST} cdreg:REGISTER:VEC:SINGLE{BCAST} ddreg:REGISTER:VEC:SINGLE{BCAST} {nstructs:4}
ld4rw {z1.s, z2.s, z3.s, z4.s}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE{BCAST} cdreg:REGISTER:VEC:SINGLE{BCAST} {nstructs:3}
ld3rw {z1.s, z2.s, z3.s}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE{BCAST} {nstructs:2}
ld2rw {z1.s, z2.s}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 {nstructs:4}
ld4h {z1.h, z2.h, z3.h, z4.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 {nstructs:3}
ld3h {z1.h, z2.h, z3.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 {nstructs:2}
ld2h {z1.h, z2.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16{BCAST} cdreg:REGISTER:VEC:SINT16{BCAST} ddreg:REGISTER:VEC:SINT16{BCAST} {nstructs:4}
ld4rh {z1.h, z2.h, z3.h, z4.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16{BCAST} cdreg:REGISTER:VEC:SINT16{BCAST} {nstructs:3}
ld3rh {z1.h, z2.h, z3.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16{BCAST} {nstructs:2}
ld2rh {z1.h, z2.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 {nstructs:4}
ld4w {z1.s, z2.s, z3.s, z4.s}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {nstructs:3}
ld3w {z1.s, z2.s, z3.s}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 {nstructs:2}
ld2w {z1.s, z2.s}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32{BCAST} cdreg:REGISTER:VEC:SINT32{BCAST} ddreg:REGISTER:VEC:SINT32{BCAST} {nstructs:4}
ld4rw {z1.s, z2.s, z3.s, z4.s}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32{BCAST} cdreg:REGISTER:VEC:SINT32{BCAST} {nstructs:3}
ld3rw {z1.s, z2.s, z3.s}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32{BCAST} {nstructs:2}
ld2rw {z1.s, z2.s}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 {nstructs:4}
ld4d {z1.d, z2.d, z3.d, z4.d}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 {nstructs:3}
ld3d {z1.d, z2.d, z3.d}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 {nstructs:2}
ld2d {z1.d, z2.d}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64{BCAST} cdreg:REGISTER:VEC:SINT64{BCAST} ddreg:REGISTER:VEC:SINT64{BCAST} {nstructs:4}
ld4rd {z1.d, z2.d, z3.d, z4.d}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64{BCAST} cdreg:REGISTER:VEC:SINT64{BCAST} {nstructs:3}
ld3rd {z1.d, z2.d, z3.d}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64{BCAST} {nstructs:2}
ld2rd {z1.d, z2.d}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 {nstructs:4}
ld4b {z1.b, z2.b, z3.b, z4.b}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {nstructs:3}
ld3b {z1.b, z2.b, z3.b}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 {nstructs:2}
ld2b {z1.b, z2.b}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT8{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8{BCAST} cdreg:REGISTER:VEC:SINT8{BCAST} ddreg:REGISTER:VEC:SINT8{BCAST} {nstructs:4}
ld4rb {z1.b, z2.b, z3.b, z4.b}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT8{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8{BCAST} cdreg:REGISTER:VEC:SINT8{BCAST} {nstructs:3}
ld3rb {z1.b, z2.b, z3.b}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT8{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8{BCAST} {nstructs:2}
ld2rb {z1.b, z2.b}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 {nstructs:4}
ld4h {z1.h, z2.h, z3.h, z4.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 {nstructs:3}
ld3h {z1.h, z2.h, z3.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 {nstructs:2}
ld2h {z1.h, z2.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16{BCAST} cdreg:REGISTER:VEC:UINT16{BCAST} ddreg:REGISTER:VEC:UINT16{BCAST} {nstructs:4}
ld4rh {z1.h, z2.h, z3.h, z4.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16{BCAST} cdreg:REGISTER:VEC:UINT16{BCAST} {nstructs:3}
ld3rh {z1.h, z2.h, z3.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16{BCAST} {nstructs:2}
ld2rh {z1.h, z2.h}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 {nstructs:4}
ld4w {z1.s, z2.s, z3.s, z4.s}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {nstructs:3}
ld3w {z1.s, z2.s, z3.s}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 {nstructs:2}
ld2w {z1.s, z2.s}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32{BCAST} cdreg:REGISTER:VEC:UINT32{BCAST} ddreg:REGISTER:VEC:UINT32{BCAST} {nstructs:4}
ld4rw {z1.s, z2.s, z3.s, z4.s}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32{BCAST} cdreg:REGISTER:VEC:UINT32{BCAST} {nstructs:3}
ld3rw {z1.s, z2.s, z3.s}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32{BCAST} {nstructs:2}
ld2rw {z1.s, z2.s}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 {nstructs:4}
ld4d {z1.d, z2.d, z3.d, z4.d}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 {nstructs:3}
ld3d {z1.d, z2.d, z3.d}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 {nstructs:2}
ld2d {z1.d, z2.d}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64{BCAST} cdreg:REGISTER:VEC:UINT64{BCAST} ddreg:REGISTER:VEC:UINT64{BCAST} {nstructs:4}
ld4rd {z1.d, z2.d, z3.d, z4.d}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64{BCAST} cdreg:REGISTER:VEC:UINT64{BCAST} {nstructs:3}
ld3rd {z1.d, z2.d, z3.d}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64{BCAST} {nstructs:2}
ld2rd {z1.d, z2.d}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 {nstructs:4}
ld4b {z1.b, z2.b, z3.b, z4.b}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {nstructs:3}
ld3b {z1.b, z2.b, z3.b}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 {nstructs:2}
ld2b {z1.b, z2.b}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT8{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8{BCAST} cdreg:REGISTER:VEC:UINT8{BCAST} ddreg:REGISTER:VEC:UINT8{BCAST} {nstructs:4}
ld4rb {z1.b, z2.b, z3.b, z4.b}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT8{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8{BCAST} cdreg:REGISTER:VEC:UINT8{BCAST} {nstructs:3}
ld3rb {z1.b, z2.b, z3.b}, p1/z, [x10]
### op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT8{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8{BCAST} {nstructs:2}
ld2rb {z1.b, z2.b}, p1/z, [x10]
### op load [MASK,VINDEX] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE vidxreg:REGISTER:VEC:SINT32 {it:INT32}
ld1d {z1.d}, p1/z, [x10, z2.d, sxtw]
### op load [MASK,VINDEX] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE vidxreg:REGISTER:VEC:SINT64 {it:INT64}
ld1d {z1.d}, p1/z, [x10, z2.d]
### op load [MASK,VINDEX] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE vidxreg:REGISTER:VEC:SINT32 {it:INT32}
ld1w {z1.s}, p1/z, [x10, z2.s, sxtw]
### op load [MASK,VINDEX] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 vidxreg:REGISTER:VEC:SINT32 {it:INT32}
ld1w {z1.s}, p1/z, [x10, z2.s, sxtw]
### op load [MASK,VINDEX] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 vidxreg:REGISTER:VEC:SINT32 {it:INT32}
ld1d {z1.d}, p1/z, [x10, z2.d, sxtw]
### op load [MASK,VINDEX] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 vidxreg:REGISTER:VEC:SINT64 {it:INT64}
ld1d {z1.d}, p1/z, [x10, z2.d]
### op load [MASK,VINDEX] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 vidxreg:REGISTER:VEC:SINT32 {it:INT32}
ld1w {z1.s}, p1/z, [x10, z2.s, sxtw]
### op load [MASK,VINDEX] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 vidxreg:REGISTER:VEC:SINT32 {it:INT32}
ld1d {z1.d}, p1/z, [x10, z2.d, sxtw]
### op load [MASK,VINDEX] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 vidxreg:REGISTER:VEC:SINT64 {it:INT64}
ld1d {z1.d}, p1/z, [x10, z2.d]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 voffset:IMMEDIATE:-:-
ld1h {z1.h}, p1/z, [x10, #-8, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 voffset:IMMEDIATE:-:- @far
ld1h {z1.h}, p1/z, [x10, #7, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE voffset:IMMEDIATE:-:-
ld1d {z1.d}, p1/z, [x10, #-8, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE voffset:IMMEDIATE:-:- @far
ld1d {z1.d}, p1/z, [x10, #7, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 voffset:IMMEDIATE:-:-
ld1b {z1.b}, p1/z, [x10, #-8, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 voffset:IMMEDIATE:-:- @far
ld1b {z1.b}, p1/z, [x10, #7, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 voffset:IMMEDIATE:-:-
ld1b {z1.b}, p1/z, [x10, #-8, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 voffset:IMMEDIATE:-:- @far
ld1b {z1.b}, p1/z, [x10, #7, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF voffset:IMMEDIATE:-:-
ld1h {z1.h}, p1/z, [x10, #-8, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF voffset:IMMEDIATE:-:- @far
ld1h {z1.h}, p1/z, [x10, #7, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE voffset:IMMEDIATE:-:-
ld1w {z1.s}, p1/z, [x10, #-8, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE voffset:IMMEDIATE:-:- @far
ld1w {z1.s}, p1/z, [x10, #7, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 voffset:IMMEDIATE:-:-
ld1h {z1.h}, p1/z, [x10, #-8, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 voffset:IMMEDIATE:-:- @far
ld1h {z1.h}, p1/z, [x10, #7, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 voffset:IMMEDIATE:-:-
ld1w {z1.s}, p1/z, [x10, #-8, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 voffset:IMMEDIATE:-:- @far
ld1w {z1.s}, p1/z, [x10, #7, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 voffset:IMMEDIATE:-:-
ld1d {z1.d}, p1/z, [x10, #-8, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 voffset:IMMEDIATE:-:- @far
ld1d {z1.d}, p1/z, [x10, #7, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 voffset:IMMEDIATE:-:-
ld1b {z1.b}, p1/z, [x10, #-8, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 voffset:IMMEDIATE:-:- @far
ld1b {z1.b}, p1/z, [x10, #7, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 voffset:IMMEDIATE:-:-
ld1h {z1.h}, p1/z, [x10, #-8, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 voffset:IMMEDIATE:-:- @far
ld1h {z1.h}, p1/z, [x10, #7, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 voffset:IMMEDIATE:-:-
ld1w {z1.s}, p1/z, [x10, #-8, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 voffset:IMMEDIATE:-:- @far
ld1w {z1.s}, p1/z, [x10, #7, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 voffset:IMMEDIATE:-:-
ld1d {z1.d}, p1/z, [x10, #-8, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 voffset:IMMEDIATE:-:- @far
ld1d {z1.d}, p1/z, [x10, #7, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 voffset:IMMEDIATE:-:-
ld1b {z1.b}, p1/z, [x10, #-8, MUL VL]
### op load [MASK,VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 voffset:IMMEDIATE:-:- @far
ld1b {z1.b}, p1/z, [x10, #7, MUL VL]
### op load [MASK] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16
ld1h {z1.h}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:BF16{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 {adreg_blocksize:8}
ld1rqh {z1.h}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:BF16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16
ld1rh {z1.h}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE
ld1d {z1.d}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:DOUBLE{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE {adreg_blocksize:2}
ld1rqd {z1.d}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE
ld1rd {z1.d}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3
ld1b {z1.b}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:FP8E4M3{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 {adreg_blocksize:16}
ld1rqb {z1.b}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:FP8E4M3{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3
ld1rb {z1.b}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2
ld1b {z1.b}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:FP8E5M2{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 {adreg_blocksize:16}
ld1rqb {z1.b}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:FP8E5M2{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2
ld1rb {z1.b}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF
ld1h {z1.h}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:HALF{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF {adreg_blocksize:8}
ld1rqh {z1.h}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:HALF{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF
ld1rh {z1.h}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE
ld1w {z1.s}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:SINGLE{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE {adreg_blocksize:4}
ld1rqw {z1.s}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE
ld1rw {z1.s}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16
ld1h {z1.h}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:SINT16{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 {adreg_blocksize:8}
ld1rqh {z1.h}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:SINT16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16
ld1rh {z1.h}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32
ld1w {z1.s}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:SINT32{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 {adreg_blocksize:4}
ld1rqw {z1.s}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32
ld1rw {z1.s}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64
ld1d {z1.d}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:SINT64{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 {adreg_blocksize:2}
ld1rqd {z1.d}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64
ld1rd {z1.d}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8
ld1b {z1.b}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:SINT8{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 {adreg_blocksize:16}
ld1rqb {z1.b}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:SINT8{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8
ld1rb {z1.b}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16
ld1h {z1.h}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:UINT16{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 {adreg_blocksize:8}
ld1rqh {z1.h}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:UINT16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16
ld1rh {z1.h}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32
ld1w {z1.s}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:UINT32{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 {adreg_blocksize:4}
ld1rqw {z1.s}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32
ld1rw {z1.s}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64
ld1d {z1.d}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:UINT64{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 {adreg_blocksize:2}
ld1rqd {z1.d}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64
ld1rd {z1.d}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8
ld1b {z1.b}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:UINT8{BCAST,BLOCK} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 {adreg_blocksize:16}
ld1rqb {z1.b}, p1/z, [x10]
### op load [MASK] adreg:REGISTER:VEC:UINT8{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8
ld1rb {z1.b}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:TILE:BF16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
ld1h {za0v.h[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:TILE:BF16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
ld1h {za0v.h[w12, 7]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:TILE:BF16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
ld1h {za0h.h[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:TILE:BF16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
ld1h {za0h.h[w12, 7]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:TILE:DOUBLE{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
ld1d {za0v.d[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:TILE:DOUBLE{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
ld1d {za0v.d[w12, 1]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:TILE:DOUBLE{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
ld1d {za0h.d[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:TILE:DOUBLE{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
ld1d {za0h.d[w12, 1]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:TILE:FP8E4M3{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
ld1b {za0v.b[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:TILE:FP8E4M3{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
ld1b {za0v.b[w12, 15]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:TILE:FP8E4M3{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
ld1b {za0h.b[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:TILE:FP8E4M3{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
ld1b {za0h.b[w12, 15]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:TILE:FP8E5M2{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
ld1b {za0v.b[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:TILE:FP8E5M2{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
ld1b {za0v.b[w12, 15]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:TILE:FP8E5M2{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
ld1b {za0h.b[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:TILE:FP8E5M2{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
ld1b {za0h.b[w12, 15]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:TILE:HALF{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
ld1h {za0v.h[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:TILE:HALF{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
ld1h {za0v.h[w12, 7]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:TILE:HALF{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
ld1h {za0h.h[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:TILE:HALF{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
ld1h {za0h.h[w12, 7]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:TILE:SINGLE{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
ld1w {za0v.s[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:TILE:SINGLE{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
ld1w {za0v.s[w12, 3]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:TILE:SINGLE{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
ld1w {za0h.s[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:TILE:SINGLE{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
ld1w {za0h.s[w12, 3]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:TILE:SINT16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
ld1h {za0v.h[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:TILE:SINT16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
ld1h {za0v.h[w12, 7]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:TILE:SINT16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
ld1h {za0h.h[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:TILE:SINT16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
ld1h {za0h.h[w12, 7]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:TILE:SINT32{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
ld1w {za0v.s[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:TILE:SINT32{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
ld1w {za0v.s[w12, 3]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:TILE:SINT32{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
ld1w {za0h.s[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:TILE:SINT32{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
ld1w {za0h.s[w12, 3]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:TILE:SINT64{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
ld1d {za0v.d[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:TILE:SINT64{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
ld1d {za0v.d[w12, 1]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:TILE:SINT64{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
ld1d {za0h.d[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:TILE:SINT64{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
ld1d {za0h.d[w12, 1]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:TILE:SINT8{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
ld1b {za0v.b[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:TILE:SINT8{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
ld1b {za0v.b[w12, 15]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:TILE:SINT8{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
ld1b {za0h.b[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:TILE:SINT8{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
ld1b {za0h.b[w12, 15]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:TILE:UINT16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
ld1h {za0v.h[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:TILE:UINT16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
ld1h {za0v.h[w12, 7]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:TILE:UINT16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
ld1h {za0h.h[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:TILE:UINT16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
ld1h {za0h.h[w12, 7]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:TILE:UINT32{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
ld1w {za0v.s[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:TILE:UINT32{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
ld1w {za0v.s[w12, 3]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:TILE:UINT32{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
ld1w {za0h.s[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:TILE:UINT32{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
ld1w {za0h.s[w12, 3]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:TILE:UINT64{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
ld1d {za0v.d[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:TILE:UINT64{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
ld1d {za0v.d[w12, 1]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:TILE:UINT64{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
ld1d {za0h.d[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:TILE:UINT64{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
ld1d {za0h.d[w12, 1]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:TILE:UINT8{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
ld1b {za0v.b[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:TILE:UINT8{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
ld1b {za0v.b[w12, 15]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:TILE:UINT8{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
ld1b {za0h.b[w12, 0]}, p1/z, [x10]
### op load [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:TILE:UINT8{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
ld1b {za0h.b[w12, 15]}, p1/z, [x10]
### op load [PARAM] adreg:REGISTER:FP:DOUBLE param:NAME:-:-
ldr d1, %[p]
### op load [PARAM] adreg:REGISTER:FP:FP8E4M3 param:NAME:-:-
ldr b1, %[p]
### op load [PARAM] adreg:REGISTER:FP:FP8E5M2 param:NAME:-:-
ldr b1, %[p]
### op load [PARAM] adreg:REGISTER:FP:HALF param:NAME:-:-
ldr h1, %[p]
### op load [PARAM] adreg:REGISTER:FP:SINGLE param:NAME:-:-
ldr s1, %[p]
### op load [PARAM] adreg:REGISTER:GP:SINT16 param:NAME:-:-
ldrh w10, %[p]
### op load [PARAM] adreg:REGISTER:GP:SINT32 param:NAME:-:-
ldr w10, %[p]
### op load [PARAM] adreg:REGISTER:GP:SINT64 param:NAME:-:-
ldr x10, %[p]
### op load [PARAM] adreg:REGISTER:GP:SINT8 param:NAME:-:-
ldrb w10, %[p]
### op load [PARAM] adreg:REGISTER:GP:UINT16 param:NAME:-:-
ldrh w10, %[p]
### op load [PARAM] adreg:REGISTER:GP:UINT32 param:NAME:-:-
ldr w10, %[p]
### op load [PARAM] adreg:REGISTER:GP:UINT64 param:NAME:-:-
ldr x10, %[p]
### op load [PARAM] adreg:REGISTER:GP:UINT8 param:NAME:-:-
ldrb w10, %[p]
### op load [POSTINC] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldr d1, [x10], #-256
### op load [POSTINC] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldr d1, [x10], #255
### op load [POSTINC] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldr d1, [x10], x11
### op load [POSTINC] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldr b1, [x10], #-256
### op load [POSTINC] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldr b1, [x10], #255
### op load [POSTINC] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldr b1, [x10], x11
### op load [POSTINC] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldr b1, [x10], #-256
### op load [POSTINC] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldr b1, [x10], #255
### op load [POSTINC] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldr b1, [x10], x11
### op load [POSTINC] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldr h1, [x10], #-256
### op load [POSTINC] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldr h1, [x10], #255
### op load [POSTINC] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldr h1, [x10], x11
### op load [POSTINC] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldr s1, [x10], #-256
### op load [POSTINC] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldr s1, [x10], #255
### op load [POSTINC] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldr s1, [x10], x11
### op load [POSTINC] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldrh w10, [x11], #-256
### op load [POSTINC] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldrh w10, [x11], #255
### op load [POSTINC] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldrh w10, [x11], x12
### op load [POSTINC] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldr w10, [x11], #-256
### op load [POSTINC] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldr w10, [x11], #255
### op load [POSTINC] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldr w10, [x11], x12
### op load [POSTINC] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldr x10, [x11], #-256
### op load [POSTINC] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldr x10, [x11], #255
### op load [POSTINC] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldr x10, [x11], x12
### op load [POSTINC] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldrb w10, [x11], #-256
### op load [POSTINC] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldrb w10, [x11], #255
### op load [POSTINC] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldrb w10, [x11], x12
### op load [POSTINC] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldrh w10, [x11], #-256
### op load [POSTINC] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldrh w10, [x11], #255
### op load [POSTINC] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldrh w10, [x11], x12
### op load [POSTINC] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldr w10, [x11], #-256
### op load [POSTINC] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldr w10, [x11], #255
### op load [POSTINC] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldr w10, [x11], x12
### op load [POSTINC] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldr x10, [x11], #-256
### op load [POSTINC] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldr x10, [x11], #255
### op load [POSTINC] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldr x10, [x11], x12
### op load [POSTINC] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
ldrb w10, [x11], #-256
### op load [POSTINC] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
ldrb w10, [x11], #255
### op load [POSTINC] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
ldrb w10, [x11], x12
### op load [] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64
ldr d1, [x10]
### op load [] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64
ldr b1, [x10]
### op load [] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64
ldr b1, [x10]
### op load [] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64
ldr h1, [x10]
### op load [] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64
ldr s1, [x10]
### op load [] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64
ldrh w10, [x11]
### op load [] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64
ldr w10, [x11]
### op load [] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64
ldr x10, [x11]
### op load [] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64
ldrb w10, [x11]
### op load [] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64
ldrh w10, [x11]
### op load [] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64
ldr w10, [x11]
### op load [] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64
ldr x10, [x11]
### op load [] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64
ldrb w10, [x11]
### op move [BITS] adreg:REGISTER:GP:UINT16 bdreg:REGISTER:FP:HALF
fmov h1,w10
### op move [BITS] adreg:REGISTER:GP:UINT32 bdreg:REGISTER:FP:SINGLE
fmov s1,w10
### op move [BITS] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:FP:DOUBLE
fmov d1,x10
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:BF16 adreg:REGISTER:TILE:BF16{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:BF16{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:TILE:BF16{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:BF16{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- edreg:REGISTER:VEC:BF16 fdreg:REGISTER:VEC:BF16 gdreg:REGISTER:VEC:BF16 hdreg:REGISTER:VEC:BF16 {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.BF16
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:BF16 adreg:REGISTER:TILE:BF16{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:BF16{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:VEC:BF16 ddreg:REGISTER:VEC:BF16 {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_colreg: cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:BF16 adreg:REGISTER:TILE:BF16{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:BF16{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:TILE:BF16{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:BF16{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- edreg:REGISTER:VEC:BF16 fdreg:REGISTER:VEC:BF16 gdreg:REGISTER:VEC:BF16 hdreg:REGISTER:VEC:BF16 {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.BF16
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:BF16 adreg:REGISTER:TILE:BF16{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:BF16{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:VEC:BF16 ddreg:REGISTER:VEC:BF16 {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_rowreg: cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:TILE:BF16{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:BF16{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:TILE:BF16{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:BF16{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2} @far
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:TILE:BF16{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:BF16{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:TILE:BF16{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:BF16{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2} @far
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 ddreg:REGISTER:VEC:BF16 edreg:REGISTER:TILE:BF16{COL} edreg_immcol:IMMEDIATE:-:- edreg_colreg:REGISTER:GP:- fdreg:REGISTER:TILE:BF16{COL} fdreg_immcol:IMMEDIATE:-:- fdreg_colreg:REGISTER:GP:- gdreg:REGISTER:TILE:BF16{COL} gdreg_immcol:IMMEDIATE:-:- gdreg_colreg:REGISTER:GP:- hdreg:REGISTER:TILE:BF16{COL} hdreg_immcol:IMMEDIATE:-:- hdreg_colreg:REGISTER:GP:- {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.BF16
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 ddreg:REGISTER:VEC:BF16 edreg:REGISTER:TILE:BF16{COL} edreg_immcol:IMMEDIATE:-:- edreg_colreg:REGISTER:GP:- fdreg:REGISTER:TILE:BF16{COL} fdreg_immcol:IMMEDIATE:-:- fdreg_colreg:REGISTER:GP:- gdreg:REGISTER:TILE:BF16{COL} gdreg_immcol:IMMEDIATE:-:- gdreg_colreg:REGISTER:GP:- hdreg:REGISTER:TILE:BF16{COL} hdreg_immcol:IMMEDIATE:-:- hdreg_colreg:REGISTER:GP:- {nin:4,nout:4} @far
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.BF16
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 ddreg:REGISTER:VEC:BF16 edreg:REGISTER:TILE:BF16{ROW} edreg_immrow:IMMEDIATE:-:- edreg_rowreg:REGISTER:GP:- fdreg:REGISTER:TILE:BF16{ROW} fdreg_immrow:IMMEDIATE:-:- fdreg_rowreg:REGISTER:GP:- gdreg:REGISTER:TILE:BF16{ROW} gdreg_immrow:IMMEDIATE:-:- gdreg_rowreg:REGISTER:GP:- hdreg:REGISTER:TILE:BF16{ROW} hdreg_immrow:IMMEDIATE:-:- hdreg_rowreg:REGISTER:GP:- {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.BF16
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 ddreg:REGISTER:VEC:BF16 edreg:REGISTER:TILE:BF16{ROW} edreg_immrow:IMMEDIATE:-:- edreg_rowreg:REGISTER:GP:- fdreg:REGISTER:TILE:BF16{ROW} fdreg_immrow:IMMEDIATE:-:- fdreg_rowreg:REGISTER:GP:- gdreg:REGISTER:TILE:BF16{ROW} gdreg_immrow:IMMEDIATE:-:- gdreg_rowreg:REGISTER:GP:- hdreg:REGISTER:TILE:BF16{ROW} hdreg_immrow:IMMEDIATE:-:- hdreg_rowreg:REGISTER:GP:- {nin:4,nout:4} @far
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.BF16
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:TILE:DOUBLE{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:DOUBLE{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:TILE:DOUBLE{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:DOUBLE{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- edreg:REGISTER:VEC:DOUBLE fdreg:REGISTER:VEC:DOUBLE gdreg:REGISTER:VEC:DOUBLE hdreg:REGISTER:VEC:DOUBLE {nin:4,nout:4}
!ArgumentDependencyError: unset dependency(ies) for bdreg_colreg: edreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:TILE:DOUBLE{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:DOUBLE{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_colreg: cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:TILE:DOUBLE{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:DOUBLE{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:TILE:DOUBLE{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:DOUBLE{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- edreg:REGISTER:VEC:DOUBLE fdreg:REGISTER:VEC:DOUBLE gdreg:REGISTER:VEC:DOUBLE hdreg:REGISTER:VEC:DOUBLE {nin:4,nout:4}
!ArgumentDependencyError: unset dependency(ies) for bdreg_rowreg: edreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:TILE:DOUBLE{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:DOUBLE{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_rowreg: cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:TILE:DOUBLE{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:DOUBLE{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:TILE:DOUBLE{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:DOUBLE{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE edreg:REGISTER:TILE:DOUBLE{COL} edreg_immcol:IMMEDIATE:-:- edreg_colreg:REGISTER:GP:- fdreg:REGISTER:TILE:DOUBLE{COL} fdreg_immcol:IMMEDIATE:-:- fdreg_colreg:REGISTER:GP:- gdreg:REGISTER:TILE:DOUBLE{COL} gdreg_immcol:IMMEDIATE:-:- gdreg_colreg:REGISTER:GP:- hdreg:REGISTER:TILE:DOUBLE{COL} hdreg_immcol:IMMEDIATE:-:- hdreg_colreg:REGISTER:GP:- {nin:4,nout:4}
!ValueError: index of fdreg_colreg must be equal to index of edreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE edreg:REGISTER:TILE:DOUBLE{ROW} edreg_immrow:IMMEDIATE:-:- edreg_rowreg:REGISTER:GP:- fdreg:REGISTER:TILE:DOUBLE{ROW} fdreg_immrow:IMMEDIATE:-:- fdreg_rowreg:REGISTER:GP:- gdreg:REGISTER:TILE:DOUBLE{ROW} gdreg_immrow:IMMEDIATE:-:- gdreg_rowreg:REGISTER:GP:- hdreg:REGISTER:TILE:DOUBLE{ROW} hdreg_immrow:IMMEDIATE:-:- hdreg_rowreg:REGISTER:GP:- {nin:4,nout:4}
!ValueError: index of fdreg_rowreg must be equal to index of edreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:TILE:FP8E4M3{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:FP8E4M3{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:TILE:FP8E4M3{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:FP8E4M3{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- edreg:REGISTER:VEC:FP8E4M3 fdreg:REGISTER:VEC:FP8E4M3 gdreg:REGISTER:VEC:FP8E4M3 hdreg:REGISTER:VEC:FP8E4M3 {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.FP8E4M3
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:TILE:FP8E4M3{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:FP8E4M3{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_colreg: cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:TILE:FP8E4M3{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:FP8E4M3{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:TILE:FP8E4M3{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:FP8E4M3{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- edreg:REGISTER:VEC:FP8E4M3 fdreg:REGISTER:VEC:FP8E4M3 gdreg:REGISTER:VEC:FP8E4M3 hdreg:REGISTER:VEC:FP8E4M3 {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.FP8E4M3
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:TILE:FP8E4M3{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:FP8E4M3{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_rowreg: cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:TILE:FP8E4M3{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:FP8E4M3{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:TILE:FP8E4M3{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:FP8E4M3{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2} @far
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:TILE:FP8E4M3{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:FP8E4M3{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:TILE:FP8E4M3{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:FP8E4M3{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2} @far
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 edreg:REGISTER:TILE:FP8E4M3{COL} edreg_immcol:IMMEDIATE:-:- edreg_colreg:REGISTER:GP:- fdreg:REGISTER:TILE:FP8E4M3{COL} fdreg_immcol:IMMEDIATE:-:- fdreg_colreg:REGISTER:GP:- gdreg:REGISTER:TILE:FP8E4M3{COL} gdreg_immcol:IMMEDIATE:-:- gdreg_colreg:REGISTER:GP:- hdreg:REGISTER:TILE:FP8E4M3{COL} hdreg_immcol:IMMEDIATE:-:- hdreg_colreg:REGISTER:GP:- {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.FP8E4M3
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 edreg:REGISTER:TILE:FP8E4M3{COL} edreg_immcol:IMMEDIATE:-:- edreg_colreg:REGISTER:GP:- fdreg:REGISTER:TILE:FP8E4M3{COL} fdreg_immcol:IMMEDIATE:-:- fdreg_colreg:REGISTER:GP:- gdreg:REGISTER:TILE:FP8E4M3{COL} gdreg_immcol:IMMEDIATE:-:- gdreg_colreg:REGISTER:GP:- hdreg:REGISTER:TILE:FP8E4M3{COL} hdreg_immcol:IMMEDIATE:-:- hdreg_colreg:REGISTER:GP:- {nin:4,nout:4} @far
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.FP8E4M3
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 edreg:REGISTER:TILE:FP8E4M3{ROW} edreg_immrow:IMMEDIATE:-:- edreg_rowreg:REGISTER:GP:- fdreg:REGISTER:TILE:FP8E4M3{ROW} fdreg_immrow:IMMEDIATE:-:- fdreg_rowreg:REGISTER:GP:- gdreg:REGISTER:TILE:FP8E4M3{ROW} gdreg_immrow:IMMEDIATE:-:- gdreg_rowreg:REGISTER:GP:- hdreg:REGISTER:TILE:FP8E4M3{ROW} hdreg_immrow:IMMEDIATE:-:- hdreg_rowreg:REGISTER:GP:- {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.FP8E4M3
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 edreg:REGISTER:TILE:FP8E4M3{ROW} edreg_immrow:IMMEDIATE:-:- edreg_rowreg:REGISTER:GP:- fdreg:REGISTER:TILE:FP8E4M3{ROW} fdreg_immrow:IMMEDIATE:-:- fdreg_rowreg:REGISTER:GP:- gdreg:REGISTER:TILE:FP8E4M3{ROW} gdreg_immrow:IMMEDIATE:-:- gdreg_rowreg:REGISTER:GP:- hdreg:REGISTER:TILE:FP8E4M3{ROW} hdreg_immrow:IMMEDIATE:-:- hdreg_rowreg:REGISTER:GP:- {nin:4,nout:4} @far
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.FP8E4M3
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:TILE:FP8E5M2{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:FP8E5M2{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:TILE:FP8E5M2{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:FP8E5M2{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- edreg:REGISTER:VEC:FP8E5M2 fdreg:REGISTER:VEC:FP8E5M2 gdreg:REGISTER:VEC:FP8E5M2 hdreg:REGISTER:VEC:FP8E5M2 {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.FP8E5M2
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:TILE:FP8E5M2{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:FP8E5M2{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_colreg: cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:TILE:FP8E5M2{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:FP8E5M2{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:TILE:FP8E5M2{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:FP8E5M2{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- edreg:REGISTER:VEC:FP8E5M2 fdreg:REGISTER:VEC:FP8E5M2 gdreg:REGISTER:VEC:FP8E5M2 hdreg:REGISTER:VEC:FP8E5M2 {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.FP8E5M2
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:TILE:FP8E5M2{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:FP8E5M2{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_rowreg: cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:TILE:FP8E5M2{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:FP8E5M2{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:TILE:FP8E5M2{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:FP8E5M2{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2} @far
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:TILE:FP8E5M2{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:FP8E5M2{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:TILE:FP8E5M2{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:FP8E5M2{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2} @far
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 edreg:REGISTER:TILE:FP8E5M2{COL} edreg_immcol:IMMEDIATE:-:- edreg_colreg:REGISTER:GP:- fdreg:REGISTER:TILE:FP8E5M2{COL} fdreg_immcol:IMMEDIATE:-:- fdreg_colreg:REGISTER:GP:- gdreg:REGISTER:TILE:FP8E5M2{COL} gdreg_immcol:IMMEDIATE:-:- gdreg_colreg:REGISTER:GP:- hdreg:REGISTER:TILE:FP8E5M2{COL} hdreg_immcol:IMMEDIATE:-:- hdreg_colreg:REGISTER:GP:- {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.FP8E5M2
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 edreg:REGISTER:TILE:FP8E5M2{COL} edreg_immcol:IMMEDIATE:-:- edreg_colreg:REGISTER:GP:- fdreg:REGISTER:TILE:FP8E5M2{COL} fdreg_immcol:IMMEDIATE:-:- fdreg_colreg:REGISTER:GP:- gdreg:REGISTER:TILE:FP8E5M2{COL} gdreg_immcol:IMMEDIATE:-:- gdreg_colreg:REGISTER:GP:- hdreg:REGISTER:TILE:FP8E5M2{COL} hdreg_immcol:IMMEDIATE:-:- hdreg_colreg:REGISTER:GP:- {nin:4,nout:4} @far
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.FP8E5M2
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 edreg:REGISTER:TILE:FP8E5M2{ROW} edreg_immrow:IMMEDIATE:-:- edreg_rowreg:REGISTER:GP:- fdreg:REGISTER:TILE:FP8E5M2{ROW} fdreg_immrow:IMMEDIATE:-:- fdreg_rowreg:REGISTER:GP:- gdreg:REGISTER:TILE:FP8E5M2{ROW} gdreg_immrow:IMMEDIATE:-:- gdreg_rowreg:REGISTER:GP:- hdreg:REGISTER:TILE:FP8E5M2{ROW} hdreg_immrow:IMMEDIATE:-:- hdreg_rowreg:REGISTER:GP:- {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.FP8E5M2
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 edreg:REGISTER:TILE:FP8E5M2{ROW} edreg_immrow:IMMEDIATE:-:- edreg_rowreg:REGISTER:GP:- fdreg:REGISTER:TILE:FP8E5M2{ROW} fdreg_immrow:IMMEDIATE:-:- fdreg_rowreg:REGISTER:GP:- gdreg:REGISTER:TILE:FP8E5M2{ROW} gdreg_immrow:IMMEDIATE:-:- gdreg_rowreg:REGISTER:GP:- hdreg:REGISTER:TILE:FP8E5M2{ROW} hdreg_immrow:IMMEDIATE:-:- hdreg_rowreg:REGISTER:GP:- {nin:4,nout:4} @far
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.FP8E5M2
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:HALF adreg:REGISTER:TILE:HALF{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:HALF{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:TILE:HALF{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:HALF{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- edreg:REGISTER:VEC:HALF fdreg:REGISTER:VEC:HALF gdreg:REGISTER:VEC:HALF hdreg:REGISTER:VEC:HALF {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.HALF
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:HALF adreg:REGISTER:TILE:HALF{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:HALF{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_colreg: cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:HALF adreg:REGISTER:TILE:HALF{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:HALF{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:TILE:HALF{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:HALF{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- edreg:REGISTER:VEC:HALF fdreg:REGISTER:VEC:HALF gdreg:REGISTER:VEC:HALF hdreg:REGISTER:VEC:HALF {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.HALF
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:HALF adreg:REGISTER:TILE:HALF{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:HALF{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_rowreg: cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:TILE:HALF{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:HALF{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:TILE:HALF{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:HALF{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2} @far
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:TILE:HALF{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:HALF{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:TILE:HALF{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:HALF{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2} @far
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF edreg:REGISTER:TILE:HALF{COL} edreg_immcol:IMMEDIATE:-:- edreg_colreg:REGISTER:GP:- fdreg:REGISTER:TILE:HALF{COL} fdreg_immcol:IMMEDIATE:-:- fdreg_colreg:REGISTER:GP:- gdreg:REGISTER:TILE:HALF{COL} gdreg_immcol:IMMEDIATE:-:- gdreg_colreg:REGISTER:GP:- hdreg:REGISTER:TILE:HALF{COL} hdreg_immcol:IMMEDIATE:-:- hdreg_colreg:REGISTER:GP:- {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.HALF
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF edreg:REGISTER:TILE:HALF{COL} edreg_immcol:IMMEDIATE:-:- edreg_colreg:REGISTER:GP:- fdreg:REGISTER:TILE:HALF{COL} fdreg_immcol:IMMEDIATE:-:- fdreg_colreg:REGISTER:GP:- gdreg:REGISTER:TILE:HALF{COL} gdreg_immcol:IMMEDIATE:-:- gdreg_colreg:REGISTER:GP:- hdreg:REGISTER:TILE:HALF{COL} hdreg_immcol:IMMEDIATE:-:- hdreg_colreg:REGISTER:GP:- {nin:4,nout:4} @far
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.HALF
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF edreg:REGISTER:TILE:HALF{ROW} edreg_immrow:IMMEDIATE:-:- edreg_rowreg:REGISTER:GP:- fdreg:REGISTER:TILE:HALF{ROW} fdreg_immrow:IMMEDIATE:-:- fdreg_rowreg:REGISTER:GP:- gdreg:REGISTER:TILE:HALF{ROW} gdreg_immrow:IMMEDIATE:-:- gdreg_rowreg:REGISTER:GP:- hdreg:REGISTER:TILE:HALF{ROW} hdreg_immrow:IMMEDIATE:-:- hdreg_rowreg:REGISTER:GP:- {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.HALF
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF edreg:REGISTER:TILE:HALF{ROW} edreg_immrow:IMMEDIATE:-:- edreg_rowreg:REGISTER:GP:- fdreg:REGISTER:TILE:HALF{ROW} fdreg_immrow:IMMEDIATE:-:- fdreg_rowreg:REGISTER:GP:- gdreg:REGISTER:TILE:HALF{ROW} gdreg_immrow:IMMEDIATE:-:- gdreg_rowreg:REGISTER:GP:- hdreg:REGISTER:TILE:HALF{ROW} hdreg_immrow:IMMEDIATE:-:- hdreg_rowreg:REGISTER:GP:- {nin:4,nout:4} @far
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.HALF
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINGLE adreg:REGISTER:TILE:SINGLE{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:SINGLE{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:TILE:SINGLE{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINGLE{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- edreg:REGISTER:VEC:SINGLE fdreg:REGISTER:VEC:SINGLE gdreg:REGISTER:VEC:SINGLE hdreg:REGISTER:VEC:SINGLE {nin:4,nout:4}
!ArgumentDependencyError: unset dependency(ies) for bdreg_colreg: edreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINGLE adreg:REGISTER:TILE:SINGLE{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:SINGLE{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_colreg: cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINGLE adreg:REGISTER:TILE:SINGLE{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:SINGLE{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:TILE:SINGLE{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINGLE{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- edreg:REGISTER:VEC:SINGLE fdreg:REGISTER:VEC:SINGLE gdreg:REGISTER:VEC:SINGLE hdreg:REGISTER:VEC:SINGLE {nin:4,nout:4}
!ArgumentDependencyError: unset dependency(ies) for bdreg_rowreg: edreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINGLE adreg:REGISTER:TILE:SINGLE{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:SINGLE{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_rowreg: cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:TILE:SINGLE{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINGLE{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:TILE:SINGLE{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINGLE{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2} @far
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:TILE:SINGLE{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINGLE{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:TILE:SINGLE{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINGLE{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2} @far
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE edreg:REGISTER:TILE:SINGLE{COL} edreg_immcol:IMMEDIATE:-:- edreg_colreg:REGISTER:GP:- fdreg:REGISTER:TILE:SINGLE{COL} fdreg_immcol:IMMEDIATE:-:- fdreg_colreg:REGISTER:GP:- gdreg:REGISTER:TILE:SINGLE{COL} gdreg_immcol:IMMEDIATE:-:- gdreg_colreg:REGISTER:GP:- hdreg:REGISTER:TILE:SINGLE{COL} hdreg_immcol:IMMEDIATE:-:- hdreg_colreg:REGISTER:GP:- {nin:4,nout:4}
!ValueError: index of fdreg_colreg must be equal to index of edreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE edreg:REGISTER:TILE:SINGLE{ROW} edreg_immrow:IMMEDIATE:-:- edreg_rowreg:REGISTER:GP:- fdreg:REGISTER:TILE:SINGLE{ROW} fdreg_immrow:IMMEDIATE:-:- fdreg_rowreg:REGISTER:GP:- gdreg:REGISTER:TILE:SINGLE{ROW} gdreg_immrow:IMMEDIATE:-:- gdreg_rowreg:REGISTER:GP:- hdreg:REGISTER:TILE:SINGLE{ROW} hdreg_immrow:IMMEDIATE:-:- hdreg_rowreg:REGISTER:GP:- {nin:4,nout:4}
!ValueError: index of fdreg_rowreg must be equal to index of edreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT16 adreg:REGISTER:TILE:SINT16{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:SINT16{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:TILE:SINT16{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINT16{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- edreg:REGISTER:VEC:SINT16 fdreg:REGISTER:VEC:SINT16 gdreg:REGISTER:VEC:SINT16 hdreg:REGISTER:VEC:SINT16 {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.SINT16
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT16 adreg:REGISTER:TILE:SINT16{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:SINT16{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_colreg: cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT16 adreg:REGISTER:TILE:SINT16{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:SINT16{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:TILE:SINT16{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINT16{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- edreg:REGISTER:VEC:SINT16 fdreg:REGISTER:VEC:SINT16 gdreg:REGISTER:VEC:SINT16 hdreg:REGISTER:VEC:SINT16 {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.SINT16
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT16 adreg:REGISTER:TILE:SINT16{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:SINT16{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_rowreg: cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:TILE:SINT16{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINT16{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:TILE:SINT16{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINT16{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2} @far
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:TILE:SINT16{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINT16{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:TILE:SINT16{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINT16{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2} @far
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 edreg:REGISTER:TILE:SINT16{COL} edreg_immcol:IMMEDIATE:-:- edreg_colreg:REGISTER:GP:- fdreg:REGISTER:TILE:SINT16{COL} fdreg_immcol:IMMEDIATE:-:- fdreg_colreg:REGISTER:GP:- gdreg:REGISTER:TILE:SINT16{COL} gdreg_immcol:IMMEDIATE:-:- gdreg_colreg:REGISTER:GP:- hdreg:REGISTER:TILE:SINT16{COL} hdreg_immcol:IMMEDIATE:-:- hdreg_colreg:REGISTER:GP:- {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.SINT16
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 edreg:REGISTER:TILE:SINT16{COL} edreg_immcol:IMMEDIATE:-:- edreg_colreg:REGISTER:GP:- fdreg:REGISTER:TILE:SINT16{COL} fdreg_immcol:IMMEDIATE:-:- fdreg_colreg:REGISTER:GP:- gdreg:REGISTER:TILE:SINT16{COL} gdreg_immcol:IMMEDIATE:-:- gdreg_colreg:REGISTER:GP:- hdreg:REGISTER:TILE:SINT16{COL} hdreg_immcol:IMMEDIATE:-:- hdreg_colreg:REGISTER:GP:- {nin:4,nout:4} @far
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.SINT16
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 edreg:REGISTER:TILE:SINT16{ROW} edreg_immrow:IMMEDIATE:-:- edreg_rowreg:REGISTER:GP:- fdreg:REGISTER:TILE:SINT16{ROW} fdreg_immrow:IMMEDIATE:-:- fdreg_rowreg:REGISTER:GP:- gdreg:REGISTER:TILE:SINT16{ROW} gdreg_immrow:IMMEDIATE:-:- gdreg_rowreg:REGISTER:GP:- hdreg:REGISTER:TILE:SINT16{ROW} hdreg_immrow:IMMEDIATE:-:- hdreg_rowreg:REGISTER:GP:- {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.SINT16
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 edreg:REGISTER:TILE:SINT16{ROW} edreg_immrow:IMMEDIATE:-:- edreg_rowreg:REGISTER:GP:- fdreg:REGISTER:TILE:SINT16{ROW} fdreg_immrow:IMMEDIATE:-:- fdreg_rowreg:REGISTER:GP:- gdreg:REGISTER:TILE:SINT16{ROW} gdreg_immrow:IMMEDIATE:-:- gdreg_rowreg:REGISTER:GP:- hdreg:REGISTER:TILE:SINT16{ROW} hdreg_immrow:IMMEDIATE:-:- hdreg_rowreg:REGISTER:GP:- {nin:4,nout:4} @far
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.SINT16
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT32 adreg:REGISTER:TILE:SINT32{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:SINT32{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:TILE:SINT32{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINT32{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- edreg:REGISTER:VEC:SINT32 fdreg:REGISTER:VEC:SINT32 gdreg:REGISTER:VEC:SINT32 hdreg:REGISTER:VEC:SINT32 {nin:4,nout:4}
!ArgumentDependencyError: unset dependency(ies) for bdreg_colreg: edreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT32 adreg:REGISTER:TILE:SINT32{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:SINT32{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_colreg: cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT32 adreg:REGISTER:TILE:SINT32{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:SINT32{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:TILE:SINT32{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINT32{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- edreg:REGISTER:VEC:SINT32 fdreg:REGISTER:VEC:SINT32 gdreg:REGISTER:VEC:SINT32 hdreg:REGISTER:VEC:SINT32 {nin:4,nout:4}
!ArgumentDependencyError: unset dependency(ies) for bdreg_rowreg: edreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT32 adreg:REGISTER:TILE:SINT32{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:SINT32{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_rowreg: cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:TILE:SINT32{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINT32{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:TILE:SINT32{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINT32{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2} @far
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:TILE:SINT32{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINT32{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:TILE:SINT32{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINT32{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2} @far
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 edreg:REGISTER:TILE:SINT32{COL} edreg_immcol:IMMEDIATE:-:- edreg_colreg:REGISTER:GP:- fdreg:REGISTER:TILE:SINT32{COL} fdreg_immcol:IMMEDIATE:-:- fdreg_colreg:REGISTER:GP:- gdreg:REGISTER:TILE:SINT32{COL} gdreg_immcol:IMMEDIATE:-:- gdreg_colreg:REGISTER:GP:- hdreg:REGISTER:TILE:SINT32{COL} hdreg_immcol:IMMEDIATE:-:- hdreg_colreg:REGISTER:GP:- {nin:4,nout:4}
!ValueError: index of fdreg_colreg must be equal to index of edreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 edreg:REGISTER:TILE:SINT32{ROW} edreg_immrow:IMMEDIATE:-:- edreg_rowreg:REGISTER:GP:- fdreg:REGISTER:TILE:SINT32{ROW} fdreg_immrow:IMMEDIATE:-:- fdreg_rowreg:REGISTER:GP:- gdreg:REGISTER:TILE:SINT32{ROW} gdreg_immrow:IMMEDIATE:-:- gdreg_rowreg:REGISTER:GP:- hdreg:REGISTER:TILE:SINT32{ROW} hdreg_immrow:IMMEDIATE:-:- hdreg_rowreg:REGISTER:GP:- {nin:4,nout:4}
!ValueError: index of fdreg_rowreg must be equal to index of edreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT64 adreg:REGISTER:TILE:SINT64{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:SINT64{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:TILE:SINT64{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINT64{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- edreg:REGISTER:VEC:SINT64 fdreg:REGISTER:VEC:SINT64 gdreg:REGISTER:VEC:SINT64 hdreg:REGISTER:VEC:SINT64 {nin:4,nout:4}
!ArgumentDependencyError: unset dependency(ies) for bdreg_colreg: edreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT64 adreg:REGISTER:TILE:SINT64{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:SINT64{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_colreg: cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT64 adreg:REGISTER:TILE:SINT64{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:SINT64{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:TILE:SINT64{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINT64{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- edreg:REGISTER:VEC:SINT64 fdreg:REGISTER:VEC:SINT64 gdreg:REGISTER:VEC:SINT64 hdreg:REGISTER:VEC:SINT64 {nin:4,nout:4}
!ArgumentDependencyError: unset dependency(ies) for bdreg_rowreg: edreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT64 adreg:REGISTER:TILE:SINT64{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:SINT64{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_rowreg: cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:TILE:SINT64{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINT64{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:TILE:SINT64{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINT64{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 edreg:REGISTER:TILE:SINT64{COL} edreg_immcol:IMMEDIATE:-:- edreg_colreg:REGISTER:GP:- fdreg:REGISTER:TILE:SINT64{COL} fdreg_immcol:IMMEDIATE:-:- fdreg_colreg:REGISTER:GP:- gdreg:REGISTER:TILE:SINT64{COL} gdreg_immcol:IMMEDIATE:-:- gdreg_colreg:REGISTER:GP:- hdreg:REGISTER:TILE:SINT64{COL} hdreg_immcol:IMMEDIATE:-:- hdreg_colreg:REGISTER:GP:- {nin:4,nout:4}
!ValueError: index of fdreg_colreg must be equal to index of edreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 edreg:REGISTER:TILE:SINT64{ROW} edreg_immrow:IMMEDIATE:-:- edreg_rowreg:REGISTER:GP:- fdreg:REGISTER:TILE:SINT64{ROW} fdreg_immrow:IMMEDIATE:-:- fdreg_rowreg:REGISTER:GP:- gdreg:REGISTER:TILE:SINT64{ROW} gdreg_immrow:IMMEDIATE:-:- gdreg_rowreg:REGISTER:GP:- hdreg:REGISTER:TILE:SINT64{ROW} hdreg_immrow:IMMEDIATE:-:- hdreg_rowreg:REGISTER:GP:- {nin:4,nout:4}
!ValueError: index of fdreg_rowreg must be equal to index of edreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT8 adreg:REGISTER:TILE:SINT8{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:SINT8{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:TILE:SINT8{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINT8{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- edreg:REGISTER:VEC:SINT8 fdreg:REGISTER:VEC:SINT8 gdreg:REGISTER:VEC:SINT8 hdreg:REGISTER:VEC:SINT8 {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.SINT8
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT8 adreg:REGISTER:TILE:SINT8{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:SINT8{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_colreg: cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT8 adreg:REGISTER:TILE:SINT8{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:SINT8{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:TILE:SINT8{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINT8{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- edreg:REGISTER:VEC:SINT8 fdreg:REGISTER:VEC:SINT8 gdreg:REGISTER:VEC:SINT8 hdreg:REGISTER:VEC:SINT8 {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.SINT8
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT8 adreg:REGISTER:TILE:SINT8{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:SINT8{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_rowreg: cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:TILE:SINT8{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINT8{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:TILE:SINT8{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINT8{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2} @far
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:TILE:SINT8{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINT8{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:TILE:SINT8{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:SINT8{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2} @far
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 edreg:REGISTER:TILE:SINT8{COL} edreg_immcol:IMMEDIATE:-:- edreg_colreg:REGISTER:GP:- fdreg:REGISTER:TILE:SINT8{COL} fdreg_immcol:IMMEDIATE:-:- fdreg_colreg:REGISTER:GP:- gdreg:REGISTER:TILE:SINT8{COL} gdreg_immcol:IMMEDIATE:-:- gdreg_colreg:REGISTER:GP:- hdreg:REGISTER:TILE:SINT8{COL} hdreg_immcol:IMMEDIATE:-:- hdreg_colreg:REGISTER:GP:- {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.SINT8
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 edreg:REGISTER:TILE:SINT8{COL} edreg_immcol:IMMEDIATE:-:- edreg_colreg:REGISTER:GP:- fdreg:REGISTER:TILE:SINT8{COL} fdreg_immcol:IMMEDIATE:-:- fdreg_colreg:REGISTER:GP:- gdreg:REGISTER:TILE:SINT8{COL} gdreg_immcol:IMMEDIATE:-:- gdreg_colreg:REGISTER:GP:- hdreg:REGISTER:TILE:SINT8{COL} hdreg_immcol:IMMEDIATE:-:- hdreg_colreg:REGISTER:GP:- {nin:4,nout:4} @far
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.SINT8
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 edreg:REGISTER:TILE:SINT8{ROW} edreg_immrow:IMMEDIATE:-:- edreg_rowreg:REGISTER:GP:- fdreg:REGISTER:TILE:SINT8{ROW} fdreg_immrow:IMMEDIATE:-:- fdreg_rowreg:REGISTER:GP:- gdreg:REGISTER:TILE:SINT8{ROW} gdreg_immrow:IMMEDIATE:-:- gdreg_rowreg:REGISTER:GP:- hdreg:REGISTER:TILE:SINT8{ROW} hdreg_immrow:IMMEDIATE:-:- hdreg_rowreg:REGISTER:GP:- {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.SINT8
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 edreg:REGISTER:TILE:SINT8{ROW} edreg_immrow:IMMEDIATE:-:- edreg_rowreg:REGISTER:GP:- fdreg:REGISTER:TILE:SINT8{ROW} fdreg_immrow:IMMEDIATE:-:- fdreg_rowreg:REGISTER:GP:- gdreg:REGISTER:TILE:SINT8{ROW} gdreg_immrow:IMMEDIATE:-:- gdreg_rowreg:REGISTER:GP:- hdreg:REGISTER:TILE:SINT8{ROW} hdreg_immrow:IMMEDIATE:-:- hdreg_rowreg:REGISTER:GP:- {nin:4,nout:4} @far
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.SINT8
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT16 adreg:REGISTER:TILE:UINT16{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:UINT16{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:TILE:UINT16{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:UINT16{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- edreg:REGISTER:VEC:UINT16 fdreg:REGISTER:VEC:UINT16 gdreg:REGISTER:VEC:UINT16 hdreg:REGISTER:VEC:UINT16 {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.UINT16
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT16 adreg:REGISTER:TILE:UINT16{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:UINT16{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_colreg: cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT16 adreg:REGISTER:TILE:UINT16{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:UINT16{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:TILE:UINT16{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:UINT16{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- edreg:REGISTER:VEC:UINT16 fdreg:REGISTER:VEC:UINT16 gdreg:REGISTER:VEC:UINT16 hdreg:REGISTER:VEC:UINT16 {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.UINT16
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT16 adreg:REGISTER:TILE:UINT16{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:UINT16{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_rowreg: cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:TILE:UINT16{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:UINT16{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:TILE:UINT16{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:UINT16{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2} @far
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:TILE:UINT16{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:UINT16{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:TILE:UINT16{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:UINT16{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2} @far
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 edreg:REGISTER:TILE:UINT16{COL} edreg_immcol:IMMEDIATE:-:- edreg_colreg:REGISTER:GP:- fdreg:REGISTER:TILE:UINT16{COL} fdreg_immcol:IMMEDIATE:-:- fdreg_colreg:REGISTER:GP:- gdreg:REGISTER:TILE:UINT16{COL} gdreg_immcol:IMMEDIATE:-:- gdreg_colreg:REGISTER:GP:- hdreg:REGISTER:TILE:UINT16{COL} hdreg_immcol:IMMEDIATE:-:- hdreg_colreg:REGISTER:GP:- {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.UINT16
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 edreg:REGISTER:TILE:UINT16{COL} edreg_immcol:IMMEDIATE:-:- edreg_colreg:REGISTER:GP:- fdreg:REGISTER:TILE:UINT16{COL} fdreg_immcol:IMMEDIATE:-:- fdreg_colreg:REGISTER:GP:- gdreg:REGISTER:TILE:UINT16{COL} gdreg_immcol:IMMEDIATE:-:- gdreg_colreg:REGISTER:GP:- hdreg:REGISTER:TILE:UINT16{COL} hdreg_immcol:IMMEDIATE:-:- hdreg_colreg:REGISTER:GP:- {nin:4,nout:4} @far
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.UINT16
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 edreg:REGISTER:TILE:UINT16{ROW} edreg_immrow:IMMEDIATE:-:- edreg_rowreg:REGISTER:GP:- fdreg:REGISTER:TILE:UINT16{ROW} fdreg_immrow:IMMEDIATE:-:- fdreg_rowreg:REGISTER:GP:- gdreg:REGISTER:TILE:UINT16{ROW} gdreg_immrow:IMMEDIATE:-:- gdreg_rowreg:REGISTER:GP:- hdreg:REGISTER:TILE:UINT16{ROW} hdreg_immrow:IMMEDIATE:-:- hdreg_rowreg:REGISTER:GP:- {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.UINT16
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 edreg:REGISTER:TILE:UINT16{ROW} edreg_immrow:IMMEDIATE:-:- edreg_rowreg:REGISTER:GP:- fdreg:REGISTER:TILE:UINT16{ROW} fdreg_immrow:IMMEDIATE:-:- fdreg_rowreg:REGISTER:GP:- gdreg:REGISTER:TILE:UINT16{ROW} gdreg_immrow:IMMEDIATE:-:- gdreg_rowreg:REGISTER:GP:- hdreg:REGISTER:TILE:UINT16{ROW} hdreg_immrow:IMMEDIATE:-:- hdreg_rowreg:REGISTER:GP:- {nin:4,nout:4} @far
!uninstantiable ValueError: SME has no tile 3 for data type asm_data_type.UINT16
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT32 adreg:REGISTER:TILE:UINT32{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:UINT32{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:TILE:UINT32{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:UINT32{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- edreg:REGISTER:VEC:UINT32 fdreg:REGISTER:VEC:UINT32 gdreg:REGISTER:VEC:UINT32 hdreg:REGISTER:VEC:UINT32 {nin:4,nout:4}
!ArgumentDependencyError: unset dependency(ies) for bdreg_colreg: edreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT32 adreg:REGISTER:TILE:UINT32{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:UINT32{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_colreg: cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT32 adreg:REGISTER:TILE:UINT32{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:UINT32{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:TILE:UINT32{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:UINT32{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- edreg:REGISTER:VEC:UINT32 fdreg:REGISTER:VEC:UINT32 gdreg:REGISTER:VEC:UINT32 hdreg:REGISTER:VEC:UINT32 {nin:4,nout:4}
!ArgumentDependencyError: unset dependency(ies) for bdreg_rowreg: edreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT32 adreg:REGISTER:TILE:UINT32{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:UINT32{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_rowreg: cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:TILE:UINT32{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:UINT32{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:TILE:UINT32{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:UINT32{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2} @far
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:TILE:UINT32{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:UINT32{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:TILE:UINT32{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:UINT32{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2} @far
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 edreg:REGISTER:TILE:UINT32{COL} edreg_immcol:IMMEDIATE:-:- edreg_colreg:REGISTER:GP:- fdreg:REGISTER:TILE:UINT32{COL} fdreg_immcol:IMMEDIATE:-:- fdreg_colreg:REGISTER:GP:- gdreg:REGISTER:TILE:UINT32{COL} gdreg_immcol:IMMEDIATE:-:- gdreg_colreg:REGISTER:GP:- hdreg:REGISTER:TILE:UINT32{COL} hdreg_immcol:IMMEDIATE:-:- hdreg_colreg:REGISTER:GP:- {nin:4,nout:4}
!ValueError: index of fdreg_colreg must be equal to index of edreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 edreg:REGISTER:TILE:UINT32{ROW} edreg_immrow:IMMEDIATE:-:- edreg_rowreg:REGISTER:GP:- fdreg:REGISTER:TILE:UINT32{ROW} fdreg_immrow:IMMEDIATE:-:- fdreg_rowreg:REGISTER:GP:- gdreg:REGISTER:TILE:UINT32{ROW} gdreg_immrow:IMMEDIATE:-:- gdreg_rowreg:REGISTER:GP:- hdreg:REGISTER:TILE:UINT32{ROW} hdreg_immrow:IMMEDIATE:-:- hdreg_rowreg:REGISTER:GP:- {nin:4,nout:4}
!ValueError: index of fdreg_rowreg must be equal to index of edreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT64 adreg:REGISTER:TILE:UINT64{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:UINT64{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:TILE:UINT64{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:UINT64{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- edreg:REGISTER:VEC:UINT64 fdreg:REGISTER:VEC:UINT64 gdreg:REGISTER:VEC:UINT64 hdreg:REGISTER:VEC:UINT64 {nin:4,nout:4}
!ArgumentDependencyError: unset dependency(ies) for bdreg_colreg: edreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT64 adreg:REGISTER:TILE:UINT64{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:UINT64{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_colreg: cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT64 adreg:REGISTER:TILE:UINT64{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:UINT64{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:TILE:UINT64{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:UINT64{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- edreg:REGISTER:VEC:UINT64 fdreg:REGISTER:VEC:UINT64 gdreg:REGISTER:VEC:UINT64 hdreg:REGISTER:VEC:UINT64 {nin:4,nout:4}
!ArgumentDependencyError: unset dependency(ies) for bdreg_rowreg: edreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT64 adreg:REGISTER:TILE:UINT64{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:UINT64{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_rowreg: cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:TILE:UINT64{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:UINT64{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:TILE:UINT64{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:UINT64{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 edreg:REGISTER:TILE:UINT64{COL} edreg_immcol:IMMEDIATE:-:- edreg_colreg:REGISTER:GP:- fdreg:REGISTER:TILE:UINT64{COL} fdreg_immcol:IMMEDIATE:-:- fdreg_colreg:REGISTER:GP:- gdreg:REGISTER:TILE:UINT64{COL} gdreg_immcol:IMMEDIATE:-:- gdreg_colreg:REGISTER:GP:- hdreg:REGISTER:TILE:UINT64{COL} hdreg_immcol:IMMEDIATE:-:- hdreg_colreg:REGISTER:GP:- {nin:4,nout:4}
!ValueError: index of fdreg_colreg must be equal to index of edreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 edreg:REGISTER:TILE:UINT64{ROW} edreg_immrow:IMMEDIATE:-:- edreg_rowreg:REGISTER:GP:- fdreg:REGISTER:TILE:UINT64{ROW} fdreg_immrow:IMMEDIATE:-:- fdreg_rowreg:REGISTER:GP:- gdreg:REGISTER:TILE:UINT64{ROW} gdreg_immrow:IMMEDIATE:-:- gdreg_rowreg:REGISTER:GP:- hdreg:REGISTER:TILE:UINT64{ROW} hdreg_immrow:IMMEDIATE:-:- hdreg_rowreg:REGISTER:GP:- {nin:4,nout:4}
!ValueError: index of fdreg_rowreg must be equal to index of edreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT8 adreg:REGISTER:TILE:UINT8{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:UINT8{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:TILE:UINT8{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:UINT8{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- edreg:REGISTER:VEC:UINT8 fdreg:REGISTER:VEC:UINT8 gdreg:REGISTER:VEC:UINT8 hdreg:REGISTER:VEC:UINT8 {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.UINT8
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT8 adreg:REGISTER:TILE:UINT8{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:TILE:UINT8{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_colreg: cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT8 adreg:REGISTER:TILE:UINT8{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:UINT8{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:TILE:UINT8{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:UINT8{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- edreg:REGISTER:VEC:UINT8 fdreg:REGISTER:VEC:UINT8 gdreg:REGISTER:VEC:UINT8 hdreg:REGISTER:VEC:UINT8 {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.UINT8
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT8 adreg:REGISTER:TILE:UINT8{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:TILE:UINT8{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 {nin:2,nout:2}
!ArgumentDependencyError: unset dependency(ies) for bdreg_rowreg: cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:TILE:UINT8{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:UINT8{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:TILE:UINT8{COL} cdreg_immcol:IMMEDIATE:-:- cdreg_colreg:REGISTER:GP:- ddreg:REGISTER:TILE:UINT8{COL} ddreg_immcol:IMMEDIATE:-:- ddreg_colreg:REGISTER:GP:- {nin:2,nout:2} @far
!ValueError: index of ddreg_colreg must be equal to index of cdreg_colreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:TILE:UINT8{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:UINT8{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2}
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:TILE:UINT8{ROW} cdreg_immrow:IMMEDIATE:-:- cdreg_rowreg:REGISTER:GP:- ddreg:REGISTER:TILE:UINT8{ROW} ddreg_immrow:IMMEDIATE:-:- ddreg_rowreg:REGISTER:GP:- {nin:2,nout:2} @far
!ValueError: index of ddreg_rowreg must be equal to index of cdreg_rowreg
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 edreg:REGISTER:TILE:UINT8{COL} edreg_immcol:IMMEDIATE:-:- edreg_colreg:REGISTER:GP:- fdreg:REGISTER:TILE:UINT8{COL} fdreg_immcol:IMMEDIATE:-:- fdreg_colreg:REGISTER:GP:- gdreg:REGISTER:TILE:UINT8{COL} gdreg_immcol:IMMEDIATE:-:- gdreg_colreg:REGISTER:GP:- hdreg:REGISTER:TILE:UINT8{COL} hdreg_immcol:IMMEDIATE:-:- hdreg_colreg:REGISTER:GP:- {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.UINT8
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 edreg:REGISTER:TILE:UINT8{COL} edreg_immcol:IMMEDIATE:-:- edreg_colreg:REGISTER:GP:- fdreg:REGISTER:TILE:UINT8{COL} fdreg_immcol:IMMEDIATE:-:- fdreg_colreg:REGISTER:GP:- gdreg:REGISTER:TILE:UINT8{COL} gdreg_immcol:IMMEDIATE:-:- gdreg_colreg:REGISTER:GP:- hdreg:REGISTER:TILE:UINT8{COL} hdreg_immcol:IMMEDIATE:-:- hdreg_colreg:REGISTER:GP:- {nin:4,nout:4} @far
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.UINT8
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 edreg:REGISTER:TILE:UINT8{ROW} edreg_immrow:IMMEDIATE:-:- edreg_rowreg:REGISTER:GP:- fdreg:REGISTER:TILE:UINT8{ROW} fdreg_immrow:IMMEDIATE:-:- fdreg_rowreg:REGISTER:GP:- gdreg:REGISTER:TILE:UINT8{ROW} gdreg_immrow:IMMEDIATE:-:- gdreg_rowreg:REGISTER:GP:- hdreg:REGISTER:TILE:UINT8{ROW} hdreg_immrow:IMMEDIATE:-:- hdreg_rowreg:REGISTER:GP:- {nin:4,nout:4}
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.UINT8
### op move [MASK,MULTIPLE_IN,MULTIPLE_OUT] amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 edreg:REGISTER:TILE:UINT8{ROW} edreg_immrow:IMMEDIATE:-:- edreg_rowreg:REGISTER:GP:- fdreg:REGISTER:TILE:UINT8{ROW} fdreg_immrow:IMMEDIATE:-:- fdreg_rowreg:REGISTER:GP:- gdreg:REGISTER:TILE:UINT8{ROW} gdreg_immrow:IMMEDIATE:-:- gdreg_rowreg:REGISTER:GP:- hdreg:REGISTER:TILE:UINT8{ROW} hdreg_immrow:IMMEDIATE:-:- hdreg_rowreg:REGISTER:GP:- {nin:4,nout:4} @far
!uninstantiable ValueError: SME has no tile 2 for data type asm_data_type.UINT8
### op move [MASK] amreg:REGISTER:MASK:BF16 adreg:REGISTER:TILE:BF16{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:VEC:BF16
!KeyError: <asm_data_type.BF16: 5>
### op move [MASK] amreg:REGISTER:MASK:BF16 adreg:REGISTER:TILE:BF16{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:VEC:BF16
!KeyError: <asm_data_type.BF16: 5>
### op move [MASK] amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:TILE:BF16{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:-
!KeyError: <asm_data_type.BF16: 5>
### op move [MASK] amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:TILE:BF16{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- @far
!KeyError: <asm_data_type.BF16: 5>
### op move [MASK] amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:TILE:BF16{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:-
!KeyError: <asm_data_type.BF16: 5>
### op move [MASK] amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:TILE:BF16{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- @far
!KeyError: <asm_data_type.BF16: 5>
### op move [MASK] amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 adreg:REGISTER:VEC:BF16
!KeyError: <asm_data_type.BF16: 5>
### op move [MASK] amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16{BCAST} adreg:REGISTER:FP:BF16
!KeyError: <asm_data_type.BF16: 5>
### op move [MASK] amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16{BCAST} adreg:REGISTER:VEC:BF16{ILANE} adreg_lane:IMMEDIATE:-:-
!KeyError: <asm_data_type.BF16: 5>
### op move [MASK] amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16{BCAST} adreg:REGISTER:VEC:BF16{ILANE} adreg_lane:IMMEDIATE:-:- @far
!KeyError: <asm_data_type.BF16: 5>
### op move [MASK] amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:TILE:DOUBLE{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:VEC:DOUBLE
mova z1.d,p1/m,za0v.d[w12,0]
### op move [MASK] amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:TILE:DOUBLE{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:VEC:DOUBLE
mova z1.d,p1/m,za0h.d[w12,0]
### op move [MASK] amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:TILE:DOUBLE{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:-
mova za0v.d[w12,0],p1/m,z1.d
### op move [MASK] amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:TILE:DOUBLE{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- @far
mova za0v.d[w12,1],p1/m,z1.d
### op move [MASK] amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:TILE:DOUBLE{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:-
mova za0h.d[w12,0],p1/m,z1.d
### op move [MASK] amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:TILE:DOUBLE{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- @far
mova za0h.d[w12,1],p1/m,z1.d
### op move [MASK] amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE adreg:REGISTER:VEC:DOUBLE
mov z1.d,p1/m,z2.d
### op move [MASK] amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE{BCAST} adreg:REGISTER:FP:DOUBLE
mov z1.d,p1/m,d1
### op move [MASK] amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE{BCAST} adreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.d,p1/m,z2.d[0]
### op move [MASK] amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE{BCAST} adreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.d,p1/m,z2.d[7]
### op move [MASK] amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:TILE:FP8E4M3{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:VEC:FP8E4M3
mova z1.b,p1/m,za0v.b[w12,0]
### op move [MASK] amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:TILE:FP8E4M3{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:VEC:FP8E4M3
mova z1.b,p1/m,za0h.b[w12,0]
### op move [MASK] amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:TILE:FP8E4M3{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:-
mova za0v.b[w12,0],p1/m,z1.b
### op move [MASK] amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:TILE:FP8E4M3{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- @far
mova za0v.b[w12,15],p1/m,z1.b
### op move [MASK] amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:TILE:FP8E4M3{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:-
mova za0h.b[w12,0],p1/m,z1.b
### op move [MASK] amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:TILE:FP8E4M3{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- @far
mova za0h.b[w12,15],p1/m,z1.b
### op move [MASK] amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3
mov z1.b,p1/m,z2.b
### op move [MASK] amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BCAST} adreg:REGISTER:FP:FP8E4M3
mov z1.b,p1/m,b1
### op move [MASK] amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BCAST} adreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.b,p1/m,z2.b[0]
### op move [MASK] amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BCAST} adreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.b,p1/m,z2.b[63]
### op move [MASK] amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:TILE:FP8E5M2{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:VEC:FP8E5M2
mova z1.b,p1/m,za0v.b[w12,0]
### op move [MASK] amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:TILE:FP8E5M2{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:VEC:FP8E5M2
mova z1.b,p1/m,za0h.b[w12,0]
### op move [MASK] amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:TILE:FP8E5M2{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:-
mova za0v.b[w12,0],p1/m,z1.b
### op move [MASK] amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:TILE:FP8E5M2{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- @far
mova za0v.b[w12,15],p1/m,z1.b
### op move [MASK] amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:TILE:FP8E5M2{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:-
mova za0h.b[w12,0],p1/m,z1.b
### op move [MASK] amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:TILE:FP8E5M2{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- @far
mova za0h.b[w12,15],p1/m,z1.b
### op move [MASK] amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2
mov z1.b,p1/m,z2.b
### op move [MASK] amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BCAST} adreg:REGISTER:FP:FP8E5M2
mov z1.b,p1/m,b1
### op move [MASK] amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BCAST} adreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.b,p1/m,z2.b[0]
### op move [MASK] amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BCAST} adreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.b,p1/m,z2.b[63]
### op move [MASK] amreg:REGISTER:MASK:HALF adreg:REGISTER:TILE:HALF{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:VEC:HALF
mova z1.h,p1/m,za0v.h[w12,0]
### op move [MASK] amreg:REGISTER:MASK:HALF adreg:REGISTER:TILE:HALF{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:VEC:HALF
mova z1.h,p1/m,za0h.h[w12,0]
### op move [MASK] amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:TILE:HALF{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:-
mova za0v.h[w12,0],p1/m,z1.h
### op move [MASK] amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:TILE:HALF{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- @far
mova za0v.h[w12,7],p1/m,z1.h
### op move [MASK] amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:TILE:HALF{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:-
mova za0h.h[w12,0],p1/m,z1.h
### op move [MASK] amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:TILE:HALF{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- @far
mova za0h.h[w12,7],p1/m,z1.h
### op move [MASK] amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF adreg:REGISTER:VEC:HALF
mov z1.h,p1/m,z2.h
### op move [MASK] amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF{BCAST} adreg:REGISTER:FP:HALF
mov z1.h,p1/m,h1
### op move [MASK] amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF{BCAST} adreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.h,p1/m,z2.h[0]
### op move [MASK] amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF{BCAST} adreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.h,p1/m,z2.h[31]
### op move [MASK] amreg:REGISTER:MASK:SINGLE adreg:REGISTER:TILE:SINGLE{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:VEC:SINGLE
mova z1.s,p1/m,za0v.s[w12,0]
### op move [MASK] amreg:REGISTER:MASK:SINGLE adreg:REGISTER:TILE:SINGLE{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:VEC:SINGLE
mova z1.s,p1/m,za0h.s[w12,0]
### op move [MASK] amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:TILE:SINGLE{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:-
mova za0v.s[w12,0],p1/m,z1.s
### op move [MASK] amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:TILE:SINGLE{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- @far
mova za0v.s[w12,3],p1/m,z1.s
### op move [MASK] amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:TILE:SINGLE{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:-
mova za0h.s[w12,0],p1/m,z1.s
### op move [MASK] amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:TILE:SINGLE{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- @far
mova za0h.s[w12,3],p1/m,z1.s
### op move [MASK] amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE adreg:REGISTER:VEC:SINGLE
mov z1.s,p1/m,z2.s
### op move [MASK] amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE{BCAST} adreg:REGISTER:FP:SINGLE
mov z1.s,p1/m,s1
### op move [MASK] amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE{BCAST} adreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.s,p1/m,z2.s[0]
### op move [MASK] amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE{BCAST} adreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.s,p1/m,z2.s[15]
### op move [MASK] amreg:REGISTER:MASK:SINT16 adreg:REGISTER:TILE:SINT16{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:VEC:SINT16
mova z1.h,p1/m,za0v.h[w12,0]
### op move [MASK] amreg:REGISTER:MASK:SINT16 adreg:REGISTER:TILE:SINT16{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:VEC:SINT16
mova z1.h,p1/m,za0h.h[w12,0]
### op move [MASK] amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:TILE:SINT16{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:-
mova za0v.h[w12,0],p1/m,z1.h
### op move [MASK] amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:TILE:SINT16{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- @far
mova za0v.h[w12,7],p1/m,z1.h
### op move [MASK] amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:TILE:SINT16{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:-
mova za0h.h[w12,0],p1/m,z1.h
### op move [MASK] amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:TILE:SINT16{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- @far
mova za0h.h[w12,7],p1/m,z1.h
### op move [MASK] amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 adreg:REGISTER:VEC:SINT16
mov z1.h,p1/m,z2.h
### op move [MASK] amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16{BCAST} adreg:REGISTER:GP:SINT16
mov z1.h,p1/m,w10
### op move [MASK] amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16{BCAST} adreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.h,p1/m,z2.h[0]
### op move [MASK] amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16{BCAST} adreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.h,p1/m,z2.h[31]
### op move [MASK] amreg:REGISTER:MASK:SINT32 adreg:REGISTER:TILE:SINT32{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:VEC:SINT32
mova z1.s,p1/m,za0v.s[w12,0]
### op move [MASK] amreg:REGISTER:MASK:SINT32 adreg:REGISTER:TILE:SINT32{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:VEC:SINT32
mova z1.s,p1/m,za0h.s[w12,0]
### op move [MASK] amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:TILE:SINT32{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:-
mova za0v.s[w12,0],p1/m,z1.s
### op move [MASK] amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:TILE:SINT32{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- @far
mova za0v.s[w12,3],p1/m,z1.s
### op move [MASK] amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:TILE:SINT32{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:-
mova za0h.s[w12,0],p1/m,z1.s
### op move [MASK] amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:TILE:SINT32{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- @far
mova za0h.s[w12,3],p1/m,z1.s
### op move [MASK] amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 adreg:REGISTER:VEC:SINT32
mov z1.s,p1/m,z2.s
### op move [MASK] amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32{BCAST} adreg:REGISTER:GP:SINT32
mov z1.s,p1/m,w10
### op move [MASK] amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32{BCAST} adreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.s,p1/m,z2.s[0]
### op move [MASK] amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32{BCAST} adreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.s,p1/m,z2.s[15]
### op move [MASK] amreg:REGISTER:MASK:SINT64 adreg:REGISTER:TILE:SINT64{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:VEC:SINT64
mova z1.d,p1/m,za0v.d[w12,0]
### op move [MASK] amreg:REGISTER:MASK:SINT64 adreg:REGISTER:TILE:SINT64{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:VEC:SINT64
mova z1.d,p1/m,za0h.d[w12,0]
### op move [MASK] amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:TILE:SINT64{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:-
mova za0v.d[w12,0],p1/m,z1.d
### op move [MASK] amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:TILE:SINT64{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- @far
mova za0v.d[w12,1],p1/m,z1.d
### op move [MASK] amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:TILE:SINT64{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:-
mova za0h.d[w12,0],p1/m,z1.d
### op move [MASK] amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:TILE:SINT64{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- @far
mova za0h.d[w12,1],p1/m,z1.d
### op move [MASK] amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 adreg:REGISTER:VEC:SINT64
mov z1.d,p1/m,z2.d
### op move [MASK] amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64{BCAST} adreg:REGISTER:GP:SINT64
mov z1.d,p1/m,x10
### op move [MASK] amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64{BCAST} adreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.d,p1/m,z2.d[0]
### op move [MASK] amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64{BCAST} adreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.d,p1/m,z2.d[7]
### op move [MASK] amreg:REGISTER:MASK:SINT8 adreg:REGISTER:TILE:SINT8{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:VEC:SINT8
mova z1.b,p1/m,za0v.b[w12,0]
### op move [MASK] amreg:REGISTER:MASK:SINT8 adreg:REGISTER:TILE:SINT8{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:VEC:SINT8
mova z1.b,p1/m,za0h.b[w12,0]
### op move [MASK] amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:TILE:SINT8{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:-
mova za0v.b[w12,0],p1/m,z1.b
### op move [MASK] amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:TILE:SINT8{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- @far
mova za0v.b[w12,15],p1/m,z1.b
### op move [MASK] amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:TILE:SINT8{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:-
mova za0h.b[w12,0],p1/m,z1.b
### op move [MASK] amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:TILE:SINT8{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- @far
mova za0h.b[w12,15],p1/m,z1.b
### op move [MASK] amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 adreg:REGISTER:VEC:SINT8
mov z1.b,p1/m,z2.b
### op move [MASK] amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8{BCAST} adreg:REGISTER:GP:SINT8
mov z1.b,p1/m,w10
### op move [MASK] amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8{BCAST} adreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.b,p1/m,z2.b[0]
### op move [MASK] amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8{BCAST} adreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.b,p1/m,z2.b[63]
### op move [MASK] amreg:REGISTER:MASK:UINT16 adreg:REGISTER:TILE:UINT16{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:VEC:UINT16
mova z1.h,p1/m,za0v.h[w12,0]
### op move [MASK] amreg:REGISTER:MASK:UINT16 adreg:REGISTER:TILE:UINT16{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:VEC:UINT16
mova z1.h,p1/m,za0h.h[w12,0]
### op move [MASK] amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:TILE:UINT16{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:-
mova za0v.h[w12,0],p1/m,z1.h
### op move [MASK] amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:TILE:UINT16{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- @far
mova za0v.h[w12,7],p1/m,z1.h
### op move [MASK] amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:TILE:UINT16{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:-
mova za0h.h[w12,0],p1/m,z1.h
### op move [MASK] amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:TILE:UINT16{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- @far
mova za0h.h[w12,7],p1/m,z1.h
### op move [MASK] amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 adreg:REGISTER:VEC:UINT16
mov z1.h,p1/m,z2.h
### op move [MASK] amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16{BCAST} adreg:REGISTER:GP:UINT16
mov z1.h,p1/m,w10
### op move [MASK] amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16{BCAST} adreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.h,p1/m,z2.h[0]
### op move [MASK] amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16{BCAST} adreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.h,p1/m,z2.h[31]
### op move [MASK] amreg:REGISTER:MASK:UINT32 adreg:REGISTER:TILE:UINT32{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:VEC:UINT32
mova z1.s,p1/m,za0v.s[w12,0]
### op move [MASK] amreg:REGISTER:MASK:UINT32 adreg:REGISTER:TILE:UINT32{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:VEC:UINT32
mova z1.s,p1/m,za0h.s[w12,0]
### op move [MASK] amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:TILE:UINT32{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:-
mova za0v.s[w12,0],p1/m,z1.s
### op move [MASK] amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:TILE:UINT32{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- @far
mova za0v.s[w12,3],p1/m,z1.s
### op move [MASK] amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:TILE:UINT32{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:-
mova za0h.s[w12,0],p1/m,z1.s
### op move [MASK] amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:TILE:UINT32{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- @far
mova za0h.s[w12,3],p1/m,z1.s
### op move [MASK] amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 adreg:REGISTER:VEC:UINT32
mov z1.s,p1/m,z2.s
### op move [MASK] amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32{BCAST} adreg:REGISTER:GP:UINT32
mov z1.s,p1/m,w10
### op move [MASK] amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32{BCAST} adreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.s,p1/m,z2.s[0]
### op move [MASK] amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32{BCAST} adreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.s,p1/m,z2.s[15]
### op move [MASK] amreg:REGISTER:MASK:UINT64 adreg:REGISTER:TILE:UINT64{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:VEC:UINT64
mova z1.d,p1/m,za0v.d[w12,0]
### op move [MASK] amreg:REGISTER:MASK:UINT64 adreg:REGISTER:TILE:UINT64{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:VEC:UINT64
mova z1.d,p1/m,za0h.d[w12,0]
### op move [MASK] amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:TILE:UINT64{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:-
mova za0v.d[w12,0],p1/m,z1.d
### op move [MASK] amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:TILE:UINT64{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- @far
mova za0v.d[w12,1],p1/m,z1.d
### op move [MASK] amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:TILE:UINT64{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:-
mova za0h.d[w12,0],p1/m,z1.d
### op move [MASK] amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:TILE:UINT64{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- @far
mova za0h.d[w12,1],p1/m,z1.d
### op move [MASK] amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 adreg:REGISTER:VEC:UINT64
mov z1.d,p1/m,z2.d
### op move [MASK] amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64{BCAST} adreg:REGISTER:GP:UINT64
mov z1.d,p1/m,x10
### op move [MASK] amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64{BCAST} adreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.d,p1/m,z2.d[0]
### op move [MASK] amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64{BCAST} adreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.d,p1/m,z2.d[7]
### op move [MASK] amreg:REGISTER:MASK:UINT8 adreg:REGISTER:TILE:UINT8{COL} adreg_immcol:IMMEDIATE:-:- adreg_colreg:REGISTER:GP:- bdreg:REGISTER:VEC:UINT8
mova z1.b,p1/m,za0v.b[w12,0]
### op move [MASK] amreg:REGISTER:MASK:UINT8 adreg:REGISTER:TILE:UINT8{ROW} adreg_immrow:IMMEDIATE:-:- adreg_rowreg:REGISTER:GP:- bdreg:REGISTER:VEC:UINT8
mova z1.b,p1/m,za0h.b[w12,0]
### op move [MASK] amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:TILE:UINT8{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:-
mova za0v.b[w12,0],p1/m,z1.b
### op move [MASK] amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:TILE:UINT8{COL} bdreg_immcol:IMMEDIATE:-:- bdreg_colreg:REGISTER:GP:- @far
mova za0v.b[w12,15],p1/m,z1.b
### op move [MASK] amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:TILE:UINT8{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:-
mova za0h.b[w12,0],p1/m,z1.b
### op move [MASK] amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:TILE:UINT8{ROW} bdreg_immrow:IMMEDIATE:-:- bdreg_rowreg:REGISTER:GP:- @far
mova za0h.b[w12,15],p1/m,z1.b
### op move [MASK] amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 adreg:REGISTER:VEC:UINT8
mov z1.b,p1/m,z2.b
### op move [MASK] amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8{BCAST} adreg:REGISTER:GP:UINT8
mov z1.b,p1/m,w10
### op move [MASK] amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8{BCAST} adreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.b,p1/m,z2.b[0]
### op move [MASK] amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8{BCAST} adreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.b,p1/m,z2.b[63]
### op move [] adreg:REGISTER:FP:DOUBLE bdreg:REGISTER:FP:DOUBLE
fmov d2,d1
### op move [] adreg:REGISTER:FP:DOUBLE bdreg:REGISTER:VEC:DOUBLE{FILLOTHERS,ILANESHIFT} bdreg_irot:IMMEDIATE:-:-
insr z1.d,d1
### op move [] adreg:REGISTER:FP:HALF bdreg:REGISTER:FP:HALF
fmov h2,h1
### op move [] adreg:REGISTER:FP:HALF bdreg:REGISTER:VEC:HALF{FILLOTHERS,ILANESHIFT} bdreg_irot:IMMEDIATE:-:-
insr z1.h,h1
### op move [] adreg:REGISTER:FP:SINGLE bdreg:REGISTER:FP:SINGLE
fmov s2,s1
### op move [] adreg:REGISTER:FP:SINGLE bdreg:REGISTER:VEC:SINGLE{FILLOTHERS,ILANESHIFT} bdreg_irot:IMMEDIATE:-:-
insr z1.s,s1
### op move [] adreg:REGISTER:GP:SINT16 bdreg:REGISTER:VEC:SINT16{FILLOTHERS,ILANESHIFT} bdreg_irot:IMMEDIATE:-:-
insr z1.h,x10
### op move [] adreg:REGISTER:GP:SINT32 bdreg:REGISTER:VEC:SINT32{FILLOTHERS,ILANESHIFT} bdreg_irot:IMMEDIATE:-:-
insr z1.s,x10
### op move [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64
mov x11,x10
### op move [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:VEC:SINT64{FILLOTHERS,ILANESHIFT} bdreg_irot:IMMEDIATE:-:-
insr z1.d,x10
### op move [] adreg:REGISTER:GP:SINT8 bdreg:REGISTER:VEC:SINT8{FILLOTHERS,ILANESHIFT} bdreg_irot:IMMEDIATE:-:-
insr z1.b,x10
### op move [] adreg:REGISTER:GP:UINT16 bdreg:REGISTER:VEC:UINT16{FILLOTHERS,ILANESHIFT} bdreg_irot:IMMEDIATE:-:-
insr z1.h,x10
### op move [] adreg:REGISTER:GP:UINT32 bdreg:REGISTER:VEC:UINT32{FILLOTHERS,ILANESHIFT} bdreg_irot:IMMEDIATE:-:-
insr z1.s,x10
### op move [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64
mov x11,x10
### op move [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:VEC:UINT64{FILLOTHERS,ILANESHIFT} bdreg_irot:IMMEDIATE:-:-
insr z1.d,x10
### op move [] adreg:REGISTER:GP:UINT8 bdreg:REGISTER:VEC:UINT8{FILLOTHERS,ILANESHIFT} bdreg_irot:IMMEDIATE:-:-
insr z1.b,x10
### op move [] adreg:REGISTER:VEC:BF16{IBLOCKROT} bdreg:REGISTER:VEC:BF16 adreg_irot:IMMEDIATE:-:- {adreg_blocksize:8}
ext z1.b,z1.b,z1.b,#240
### op move [] adreg:REGISTER:VEC:BF16{IBLOCKROT} bdreg:REGISTER:VEC:BF16 adreg_irot:IMMEDIATE:-:- {adreg_blocksize:8} @far
ext z1.b,z1.b,z1.b,#16
### op move [] adreg:REGISTER:VEC:BF16{ILANEROT} bdreg:REGISTER:VEC:BF16 adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#254
### op move [] adreg:REGISTER:VEC:BF16{ILANEROT} bdreg:REGISTER:VEC:BF16 adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#2
### op move [] adreg:REGISTER:VEC:BF16{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:BF16 adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#254
### op move [] adreg:REGISTER:VEC:BF16{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:BF16 adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#2
### op move [] adreg:REGISTER:VEC:DOUBLE{FILLOTHERS,ILANESHIFT} bdreg:REGISTER:VEC:DOUBLE adreg_irot:IMMEDIATE:-:- fillreg:REGISTER:FP:DOUBLE
!ValueError: Invalid configuration for sme_move.
### op move [] adreg:REGISTER:VEC:DOUBLE{IBLOCKROT} bdreg:REGISTER:VEC:DOUBLE adreg_irot:IMMEDIATE:-:- {adreg_blocksize:2}
ext z1.b,z1.b,z1.b,#240
### op move [] adreg:REGISTER:VEC:DOUBLE{IBLOCKROT} bdreg:REGISTER:VEC:DOUBLE adreg_irot:IMMEDIATE:-:- {adreg_blocksize:2} @far
ext z1.b,z1.b,z1.b,#16
### op move [] adreg:REGISTER:VEC:DOUBLE{ILANEROT} bdreg:REGISTER:VEC:DOUBLE adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#248
### op move [] adreg:REGISTER:VEC:DOUBLE{ILANEROT} bdreg:REGISTER:VEC:DOUBLE adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#8
### op move [] adreg:REGISTER:VEC:DOUBLE{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:DOUBLE adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#248
### op move [] adreg:REGISTER:VEC:DOUBLE{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:DOUBLE adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#8
### op move [] adreg:REGISTER:VEC:DOUBLE{ILANE} bdreg:REGISTER:FP:DOUBLE adreg_lane:IMMEDIATE:-:-
fmov d1,d1
### op move [] adreg:REGISTER:VEC:FP8E4M3{IBLOCKROT} bdreg:REGISTER:VEC:FP8E4M3 adreg_irot:IMMEDIATE:-:- {adreg_blocksize:16}
ext z1.b,z1.b,z1.b,#240
### op move [] adreg:REGISTER:VEC:FP8E4M3{IBLOCKROT} bdreg:REGISTER:VEC:FP8E4M3 adreg_irot:IMMEDIATE:-:- {adreg_blocksize:16} @far
ext z1.b,z1.b,z1.b,#16
### op move [] adreg:REGISTER:VEC:FP8E4M3{ILANEROT} bdreg:REGISTER:VEC:FP8E4M3 adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#255
### op move [] adreg:REGISTER:VEC:FP8E4M3{ILANEROT} bdreg:REGISTER:VEC:FP8E4M3 adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#1
### op move [] adreg:REGISTER:VEC:FP8E4M3{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:FP8E4M3 adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#255
### op move [] adreg:REGISTER:VEC:FP8E4M3{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:FP8E4M3 adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#1
### op move [] adreg:REGISTER:VEC:FP8E5M2{IBLOCKROT} bdreg:REGISTER:VEC:FP8E5M2 adreg_irot:IMMEDIATE:-:- {adreg_blocksize:16}
ext z1.b,z1.b,z1.b,#240
### op move [] adreg:REGISTER:VEC:FP8E5M2{IBLOCKROT} bdreg:REGISTER:VEC:FP8E5M2 adreg_irot:IMMEDIATE:-:- {adreg_blocksize:16} @far
ext z1.b,z1.b,z1.b,#16
### op move [] adreg:REGISTER:VEC:FP8E5M2{ILANEROT} bdreg:REGISTER:VEC:FP8E5M2 adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#255
### op move [] adreg:REGISTER:VEC:FP8E5M2{ILANEROT} bdreg:REGISTER:VEC:FP8E5M2 adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#1
### op move [] adreg:REGISTER:VEC:FP8E5M2{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:FP8E5M2 adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#255
### op move [] adreg:REGISTER:VEC:FP8E5M2{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:FP8E5M2 adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#1
### op move [] adreg:REGISTER:VEC:HALF{FILLOTHERS,ILANESHIFT} bdreg:REGISTER:VEC:HALF adreg_irot:IMMEDIATE:-:- fillreg:REGISTER:FP:HALF
!ValueError: Invalid configuration for sme_move.
### op move [] adreg:REGISTER:VEC:HALF{IBLOCKROT} bdreg:REGISTER:VEC:HALF adreg_irot:IMMEDIATE:-:- {adreg_blocksize:8}
ext z1.b,z1.b,z1.b,#240
### op move [] adreg:REGISTER:VEC:HALF{IBLOCKROT} bdreg:REGISTER:VEC:HALF adreg_irot:IMMEDIATE:-:- {adreg_blocksize:8} @far
ext z1.b,z1.b,z1.b,#16
### op move [] adreg:REGISTER:VEC:HALF{ILANEROT} bdreg:REGISTER:VEC:HALF adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#254
### op move [] adreg:REGISTER:VEC:HALF{ILANEROT} bdreg:REGISTER:VEC:HALF adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#2
### op move [] adreg:REGISTER:VEC:HALF{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:HALF adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#254
### op move [] adreg:REGISTER:VEC:HALF{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:HALF adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#2
### op move [] adreg:REGISTER:VEC:HALF{ILANE} bdreg:REGISTER:FP:HALF adreg_lane:IMMEDIATE:-:-
fmov h1,h1
### op move [] adreg:REGISTER:VEC:SINGLE{FILLOTHERS,ILANESHIFT} bdreg:REGISTER:VEC:SINGLE adreg_irot:IMMEDIATE:-:- fillreg:REGISTER:FP:SINGLE
!ValueError: Invalid configuration for sme_move.
### op move [] adreg:REGISTER:VEC:SINGLE{IBLOCKROT} bdreg:REGISTER:VEC:SINGLE adreg_irot:IMMEDIATE:-:- {adreg_blocksize:4}
ext z1.b,z1.b,z1.b,#240
### op move [] adreg:REGISTER:VEC:SINGLE{IBLOCKROT} bdreg:REGISTER:VEC:SINGLE adreg_irot:IMMEDIATE:-:- {adreg_blocksize:4} @far
ext z1.b,z1.b,z1.b,#16
### op move [] adreg:REGISTER:VEC:SINGLE{ILANEROT} bdreg:REGISTER:VEC:SINGLE adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#252
### op move [] adreg:REGISTER:VEC:SINGLE{ILANEROT} bdreg:REGISTER:VEC:SINGLE adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#4
### op move [] adreg:REGISTER:VEC:SINGLE{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINGLE adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#252
### op move [] adreg:REGISTER:VEC:SINGLE{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINGLE adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#4
### op move [] adreg:REGISTER:VEC:SINGLE{ILANE} bdreg:REGISTER:FP:SINGLE adreg_lane:IMMEDIATE:-:-
fmov s1,s1
### op move [] adreg:REGISTER:VEC:SINT16{FILLOTHERS,ILANESHIFT} bdreg:REGISTER:VEC:SINT16 adreg_irot:IMMEDIATE:-:- fillreg:REGISTER:GP:SINT16
!ValueError: Invalid configuration for sme_move.
### op move [] adreg:REGISTER:VEC:SINT16{IBLOCKROT} bdreg:REGISTER:VEC:SINT16 adreg_irot:IMMEDIATE:-:- {adreg_blocksize:8}
ext z1.b,z1.b,z1.b,#240
### op move [] adreg:REGISTER:VEC:SINT16{IBLOCKROT} bdreg:REGISTER:VEC:SINT16 adreg_irot:IMMEDIATE:-:- {adreg_blocksize:8} @far
ext z1.b,z1.b,z1.b,#16
### op move [] adreg:REGISTER:VEC:SINT16{ILANEROT} bdreg:REGISTER:VEC:SINT16 adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#254
### op move [] adreg:REGISTER:VEC:SINT16{ILANEROT} bdreg:REGISTER:VEC:SINT16 adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#2
### op move [] adreg:REGISTER:VEC:SINT16{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINT16 adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#254
### op move [] adreg:REGISTER:VEC:SINT16{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINT16 adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#2
### op move [] adreg:REGISTER:VEC:SINT32{FILLOTHERS,ILANESHIFT} bdreg:REGISTER:VEC:SINT32 adreg_irot:IMMEDIATE:-:- fillreg:REGISTER:GP:SINT32
!ValueError: Invalid configuration for sme_move.
### op move [] adreg:REGISTER:VEC:SINT32{IBLOCKROT} bdreg:REGISTER:VEC:SINT32 adreg_irot:IMMEDIATE:-:- {adreg_blocksize:4}
ext z1.b,z1.b,z1.b,#240
### op move [] adreg:REGISTER:VEC:SINT32{IBLOCKROT} bdreg:REGISTER:VEC:SINT32 adreg_irot:IMMEDIATE:-:- {adreg_blocksize:4} @far
ext z1.b,z1.b,z1.b,#16
### op move [] adreg:REGISTER:VEC:SINT32{ILANEROT} bdreg:REGISTER:VEC:SINT32 adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#252
### op move [] adreg:REGISTER:VEC:SINT32{ILANEROT} bdreg:REGISTER:VEC:SINT32 adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#4
### op move [] adreg:REGISTER:VEC:SINT32{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINT32 adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#252
### op move [] adreg:REGISTER:VEC:SINT32{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINT32 adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#4
### op move [] adreg:REGISTER:VEC:SINT64{FILLOTHERS,ILANESHIFT} bdreg:REGISTER:VEC:SINT64 adreg_irot:IMMEDIATE:-:- fillreg:REGISTER:GP:SINT64
!ValueError: Invalid configuration for sme_move.
### op move [] adreg:REGISTER:VEC:SINT64{IBLOCKROT} bdreg:REGISTER:VEC:SINT64 adreg_irot:IMMEDIATE:-:- {adreg_blocksize:2}
ext z1.b,z1.b,z1.b,#240
### op move [] adreg:REGISTER:VEC:SINT64{IBLOCKROT} bdreg:REGISTER:VEC:SINT64 adreg_irot:IMMEDIATE:-:- {adreg_blocksize:2} @far
ext z1.b,z1.b,z1.b,#16
### op move [] adreg:REGISTER:VEC:SINT64{ILANEROT} bdreg:REGISTER:VEC:SINT64 adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#248
### op move [] adreg:REGISTER:VEC:SINT64{ILANEROT} bdreg:REGISTER:VEC:SINT64 adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#8
### op move [] adreg:REGISTER:VEC:SINT64{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINT64 adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#248
### op move [] adreg:REGISTER:VEC:SINT64{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINT64 adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#8
### op move [] adreg:REGISTER:VEC:SINT8{FILLOTHERS,ILANESHIFT} bdreg:REGISTER:VEC:SINT8 adreg_irot:IMMEDIATE:-:- fillreg:REGISTER:GP:SINT8
!ValueError: Invalid configuration for sme_move.
### op move [] adreg:REGISTER:VEC:SINT8{IBLOCKROT} bdreg:REGISTER:VEC:SINT8 adreg_irot:IMMEDIATE:-:- {adreg_blocksize:16}
ext z1.b,z1.b,z1.b,#240
### op move [] adreg:REGISTER:VEC:SINT8{IBLOCKROT} bdreg:REGISTER:VEC:SINT8 adreg_irot:IMMEDIATE:-:- {adreg_blocksize:16} @far
ext z1.b,z1.b,z1.b,#16
### op move [] adreg:REGISTER:VEC:SINT8{ILANEROT} bdreg:REGISTER:VEC:SINT8 adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#255
### op move [] adreg:REGISTER:VEC:SINT8{ILANEROT} bdreg:REGISTER:VEC:SINT8 adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#1
### op move [] adreg:REGISTER:VEC:SINT8{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINT8 adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#255
### op move [] adreg:REGISTER:VEC:SINT8{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:SINT8 adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#1
### op move [] adreg:REGISTER:VEC:UINT16{FILLOTHERS,ILANESHIFT} bdreg:REGISTER:VEC:UINT16 adreg_irot:IMMEDIATE:-:- fillreg:REGISTER:GP:UINT16
!ValueError: Invalid configuration for sme_move.
### op move [] adreg:REGISTER:VEC:UINT16{IBLOCKROT} bdreg:REGISTER:VEC:UINT16 adreg_irot:IMMEDIATE:-:- {adreg_blocksize:8}
ext z1.b,z1.b,z1.b,#240
### op move [] adreg:REGISTER:VEC:UINT16{IBLOCKROT} bdreg:REGISTER:VEC:UINT16 adreg_irot:IMMEDIATE:-:- {adreg_blocksize:8} @far
ext z1.b,z1.b,z1.b,#16
### op move [] adreg:REGISTER:VEC:UINT16{ILANEROT} bdreg:REGISTER:VEC:UINT16 adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#254
### op move [] adreg:REGISTER:VEC:UINT16{ILANEROT} bdreg:REGISTER:VEC:UINT16 adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#2
### op move [] adreg:REGISTER:VEC:UINT16{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:UINT16 adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#254
### op move [] adreg:REGISTER:VEC:UINT16{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:UINT16 adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#2
### op move [] adreg:REGISTER:VEC:UINT32{FILLOTHERS,ILANESHIFT} bdreg:REGISTER:VEC:UINT32 adreg_irot:IMMEDIATE:-:- fillreg:REGISTER:GP:UINT32
!ValueError: Invalid configuration for sme_move.
### op move [] adreg:REGISTER:VEC:UINT32{IBLOCKROT} bdreg:REGISTER:VEC:UINT32 adreg_irot:IMMEDIATE:-:- {adreg_blocksize:4}
ext z1.b,z1.b,z1.b,#240
### op move [] adreg:REGISTER:VEC:UINT32{IBLOCKROT} bdreg:REGISTER:VEC:UINT32 adreg_irot:IMMEDIATE:-:- {adreg_blocksize:4} @far
ext z1.b,z1.b,z1.b,#16
### op move [] adreg:REGISTER:VEC:UINT32{ILANEROT} bdreg:REGISTER:VEC:UINT32 adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#252
### op move [] adreg:REGISTER:VEC:UINT32{ILANEROT} bdreg:REGISTER:VEC:UINT32 adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#4
### op move [] adreg:REGISTER:VEC:UINT32{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:UINT32 adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#252
### op move [] adreg:REGISTER:VEC:UINT32{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:UINT32 adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#4
### op move [] adreg:REGISTER:VEC:UINT64{FILLOTHERS,ILANESHIFT} bdreg:REGISTER:VEC:UINT64 adreg_irot:IMMEDIATE:-:- fillreg:REGISTER:GP:UINT64
!ValueError: Invalid configuration for sme_move.
### op move [] adreg:REGISTER:VEC:UINT64{IBLOCKROT} bdreg:REGISTER:VEC:UINT64 adreg_irot:IMMEDIATE:-:- {adreg_blocksize:2}
ext z1.b,z1.b,z1.b,#240
### op move [] adreg:REGISTER:VEC:UINT64{IBLOCKROT} bdreg:REGISTER:VEC:UINT64 adreg_irot:IMMEDIATE:-:- {adreg_blocksize:2} @far
ext z1.b,z1.b,z1.b,#16
### op move [] adreg:REGISTER:VEC:UINT64{ILANEROT} bdreg:REGISTER:VEC:UINT64 adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#248
### op move [] adreg:REGISTER:VEC:UINT64{ILANEROT} bdreg:REGISTER:VEC:UINT64 adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#8
### op move [] adreg:REGISTER:VEC:UINT64{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:UINT64 adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#248
### op move [] adreg:REGISTER:VEC:UINT64{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:UINT64 adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#8
### op move [] adreg:REGISTER:VEC:UINT8{FILLOTHERS,ILANESHIFT} bdreg:REGISTER:VEC:UINT8 adreg_irot:IMMEDIATE:-:- fillreg:REGISTER:GP:UINT8
!ValueError: Invalid configuration for sme_move.
### op move [] adreg:REGISTER:VEC:UINT8{IBLOCKROT} bdreg:REGISTER:VEC:UINT8 adreg_irot:IMMEDIATE:-:- {adreg_blocksize:16}
ext z1.b,z1.b,z1.b,#240
### op move [] adreg:REGISTER:VEC:UINT8{IBLOCKROT} bdreg:REGISTER:VEC:UINT8 adreg_irot:IMMEDIATE:-:- {adreg_blocksize:16} @far
ext z1.b,z1.b,z1.b,#16
### op move [] adreg:REGISTER:VEC:UINT8{ILANEROT} bdreg:REGISTER:VEC:UINT8 adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#255
### op move [] adreg:REGISTER:VEC:UINT8{ILANEROT} bdreg:REGISTER:VEC:UINT8 adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#1
### op move [] adreg:REGISTER:VEC:UINT8{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:UINT8 adreg_irot:IMMEDIATE:-:-
ext z1.b,z1.b,z1.b,#255
### op move [] adreg:REGISTER:VEC:UINT8{ILANESHIFT,INVALIDOTHERS} bdreg:REGISTER:VEC:UINT8 adreg_irot:IMMEDIATE:-:- @far
ext z1.b,z1.b,z1.b,#1
### op move [] bdreg:REGISTER:VEC:BF16 adreg:REGISTER:VEC:BF16
!KeyError: <asm_data_type.BF16: 5>
### op move [] bdreg:REGISTER:VEC:BF16{BCAST,BLOCK} adreg:REGISTER:VEC:BF16{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:8,bdreg_blocksize:8}
dup z1.q,z2.q[0]
### op move [] bdreg:REGISTER:VEC:BF16{BCAST,BLOCK} adreg:REGISTER:VEC:BF16{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:8,bdreg_blocksize:8} @far
dup z1.q,z2.q[3]
### op move [] bdreg:REGISTER:VEC:BF16{BCAST} adreg:REGISTER:FP:BF16
!KeyError: <asm_data_type.BF16: 5>
### op move [] bdreg:REGISTER:VEC:BF16{BCAST} adreg:REGISTER:VEC:BF16{ILANE} adreg_lane:IMMEDIATE:-:-
!KeyError: <asm_data_type.BF16: 5>
### op move [] bdreg:REGISTER:VEC:BF16{BCAST} adreg:REGISTER:VEC:BF16{ILANE} adreg_lane:IMMEDIATE:-:- @far
!KeyError: <asm_data_type.BF16: 5>
### op move [] bdreg:REGISTER:VEC:DOUBLE adreg:REGISTER:VEC:DOUBLE
mov z1.d,z2.d
### op move [] bdreg:REGISTER:VEC:DOUBLE{BCAST,BLOCK} adreg:REGISTER:VEC:DOUBLE{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:2,bdreg_blocksize:2}
dup z1.q,z2.q[0]
### op move [] bdreg:REGISTER:VEC:DOUBLE{BCAST,BLOCK} adreg:REGISTER:VEC:DOUBLE{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:2,bdreg_blocksize:2} @far
dup z1.q,z2.q[3]
### op move [] bdreg:REGISTER:VEC:DOUBLE{BCAST} adreg:REGISTER:FP:DOUBLE
mov z1.d,d1
### op move [] bdreg:REGISTER:VEC:DOUBLE{BCAST} adreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.d,z2.d[0]
### op move [] bdreg:REGISTER:VEC:DOUBLE{BCAST} adreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.d,z2.d[7]
### op move [] bdreg:REGISTER:VEC:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3
mov z1.d,z2.d
### op move [] bdreg:REGISTER:VEC:FP8E4M3{BCAST,BLOCK} adreg:REGISTER:VEC:FP8E4M3{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:16,bdreg_blocksize:16}
dup z1.q,z2.q[0]
### op move [] bdreg:REGISTER:VEC:FP8E4M3{BCAST,BLOCK} adreg:REGISTER:VEC:FP8E4M3{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:16,bdreg_blocksize:16} @far
dup z1.q,z2.q[3]
### op move [] bdreg:REGISTER:VEC:FP8E4M3{BCAST} adreg:REGISTER:FP:FP8E4M3
mov z1.b,b1
### op move [] bdreg:REGISTER:VEC:FP8E4M3{BCAST} adreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.b,z2.b[0]
### op move [] bdreg:REGISTER:VEC:FP8E4M3{BCAST} adreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.b,z2.b[63]
### op move [] bdreg:REGISTER:VEC:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2
mov z1.d,z2.d
### op move [] bdreg:REGISTER:VEC:FP8E5M2{BCAST,BLOCK} adreg:REGISTER:VEC:FP8E5M2{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:16,bdreg_blocksize:16}
dup z1.q,z2.q[0]
### op move [] bdreg:REGISTER:VEC:FP8E5M2{BCAST,BLOCK} adreg:REGISTER:VEC:FP8E5M2{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:16,bdreg_blocksize:16} @far
dup z1.q,z2.q[3]
### op move [] bdreg:REGISTER:VEC:FP8E5M2{BCAST} adreg:REGISTER:FP:FP8E5M2
mov z1.b,b1
### op move [] bdreg:REGISTER:VEC:FP8E5M2{BCAST} adreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.b,z2.b[0]
### op move [] bdreg:REGISTER:VEC:FP8E5M2{BCAST} adreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.b,z2.b[63]
### op move [] bdreg:REGISTER:VEC:HALF adreg:REGISTER:VEC:HALF
mov z1.d,z2.d
### op move [] bdreg:REGISTER:VEC:HALF{BCAST,BLOCK} adreg:REGISTER:VEC:HALF{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:8,bdreg_blocksize:8}
dup z1.q,z2.q[0]
### op move [] bdreg:REGISTER:VEC:HALF{BCAST,BLOCK} adreg:REGISTER:VEC:HALF{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:8,bdreg_blocksize:8} @far
dup z1.q,z2.q[3]
### op move [] bdreg:REGISTER:VEC:HALF{BCAST} adreg:REGISTER:FP:HALF
mov z1.h,h1
### op move [] bdreg:REGISTER:VEC:HALF{BCAST} adreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.h,z2.h[0]
### op move [] bdreg:REGISTER:VEC:HALF{BCAST} adreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.h,z2.h[31]
### op move [] bdreg:REGISTER:VEC:SINGLE adreg:REGISTER:VEC:SINGLE
mov z1.d,z2.d
### op move [] bdreg:REGISTER:VEC:SINGLE{BCAST,BLOCK} adreg:REGISTER:VEC:SINGLE{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:4,bdreg_blocksize:4}
dup z1.q,z2.q[0]
### op move [] bdreg:REGISTER:VEC:SINGLE{BCAST,BLOCK} adreg:REGISTER:VEC:SINGLE{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:4,bdreg_blocksize:4} @far
dup z1.q,z2.q[3]
### op move [] bdreg:REGISTER:VEC:SINGLE{BCAST} adreg:REGISTER:FP:SINGLE
mov z1.s,s1
### op move [] bdreg:REGISTER:VEC:SINGLE{BCAST} adreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.s,z2.s[0]
### op move [] bdreg:REGISTER:VEC:SINGLE{BCAST} adreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.s,z2.s[15]
### op move [] bdreg:REGISTER:VEC:SINT16 adreg:REGISTER:VEC:SINT16
mov z1.d,z2.d
### op move [] bdreg:REGISTER:VEC:SINT16{BCAST,BLOCK} adreg:REGISTER:VEC:SINT16{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:8,bdreg_blocksize:8}
dup z1.q,z2.q[0]
### op move [] bdreg:REGISTER:VEC:SINT16{BCAST,BLOCK} adreg:REGISTER:VEC:SINT16{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:8,bdreg_blocksize:8} @far
dup z1.q,z2.q[3]
### op move [] bdreg:REGISTER:VEC:SINT16{BCAST} adreg:REGISTER:GP:SINT16
mov z1.h,w10
### op move [] bdreg:REGISTER:VEC:SINT16{BCAST} adreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.h,z2.h[0]
### op move [] bdreg:REGISTER:VEC:SINT16{BCAST} adreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.h,z2.h[31]
### op move [] bdreg:REGISTER:VEC:SINT32 adreg:REGISTER:VEC:SINT32
mov z1.d,z2.d
### op move [] bdreg:REGISTER:VEC:SINT32{BCAST,BLOCK} adreg:REGISTER:VEC:SINT32{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:4,bdreg_blocksize:4}
dup z1.q,z2.q[0]
### op move [] bdreg:REGISTER:VEC:SINT32{BCAST,BLOCK} adreg:REGISTER:VEC:SINT32{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:4,bdreg_blocksize:4} @far
dup z1.q,z2.q[3]
### op move [] bdreg:REGISTER:VEC:SINT32{BCAST} adreg:REGISTER:GP:SINT32
mov z1.s,w10
### op move [] bdreg:REGISTER:VEC:SINT32{BCAST} adreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.s,z2.s[0]
### op move [] bdreg:REGISTER:VEC:SINT32{BCAST} adreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.s,z2.s[15]
### op move [] bdreg:REGISTER:VEC:SINT64 adreg:REGISTER:VEC:SINT64
mov z1.d,z2.d
### op move [] bdreg:REGISTER:VEC:SINT64{BCAST,BLOCK} adreg:REGISTER:VEC:SINT64{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:2,bdreg_blocksize:2}
dup z1.q,z2.q[0]
### op move [] bdreg:REGISTER:VEC:SINT64{BCAST,BLOCK} adreg:REGISTER:VEC:SINT64{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:2,bdreg_blocksize:2} @far
dup z1.q,z2.q[3]
### op move [] bdreg:REGISTER:VEC:SINT64{BCAST} adreg:REGISTER:GP:SINT64
mov z1.d,x10
### op move [] bdreg:REGISTER:VEC:SINT64{BCAST} adreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.d,z2.d[0]
### op move [] bdreg:REGISTER:VEC:SINT64{BCAST} adreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.d,z2.d[7]
### op move [] bdreg:REGISTER:VEC:SINT8 adreg:REGISTER:VEC:SINT8
mov z1.d,z2.d
### op move [] bdreg:REGISTER:VEC:SINT8{BCAST,BLOCK} adreg:REGISTER:VEC:SINT8{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:16,bdreg_blocksize:16}
dup z1.q,z2.q[0]
### op move [] bdreg:REGISTER:VEC:SINT8{BCAST,BLOCK} adreg:REGISTER:VEC:SINT8{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:16,bdreg_blocksize:16} @far
dup z1.q,z2.q[3]
### op move [] bdreg:REGISTER:VEC:SINT8{BCAST} adreg:REGISTER:GP:SINT8
mov z1.b,w10
### op move [] bdreg:REGISTER:VEC:SINT8{BCAST} adreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.b,z2.b[0]
### op move [] bdreg:REGISTER:VEC:SINT8{BCAST} adreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.b,z2.b[63]
### op move [] bdreg:REGISTER:VEC:UINT16 adreg:REGISTER:VEC:UINT16
mov z1.d,z2.d
### op move [] bdreg:REGISTER:VEC:UINT16{BCAST,BLOCK} adreg:REGISTER:VEC:UINT16{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:8,bdreg_blocksize:8}
dup z1.q,z2.q[0]
### op move [] bdreg:REGISTER:VEC:UINT16{BCAST,BLOCK} adreg:REGISTER:VEC:UINT16{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:8,bdreg_blocksize:8} @far
dup z1.q,z2.q[3]
### op move [] bdreg:REGISTER:VEC:UINT16{BCAST} adreg:REGISTER:GP:UINT16
mov z1.h,w10
### op move [] bdreg:REGISTER:VEC:UINT16{BCAST} adreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.h,z2.h[0]
### op move [] bdreg:REGISTER:VEC:UINT16{BCAST} adreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.h,z2.h[31]
### op move [] bdreg:REGISTER:VEC:UINT32 adreg:REGISTER:VEC:UINT32
mov z1.d,z2.d
### op move [] bdreg:REGISTER:VEC:UINT32{BCAST,BLOCK} adreg:REGISTER:VEC:UINT32{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:4,bdreg_blocksize:4}
dup z1.q,z2.q[0]
### op move [] bdreg:REGISTER:VEC:UINT32{BCAST,BLOCK} adreg:REGISTER:VEC:UINT32{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:4,bdreg_blocksize:4} @far
dup z1.q,z2.q[3]
### op move [] bdreg:REGISTER:VEC:UINT32{BCAST} adreg:REGISTER:GP:UINT32
mov z1.s,w10
### op move [] bdreg:REGISTER:VEC:UINT32{BCAST} adreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.s,z2.s[0]
### op move [] bdreg:REGISTER:VEC:UINT32{BCAST} adreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.s,z2.s[15]
### op move [] bdreg:REGISTER:VEC:UINT64 adreg:REGISTER:VEC:UINT64
mov z1.d,z2.d
### op move [] bdreg:REGISTER:VEC:UINT64{BCAST,BLOCK} adreg:REGISTER:VEC:UINT64{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:2,bdreg_blocksize:2}
dup z1.q,z2.q[0]
### op move [] bdreg:REGISTER:VEC:UINT64{BCAST,BLOCK} adreg:REGISTER:VEC:UINT64{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:2,bdreg_blocksize:2} @far
dup z1.q,z2.q[3]
### op move [] bdreg:REGISTER:VEC:UINT64{BCAST} adreg:REGISTER:GP:UINT64
mov z1.d,x10
### op move [] bdreg:REGISTER:VEC:UINT64{BCAST} adreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.d,z2.d[0]
### op move [] bdreg:REGISTER:VEC:UINT64{BCAST} adreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.d,z2.d[7]
### op move [] bdreg:REGISTER:VEC:UINT8 adreg:REGISTER:VEC:UINT8
mov z1.d,z2.d
### op move [] bdreg:REGISTER:VEC:UINT8{BCAST,BLOCK} adreg:REGISTER:VEC:UINT8{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:16,bdreg_blocksize:16}
dup z1.q,z2.q[0]
### op move [] bdreg:REGISTER:VEC:UINT8{BCAST,BLOCK} adreg:REGISTER:VEC:UINT8{IBLOCK} adreg_block:IMMEDIATE:-:- {adreg_blocksize:16,bdreg_blocksize:16} @far
dup z1.q,z2.q[3]
### op move [] bdreg:REGISTER:VEC:UINT8{BCAST} adreg:REGISTER:GP:UINT8
mov z1.b,w10
### op move [] bdreg:REGISTER:VEC:UINT8{BCAST} adreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:-
dup z1.b,z2.b[0]
### op move [] bdreg:REGISTER:VEC:UINT8{BCAST} adreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- @far
dup z1.b,z2.b[63]
### op mul [MASK] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 amreg:REGISTER:MASK:BF16
!KeyError: <asm_data_type.BF16: 5>
### op mul [MASK] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE amreg:REGISTER:MASK:DOUBLE
fmul z1.d,p1/m,z1.d,z2.d
### op mul [MASK] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF amreg:REGISTER:MASK:HALF
fmul z1.h,p1/m,z1.h,z2.h
### op mul [MASK] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE amreg:REGISTER:MASK:SINGLE
fmul z1.s,p1/m,z1.s,z2.s
### op mul [MASK] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 amreg:REGISTER:MASK:SINT16
mul z1.h,p1/m,z1.h,z2.h
### op mul [MASK] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 amreg:REGISTER:MASK:SINT32
mul z1.s,p1/m,z1.s,z2.s
### op mul [MASK] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 amreg:REGISTER:MASK:SINT64
mul z1.d,p1/m,z1.d,z2.d
### op mul [MASK] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 amreg:REGISTER:MASK:SINT8
mul z1.b,p1/m,z1.b,z2.b
### op mul [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64
mul x12,x10,x11
### op mul [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64
mul x12,x10,x11
### op mul [] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16
!KeyError: <asm_data_type.BF16: 5>
### op mul [] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16{BLOCKLANE} cdreg:REGISTER:VEC:BF16 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8}
!KeyError: <asm_data_type.BF16: 5>
### op mul [] adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16{BLOCKLANE} cdreg:REGISTER:VEC:BF16 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8} @far
!KeyError: <asm_data_type.BF16: 5>
### op mul [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE
fmul z3.d,z1.d,z2.d
### op mul [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE{BLOCKLANE} cdreg:REGISTER:VEC:DOUBLE bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:2}
fmul z3.d,z1.d,z2.d[0]
### op mul [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE{BLOCKLANE} cdreg:REGISTER:VEC:DOUBLE bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:2} @far
fmul z3.d,z1.d,z2.d[1]
### op mul [] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF
fmul z3.h,z1.h,z2.h
### op mul [] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8}
fmul z3.h,z1.h,z2.h[0]
### op mul [] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8} @far
fmul z3.h,z1.h,z2.h[7]
### op mul [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE
fmul z3.s,z1.s,z2.s
### op mul [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:4}
fmul z3.s,z1.s,z2.s[0]
### op mul [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:4} @far
fmul z3.s,z1.s,z2.s[3]
### op mul [] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{BLOCKLANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8}
mul z3.h,z1.h,z2.h[0]
### op mul [] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{BLOCKLANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8} @far
mul z3.h,z1.h,z2.h[7]
### op mul [] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32{BLOCKLANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:4}
mul z3.s,z1.s,z2.s[0]
### op mul [] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32{BLOCKLANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:4} @far
mul z3.s,z1.s,z2.s[3]
### op mul [] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64{BLOCKLANE} cdreg:REGISTER:VEC:SINT64 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:2}
mul z3.d,z1.d,z2.d[0]
### op mul [] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64{BLOCKLANE} cdreg:REGISTER:VEC:SINT64 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:2} @far
mul z3.d,z1.d,z2.d[1]
### op mul [] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:16}
mul z3.b,z1.b,z2.b[0]
### op mul [] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:16} @far
mul z3.b,z1.b,z2.b[15]
### op prefetch [GOFFSET] agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
prfm PLDL1KEEP, [x10, x11]
### op prefetch [IOFFSET] agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
prfm PLDL1KEEP, [x10]
### op prefetch [] agreg:REGISTER:GP:UINT64
prfm PLDL1KEEP, [x10]
### op set [CONSTMASK] dreg:REGISTER:MASK:DOUBLE count:IMMEDIATE:-:- {mask:first}
ptrue p1.d, vl1
### op set [CONSTMASK] dreg:REGISTER:MASK:DOUBLE {mask:allfalse}
pfalse p1.b
### op set [CONSTMASK] dreg:REGISTER:MASK:DOUBLE {mask:alltrue}
ptrue p1.d
### op set [CONSTMASK] dreg:REGISTER:MASK:FP8E4M3 count:IMMEDIATE:-:- {mask:first}
ptrue p1.b, vl1
### op set [CONSTMASK] dreg:REGISTER:MASK:FP8E4M3 {mask:allfalse}
pfalse p1.b
### op set [CONSTMASK] dreg:REGISTER:MASK:FP8E4M3 {mask:alltrue}
ptrue p1.b
### op set [CONSTMASK] dreg:REGISTER:MASK:FP8E5M2 count:IMMEDIATE:-:- {mask:first}
ptrue p1.b, vl1
### op set [CONSTMASK] dreg:REGISTER:MASK:FP8E5M2 {mask:allfalse}
pfalse p1.b
### op set [CONSTMASK] dreg:REGISTER:MASK:FP8E5M2 {mask:alltrue}
ptrue p1.b
### op set [CONSTMASK] dreg:REGISTER:MASK:HALF count:IMMEDIATE:-:- {mask:first}
ptrue p1.h, vl1
### op set [CONSTMASK] dreg:REGISTER:MASK:HALF {mask:allfalse}
pfalse p1.b
### op set [CONSTMASK] dreg:REGISTER:MASK:HALF {mask:alltrue}
ptrue p1.h
### op set [CONSTMASK] dreg:REGISTER:MASK:SINGLE count:IMMEDIATE:-:- {mask:first}
ptrue p1.s, vl1
### op set [CONSTMASK] dreg:REGISTER:MASK:SINGLE {mask:allfalse}
pfalse p1.b
### op set [CONSTMASK] dreg:REGISTER:MASK:SINGLE {mask:alltrue}
ptrue p1.s
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT16 count:IMMEDIATE:-:- {mask:first}
ptrue p1.h, vl1
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT16 {mask:allfalse}
pfalse p1.b
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT16 {mask:alltrue}
ptrue p1.h
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT32 count:IMMEDIATE:-:- {mask:first}
ptrue p1.s, vl1
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT32 {mask:allfalse}
pfalse p1.b
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT32 {mask:alltrue}
ptrue p1.s
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT64 count:IMMEDIATE:-:- {mask:first}
ptrue p1.d, vl1
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT64 {mask:allfalse}
pfalse p1.b
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT64 {mask:alltrue}
ptrue p1.d
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT8 count:IMMEDIATE:-:- {mask:first}
ptrue p1.b, vl1
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT8 {mask:allfalse}
pfalse p1.b
### op set [CONSTMASK] dreg:REGISTER:MASK:SINT8 {mask:alltrue}
ptrue p1.b
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT16 count:IMMEDIATE:-:- {mask:first}
ptrue p1.h, vl1
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT16 {mask:allfalse}
pfalse p1.b
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT16 {mask:alltrue}
ptrue p1.h
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT32 count:IMMEDIATE:-:- {mask:first}
ptrue p1.s, vl1
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT32 {mask:allfalse}
pfalse p1.b
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT32 {mask:alltrue}
ptrue p1.s
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT64 count:IMMEDIATE:-:- {mask:first}
ptrue p1.d, vl1
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT64 {mask:allfalse}
pfalse p1.b
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT64 {mask:alltrue}
ptrue p1.d
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT8 count:IMMEDIATE:-:- {mask:first}
ptrue p1.b, vl1
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT8 {mask:allfalse}
pfalse p1.b
### op set [CONSTMASK] dreg:REGISTER:MASK:UINT8 {mask:alltrue}
ptrue p1.b
### op set [CONST] dreg:REGISTER:FP:DOUBLE {constant:one}
fmov d1,#1.0
### op set [CONST] dreg:REGISTER:FP:DOUBLE {constant:zero}
fmov d1,xzr
### op set [CONST] dreg:REGISTER:FP:HALF {constant:one}
fmov h1,#1.0
### op set [CONST] dreg:REGISTER:FP:HALF {constant:zero}
fmov h1,wzr
### op set [CONST] dreg:REGISTER:FP:SINGLE {constant:one}
fmov s1,#1.0
### op set [CONST] dreg:REGISTER:FP:SINGLE {constant:zero}
fmov s1,wzr
### op set [CONST] dreg:REGISTER:GP:SINT64 value:IMMEDIATE:-:-
mov x10,#-9223372036854775808
### op set [CONST] dreg:REGISTER:GP:SINT64 value:IMMEDIATE:-:- @far
mov x10,#18446744073709551615
### op set [CONST] dreg:REGISTER:GP:SINT64 {constant:one}
mov x10,#1
### op set [CONST] dreg:REGISTER:GP:SINT64 {constant:zero}
mov x10,#0
### op set [CONST] dreg:REGISTER:GP:UINT64 value:IMMEDIATE:-:-
mov x10,#-9223372036854775808
### op set [CONST] dreg:REGISTER:GP:UINT64 value:IMMEDIATE:-:- @far
mov x10,#18446744073709551615
### op set [CONST] dreg:REGISTER:GP:UINT64 {constant:one}
mov x10,#1
### op set [CONST] dreg:REGISTER:GP:UINT64 {constant:zero}
mov x10,#0
### op set [CONST] dreg:REGISTER:TILE:DOUBLE {constant:zero}
zero {za0.d}
### op set [CONST] dreg:REGISTER:TILE:FP8E4M3 {constant:zero}
zero {za0.b}
### op set [CONST] dreg:REGISTER:TILE:FP8E5M2 {constant:zero}
zero {za0.b}
### op set [CONST] dreg:REGISTER:TILE:HALF {constant:zero}
zero {za0.h}
### op set [CONST] dreg:REGISTER:TILE:SINGLE {constant:zero}
zero {za0.s}
### op set [CONST] dreg:REGISTER:TILE:SINT16 {constant:zero}
zero {za0.h}
### op set [CONST] dreg:REGISTER:TILE:SINT32 {constant:zero}
zero {za0.s}
### op set [CONST] dreg:REGISTER:TILE:SINT64 {constant:zero}
zero {za0.d}
### op set [CONST] dreg:REGISTER:TILE:SINT8 {constant:zero}
zero {za0.b}
### op set [CONST] dreg:REGISTER:TILE:UINT16 {constant:zero}
zero {za0.h}
### op set [CONST] dreg:REGISTER:TILE:UINT32 {constant:zero}
zero {za0.s}
### op set [CONST] dreg:REGISTER:TILE:UINT64 {constant:zero}
zero {za0.d}
### op set [CONST] dreg:REGISTER:TILE:UINT8 {constant:zero}
zero {za0.b}
### op set [CONST] dreg:REGISTER:VEC:DOUBLE {constant:one}
fdup z1.d,#1.0
### op set [CONST] dreg:REGISTER:VEC:DOUBLE {constant:zero}
dup z1.d,#0
### op set [CONST] dreg:REGISTER:VEC:FP8E4M3 {constant:zero}
dup z1.b,#0
### op set [CONST] dreg:REGISTER:VEC:FP8E5M2 {constant:zero}
dup z1.b,#0
### op set [CONST] dreg:REGISTER:VEC:HALF {constant:one}
fdup z1.h,#1.0
### op set [CONST] dreg:REGISTER:VEC:HALF {constant:zero}
dup z1.h,#0
### op set [CONST] dreg:REGISTER:VEC:SINGLE {constant:one}
fdup z1.s,#1.0
### op set [CONST] dreg:REGISTER:VEC:SINGLE {constant:zero}
dup z1.s,#0
### op set [CONST] dreg:REGISTER:VEC:SINT16 {constant:one}
dup z1.h,#1
### op set [CONST] dreg:REGISTER:VEC:SINT16 {constant:zero}
dup z1.h,#0
### op set [CONST] dreg:REGISTER:VEC:SINT32 {constant:one}
dup z1.s,#1
### op set [CONST] dreg:REGISTER:VEC:SINT32 {constant:zero}
dup z1.s,#0
### op set [CONST] dreg:REGISTER:VEC:SINT64 {constant:one}
dup z1.d,#1
### op set [CONST] dreg:REGISTER:VEC:SINT64 {constant:zero}
dup z1.d,#0
### op set [CONST] dreg:REGISTER:VEC:SINT8 {constant:one}
dup z1.b,#1
### op set [CONST] dreg:REGISTER:VEC:SINT8 {constant:zero}
dup z1.b,#0
### op set [CONST] dreg:REGISTER:VEC:UINT16 {constant:one}
dup z1.h,#1
### op set [CONST] dreg:REGISTER:VEC:UINT16 {constant:zero}
dup z1.h,#0
### op set [CONST] dreg:REGISTER:VEC:UINT32 {constant:one}
dup z1.s,#1
### op set [CONST] dreg:REGISTER:VEC:UINT32 {constant:zero}
dup z1.s,#0
### op set [CONST] dreg:REGISTER:VEC:UINT64 {constant:one}
dup z1.d,#1
### op set [CONST] dreg:REGISTER:VEC:UINT64 {constant:zero}
dup z1.d,#0
### op set [CONST] dreg:REGISTER:VEC:UINT8 {constant:one}
dup z1.b,#1
### op set [CONST] dreg:REGISTER:VEC:UINT8 {constant:zero}
dup z1.b,#0
### op set [ENGINE]  {engine:off}
smstop
### op set [ENGINE]  {engine:on}
smstart
### op set [MASKAVL] dreg:REGISTER:MASK:DOUBLE avlreg:REGISTER:GP:UINT64
whilelo p1.d, xzr, x10
### op set [MASKAVL] dreg:REGISTER:MASK:FP8E4M3 avlreg:REGISTER:GP:UINT64
whilelo p1.b, xzr, x10
### op set [MASKAVL] dreg:REGISTER:MASK:FP8E5M2 avlreg:REGISTER:GP:UINT64
whilelo p1.b, xzr, x10
### op set [MASKAVL] dreg:REGISTER:MASK:HALF avlreg:REGISTER:GP:UINT64
whilelo p1.h, xzr, x10
### op set [MASKAVL] dreg:REGISTER:MASK:SINGLE avlreg:REGISTER:GP:UINT64
whilelo p1.s, xzr, x10
### op set [MASKAVL] dreg:REGISTER:MASK:SINT16 avlreg:REGISTER:GP:UINT64
whilelo p1.h, xzr, x10
### op set [MASKAVL] dreg:REGISTER:MASK:SINT32 avlreg:REGISTER:GP:UINT64
whilelo p1.s, xzr, x10
### op set [MASKAVL] dreg:REGISTER:MASK:SINT64 avlreg:REGISTER:GP:UINT64
whilelo p1.d, xzr, x10
### op set [MASKAVL] dreg:REGISTER:MASK:SINT8 avlreg:REGISTER:GP:UINT64
whilelo p1.b, xzr, x10
### op set [MASKAVL] dreg:REGISTER:MASK:UINT16 avlreg:REGISTER:GP:UINT64
whilelo p1.h, xzr, x10
### op set [MASKAVL] dreg:REGISTER:MASK:UINT32 avlreg:REGISTER:GP:UINT64
whilelo p1.s, xzr, x10
### op set [MASKAVL] dreg:REGISTER:MASK:UINT64 avlreg:REGISTER:GP:UINT64
whilelo p1.d, xzr, x10
### op set [MASKAVL] dreg:REGISTER:MASK:UINT8 avlreg:REGISTER:GP:UINT64
whilelo p1.b, xzr, x10
### op set [PARAM,VLEN] param:NAME:-:-
cntb %[p]
### op set [STINDEX] dreg:REGISTER:VEC:DOUBLE streg:REGISTER:GP:UINT64
index z1.d,#0,x10
### op set [STINDEX] dreg:REGISTER:VEC:FP8E4M3 streg:REGISTER:GP:UINT64
index z1.b,#0,w10
### op set [STINDEX] dreg:REGISTER:VEC:FP8E5M2 streg:REGISTER:GP:UINT64
index z1.b,#0,w10
### op set [STINDEX] dreg:REGISTER:VEC:HALF streg:REGISTER:GP:UINT64
index z1.h,#0,w10
### op set [STINDEX] dreg:REGISTER:VEC:SINGLE streg:REGISTER:GP:UINT64
index z1.s,#0,w10
### op set [STINDEX] dreg:REGISTER:VEC:SINT16 streg:REGISTER:GP:UINT64
index z1.h,#0,w10
### op set [STINDEX] dreg:REGISTER:VEC:SINT32 streg:REGISTER:GP:UINT64
index z1.s,#0,w10
### op set [STINDEX] dreg:REGISTER:VEC:SINT64 streg:REGISTER:GP:UINT64
index z1.d,#0,x10
### op set [STINDEX] dreg:REGISTER:VEC:SINT8 streg:REGISTER:GP:UINT64
index z1.b,#0,w10
### op set [STINDEX] dreg:REGISTER:VEC:UINT16 streg:REGISTER:GP:UINT64
index z1.h,#0,w10
### op set [STINDEX] dreg:REGISTER:VEC:UINT32 streg:REGISTER:GP:UINT64
index z1.s,#0,w10
### op set [STINDEX] dreg:REGISTER:VEC:UINT64 streg:REGISTER:GP:UINT64
index z1.d,#0,x10
### op set [STINDEX] dreg:REGISTER:VEC:UINT8 streg:REGISTER:GP:UINT64
index z1.b,#0,w10
### op set [VLEN] dreg:REGISTER:GP:UINT64
cntd x10
### op shift [SHL] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64
lsl x12,x10,x11
### op shift [SHL] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:-
lsl x11,x10,#0
### op shift [SHL] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:- @far
lsl x11,x10,#63
### op shift [SHL] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64
lsl x12,x10,x11
### op shift [SHL] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:-
lsl x11,x10,#0
### op shift [SHL] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:- @far
lsl x11,x10,#63
### op shift [SHR] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64
lsr x12,x10,x11
### op shift [SHR] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:-
lsr x11,x10,#0
### op shift [SHR] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:- @far
lsr x11,x10,#63
### op shift [SHR] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64
lsr x12,x10,x11
### op shift [SHR] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:-
lsr x11,x10,#0
### op shift [SHR] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:- @far
lsr x11,x10,#63
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 ddreg:REGISTER:VEC:BF16 offreg:REGISTER:GP:SINT64 {nvectors:4}
stnt1h {z1.h, z5.h, z9.h, z13.h}, p8, [x10, x11, lsl #1]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 offreg:REGISTER:GP:SINT64 {nvectors:2}
stnt1h {z1.h, z9.h}, p8, [x10, x11, lsl #1]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE offreg:REGISTER:GP:SINT64 {nvectors:4}
stnt1d {z1.d, z5.d, z9.d, z13.d}, p8, [x10, x11, lsl #3]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE offreg:REGISTER:GP:SINT64 {nvectors:2}
stnt1d {z1.d, z9.d}, p8, [x10, x11, lsl #3]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 offreg:REGISTER:GP:SINT64 {nvectors:4}
stnt1b {z1.b, z5.b, z9.b, z13.b}, p8, [x10, x11]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 offreg:REGISTER:GP:SINT64 {nvectors:2}
stnt1b {z1.b, z9.b}, p8, [x10, x11]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 offreg:REGISTER:GP:SINT64 {nvectors:4}
stnt1b {z1.b, z5.b, z9.b, z13.b}, p8, [x10, x11]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 offreg:REGISTER:GP:SINT64 {nvectors:2}
stnt1b {z1.b, z9.b}, p8, [x10, x11]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF offreg:REGISTER:GP:SINT64 {nvectors:4}
stnt1h {z1.h, z5.h, z9.h, z13.h}, p8, [x10, x11, lsl #1]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF offreg:REGISTER:GP:SINT64 {nvectors:2}
stnt1h {z1.h, z9.h}, p8, [x10, x11, lsl #1]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE offreg:REGISTER:GP:SINT64 {nvectors:4}
stnt1w {z1.s, z5.s, z9.s, z13.s}, p8, [x10, x11, lsl #2]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE offreg:REGISTER:GP:SINT64 {nvectors:2}
stnt1w {z1.s, z9.s}, p8, [x10, x11, lsl #2]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 offreg:REGISTER:GP:SINT64 {nvectors:4}
stnt1h {z1.h, z5.h, z9.h, z13.h}, p8, [x10, x11, lsl #1]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 offreg:REGISTER:GP:SINT64 {nvectors:2}
stnt1h {z1.h, z9.h}, p8, [x10, x11, lsl #1]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 offreg:REGISTER:GP:SINT64 {nvectors:4}
stnt1w {z1.s, z5.s, z9.s, z13.s}, p8, [x10, x11, lsl #2]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 offreg:REGISTER:GP:SINT64 {nvectors:2}
stnt1w {z1.s, z9.s}, p8, [x10, x11, lsl #2]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 offreg:REGISTER:GP:SINT64 {nvectors:4}
stnt1d {z1.d, z5.d, z9.d, z13.d}, p8, [x10, x11, lsl #3]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 offreg:REGISTER:GP:SINT64 {nvectors:2}
stnt1d {z1.d, z9.d}, p8, [x10, x11, lsl #3]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 offreg:REGISTER:GP:SINT64 {nvectors:4}
stnt1b {z1.b, z5.b, z9.b, z13.b}, p8, [x10, x11]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 offreg:REGISTER:GP:SINT64 {nvectors:2}
stnt1b {z1.b, z9.b}, p8, [x10, x11]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 offreg:REGISTER:GP:SINT64 {nvectors:4}
stnt1h {z1.h, z5.h, z9.h, z13.h}, p8, [x10, x11, lsl #1]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 offreg:REGISTER:GP:SINT64 {nvectors:2}
stnt1h {z1.h, z9.h}, p8, [x10, x11, lsl #1]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 offreg:REGISTER:GP:SINT64 {nvectors:4}
stnt1w {z1.s, z5.s, z9.s, z13.s}, p8, [x10, x11, lsl #2]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 offreg:REGISTER:GP:SINT64 {nvectors:2}
stnt1w {z1.s, z9.s}, p8, [x10, x11, lsl #2]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 offreg:REGISTER:GP:SINT64 {nvectors:4}
stnt1d {z1.d, z5.d, z9.d, z13.d}, p8, [x10, x11, lsl #3]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 offreg:REGISTER:GP:SINT64 {nvectors:2}
stnt1d {z1.d, z9.d}, p8, [x10, x11, lsl #3]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 offreg:REGISTER:GP:SINT64 {nvectors:4}
stnt1b {z1.b, z5.b, z9.b, z13.b}, p8, [x10, x11]
### op store [GOFFSET,MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 offreg:REGISTER:GP:SINT64 {nvectors:2}
stnt1b {z1.b, z9.b}, p8, [x10, x11]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 ddreg:REGISTER:VEC:BF16 offreg:REGISTER:GP:SINT64 {nstructs:4}
st4h {z1.h, z2.h, z3.h, z4.h}, p1, [x10, x11, lsl #1]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 offreg:REGISTER:GP:SINT64 {nstructs:3}
st3h {z1.h, z2.h, z3.h}, p1, [x10, x11, lsl #1]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 offreg:REGISTER:GP:SINT64 {nstructs:2}
st2h {z1.h, z2.h}, p1, [x10, x11, lsl #1]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE offreg:REGISTER:GP:SINT64 {nstructs:4}
st4d {z1.d, z2.d, z3.d, z4.d}, p1, [x10, x11, lsl #3]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE offreg:REGISTER:GP:SINT64 {nstructs:3}
st3d {z1.d, z2.d, z3.d}, p1, [x10, x11, lsl #3]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE offreg:REGISTER:GP:SINT64 {nstructs:2}
st2d {z1.d, z2.d}, p1, [x10, x11, lsl #3]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 offreg:REGISTER:GP:SINT64 {nstructs:4}
st4b {z1.b, z2.b, z3.b, z4.b}, p1, [x10, x11]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 offreg:REGISTER:GP:SINT64 {nstructs:3}
st3b {z1.b, z2.b, z3.b}, p1, [x10, x11]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 offreg:REGISTER:GP:SINT64 {nstructs:2}
st2b {z1.b, z2.b}, p1, [x10, x11]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 offreg:REGISTER:GP:SINT64 {nstructs:4}
st4b {z1.b, z2.b, z3.b, z4.b}, p1, [x10, x11]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 offreg:REGISTER:GP:SINT64 {nstructs:3}
st3b {z1.b, z2.b, z3.b}, p1, [x10, x11]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 offreg:REGISTER:GP:SINT64 {nstructs:2}
st2b {z1.b, z2.b}, p1, [x10, x11]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF offreg:REGISTER:GP:SINT64 {nstructs:4}
st4h {z1.h, z2.h, z3.h, z4.h}, p1, [x10, x11, lsl #1]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF offreg:REGISTER:GP:SINT64 {nstructs:3}
st3h {z1.h, z2.h, z3.h}, p1, [x10, x11, lsl #1]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF offreg:REGISTER:GP:SINT64 {nstructs:2}
st2h {z1.h, z2.h}, p1, [x10, x11, lsl #1]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE offreg:REGISTER:GP:SINT64 {nstructs:4}
st4w {z1.s, z2.s, z3.s, z4.s}, p1, [x10, x11, lsl #2]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE offreg:REGISTER:GP:SINT64 {nstructs:3}
st3w {z1.s, z2.s, z3.s}, p1, [x10, x11, lsl #2]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE offreg:REGISTER:GP:SINT64 {nstructs:2}
st2w {z1.s, z2.s}, p1, [x10, x11, lsl #2]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 offreg:REGISTER:GP:SINT64 {nstructs:4}
st4h {z1.h, z2.h, z3.h, z4.h}, p1, [x10, x11, lsl #1]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 offreg:REGISTER:GP:SINT64 {nstructs:3}
st3h {z1.h, z2.h, z3.h}, p1, [x10, x11, lsl #1]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 offreg:REGISTER:GP:SINT64 {nstructs:2}
st2h {z1.h, z2.h}, p1, [x10, x11, lsl #1]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 offreg:REGISTER:GP:SINT64 {nstructs:4}
st4w {z1.s, z2.s, z3.s, z4.s}, p1, [x10, x11, lsl #2]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 offreg:REGISTER:GP:SINT64 {nstructs:3}
st3w {z1.s, z2.s, z3.s}, p1, [x10, x11, lsl #2]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 offreg:REGISTER:GP:SINT64 {nstructs:2}
st2w {z1.s, z2.s}, p1, [x10, x11, lsl #2]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 offreg:REGISTER:GP:SINT64 {nstructs:4}
st4d {z1.d, z2.d, z3.d, z4.d}, p1, [x10, x11, lsl #3]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 offreg:REGISTER:GP:SINT64 {nstructs:3}
st3d {z1.d, z2.d, z3.d}, p1, [x10, x11, lsl #3]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 offreg:REGISTER:GP:SINT64 {nstructs:2}
st2d {z1.d, z2.d}, p1, [x10, x11, lsl #3]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 offreg:REGISTER:GP:SINT64 {nstructs:4}
st4b {z1.b, z2.b, z3.b, z4.b}, p1, [x10, x11]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 offreg:REGISTER:GP:SINT64 {nstructs:3}
st3b {z1.b, z2.b, z3.b}, p1, [x10, x11]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 offreg:REGISTER:GP:SINT64 {nstructs:2}
st2b {z1.b, z2.b}, p1, [x10, x11]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 offreg:REGISTER:GP:SINT64 {nstructs:4}
st4h {z1.h, z2.h, z3.h, z4.h}, p1, [x10, x11, lsl #1]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 offreg:REGISTER:GP:SINT64 {nstructs:3}
st3h {z1.h, z2.h, z3.h}, p1, [x10, x11, lsl #1]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 offreg:REGISTER:GP:SINT64 {nstructs:2}
st2h {z1.h, z2.h}, p1, [x10, x11, lsl #1]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 offreg:REGISTER:GP:SINT64 {nstructs:4}
st4w {z1.s, z2.s, z3.s, z4.s}, p1, [x10, x11, lsl #2]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 offreg:REGISTER:GP:SINT64 {nstructs:3}
st3w {z1.s, z2.s, z3.s}, p1, [x10, x11, lsl #2]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 offreg:REGISTER:GP:SINT64 {nstructs:2}
st2w {z1.s, z2.s}, p1, [x10, x11, lsl #2]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 offreg:REGISTER:GP:SINT64 {nstructs:4}
st4d {z1.d, z2.d, z3.d, z4.d}, p1, [x10, x11, lsl #3]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 offreg:REGISTER:GP:SINT64 {nstructs:3}
st3d {z1.d, z2.d, z3.d}, p1, [x10, x11, lsl #3]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 offreg:REGISTER:GP:SINT64 {nstructs:2}
st2d {z1.d, z2.d}, p1, [x10, x11, lsl #3]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 offreg:REGISTER:GP:SINT64 {nstructs:4}
st4b {z1.b, z2.b, z3.b, z4.b}, p1, [x10, x11]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 offreg:REGISTER:GP:SINT64 {nstructs:3}
st3b {z1.b, z2.b, z3.b}, p1, [x10, x11]
### op store [GOFFSET,MASK,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 offreg:REGISTER:GP:SINT64 {nstructs:2}
st2b {z1.b, z2.b}, p1, [x10, x11]
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 offreg:REGISTER:GP:SINT64
st1h {z1.h}, p1, [x10, x11, lsl #1]
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE offreg:REGISTER:GP:SINT64
st1d {z1.d}, p1, [x10, x11, lsl #3]
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 offreg:REGISTER:GP:SINT64
st1b {z1.b}, p1, [x10, x11]
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 offreg:REGISTER:GP:SINT64
st1b {z1.b}, p1, [x10, x11]
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF offreg:REGISTER:GP:SINT64
st1h {z1.h}, p1, [x10, x11, lsl #1]
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE offreg:REGISTER:GP:SINT64
st1w {z1.s}, p1, [x10, x11, lsl #2]
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 offreg:REGISTER:GP:SINT64
st1h {z1.h}, p1, [x10, x11, lsl #1]
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 offreg:REGISTER:GP:SINT64
st1w {z1.s}, p1, [x10, x11, lsl #2]
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 offreg:REGISTER:GP:SINT64
st1d {z1.d}, p1, [x10, x11, lsl #3]
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 offreg:REGISTER:GP:SINT64
st1b {z1.b}, p1, [x10, x11]
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 offreg:REGISTER:GP:SINT64
st1h {z1.h}, p1, [x10, x11, lsl #1]
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 offreg:REGISTER:GP:SINT64
st1w {z1.s}, p1, [x10, x11, lsl #2]
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 offreg:REGISTER:GP:SINT64
st1d {z1.d}, p1, [x10, x11, lsl #3]
### op store [GOFFSET,MASK] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 offreg:REGISTER:GP:SINT64
st1b {z1.b}, p1, [x10, x11]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:TILE:BF16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1h {za0v.h[w12, 0]}, p1, [x10, x13, lsl #1]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:TILE:BF16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1h {za0v.h[w12, 7]}, p1, [x10, x13, lsl #1]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:TILE:BF16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1h {za0h.h[w12, 0]}, p1, [x10, x13, lsl #1]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:TILE:BF16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1h {za0h.h[w12, 7]}, p1, [x10, x13, lsl #1]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:TILE:DOUBLE{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1d {za0v.d[w12, 0]}, p1, [x10, x13, lsl #3]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:TILE:DOUBLE{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1d {za0v.d[w12, 1]}, p1, [x10, x13, lsl #3]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:TILE:DOUBLE{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1d {za0h.d[w12, 0]}, p1, [x10, x13, lsl #3]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:TILE:DOUBLE{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1d {za0h.d[w12, 1]}, p1, [x10, x13, lsl #3]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:TILE:FP8E4M3{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1b {za0v.b[w12, 0]}, p1, [x10, x13]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:TILE:FP8E4M3{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1b {za0v.b[w12, 15]}, p1, [x10, x13]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:TILE:FP8E4M3{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1b {za0h.b[w12, 0]}, p1, [x10, x13]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:TILE:FP8E4M3{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1b {za0h.b[w12, 15]}, p1, [x10, x13]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:TILE:FP8E5M2{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1b {za0v.b[w12, 0]}, p1, [x10, x13]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:TILE:FP8E5M2{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1b {za0v.b[w12, 15]}, p1, [x10, x13]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:TILE:FP8E5M2{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1b {za0h.b[w12, 0]}, p1, [x10, x13]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:TILE:FP8E5M2{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1b {za0h.b[w12, 15]}, p1, [x10, x13]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:TILE:HALF{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1h {za0v.h[w12, 0]}, p1, [x10, x13, lsl #1]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:TILE:HALF{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1h {za0v.h[w12, 7]}, p1, [x10, x13, lsl #1]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:TILE:HALF{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1h {za0h.h[w12, 0]}, p1, [x10, x13, lsl #1]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:TILE:HALF{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1h {za0h.h[w12, 7]}, p1, [x10, x13, lsl #1]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:TILE:SINGLE{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1w {za0v.s[w12, 0]}, p1, [x10, x13, lsl #2]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:TILE:SINGLE{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1w {za0v.s[w12, 3]}, p1, [x10, x13, lsl #2]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:TILE:SINGLE{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1w {za0h.s[w12, 0]}, p1, [x10, x13, lsl #2]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:TILE:SINGLE{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1w {za0h.s[w12, 3]}, p1, [x10, x13, lsl #2]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:TILE:SINT16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1h {za0v.h[w12, 0]}, p1, [x10, x13, lsl #1]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:TILE:SINT16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1h {za0v.h[w12, 7]}, p1, [x10, x13, lsl #1]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:TILE:SINT16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1h {za0h.h[w12, 0]}, p1, [x10, x13, lsl #1]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:TILE:SINT16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1h {za0h.h[w12, 7]}, p1, [x10, x13, lsl #1]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:TILE:SINT32{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1w {za0v.s[w12, 0]}, p1, [x10, x13, lsl #2]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:TILE:SINT32{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1w {za0v.s[w12, 3]}, p1, [x10, x13, lsl #2]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:TILE:SINT32{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1w {za0h.s[w12, 0]}, p1, [x10, x13, lsl #2]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:TILE:SINT32{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1w {za0h.s[w12, 3]}, p1, [x10, x13, lsl #2]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:TILE:SINT64{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1d {za0v.d[w12, 0]}, p1, [x10, x13, lsl #3]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:TILE:SINT64{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1d {za0v.d[w12, 1]}, p1, [x10, x13, lsl #3]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:TILE:SINT64{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1d {za0h.d[w12, 0]}, p1, [x10, x13, lsl #3]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:TILE:SINT64{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1d {za0h.d[w12, 1]}, p1, [x10, x13, lsl #3]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:TILE:SINT8{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1b {za0v.b[w12, 0]}, p1, [x10, x13]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:TILE:SINT8{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1b {za0v.b[w12, 15]}, p1, [x10, x13]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:TILE:SINT8{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1b {za0h.b[w12, 0]}, p1, [x10, x13]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:TILE:SINT8{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1b {za0h.b[w12, 15]}, p1, [x10, x13]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:TILE:UINT16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1h {za0v.h[w12, 0]}, p1, [x10, x13, lsl #1]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:TILE:UINT16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1h {za0v.h[w12, 7]}, p1, [x10, x13, lsl #1]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:TILE:UINT16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1h {za0h.h[w12, 0]}, p1, [x10, x13, lsl #1]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:TILE:UINT16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1h {za0h.h[w12, 7]}, p1, [x10, x13, lsl #1]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:TILE:UINT32{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1w {za0v.s[w12, 0]}, p1, [x10, x13, lsl #2]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:TILE:UINT32{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1w {za0v.s[w12, 3]}, p1, [x10, x13, lsl #2]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:TILE:UINT32{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1w {za0h.s[w12, 0]}, p1, [x10, x13, lsl #2]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:TILE:UINT32{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1w {za0h.s[w12, 3]}, p1, [x10, x13, lsl #2]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:TILE:UINT64{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1d {za0v.d[w12, 0]}, p1, [x10, x13, lsl #3]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:TILE:UINT64{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1d {za0v.d[w12, 1]}, p1, [x10, x13, lsl #3]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:TILE:UINT64{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1d {za0h.d[w12, 0]}, p1, [x10, x13, lsl #3]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:TILE:UINT64{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1d {za0h.d[w12, 1]}, p1, [x10, x13, lsl #3]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:TILE:UINT8{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1b {za0v.b[w12, 0]}, p1, [x10, x13]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:TILE:UINT8{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1b {za0v.b[w12, 15]}, p1, [x10, x13]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:TILE:UINT8{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64
st1b {za0h.b[w12, 0]}, p1, [x10, x13]
### op store [GOFFSET,MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:TILE:UINT8{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- offreg:REGISTER:GP:SINT64 @far
st1b {za0h.b[w12, 15]}, p1, [x10, x13]
### op store [GOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
str d1, [x10, x11]
### op store [GOFFSET] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
str b1, [x10, x11]
### op store [GOFFSET] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
str b1, [x10, x11]
### op store [GOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
str h1, [x10, x11]
### op store [GOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
str s1, [x10, x11]
### op store [GOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
strh w10, [x11, x12]
### op store [GOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
str w10, [x11, x12]
### op store [GOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
str x10, [x11, x12]
### op store [GOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
strb w10, [x11, x12]
### op store [GOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
strh w10, [x11, x12]
### op store [GOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
str w10, [x11, x12]
### op store [GOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
str x10, [x11, x12]
### op store [GOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 offreg:REGISTER:GP:UINT64
strb w10, [x11, x12]
### op store [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE vidxreg:REGISTER:VEC:SINT64 ioffset:IMMEDIATE:-:- {it:INT64}
st1d {z1.d}, p1, [z2.d, #0]
### op store [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE vidxreg:REGISTER:VEC:SINT64 ioffset:IMMEDIATE:-:- {it:INT64} @far
st1d {z1.d}, p1, [z2.d, #248]
### op store [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE vidxreg:REGISTER:VEC:SINT32 ioffset:IMMEDIATE:-:- {it:INT32}
st1w {z1.s}, p1, [z2.s, #0]
### op store [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE vidxreg:REGISTER:VEC:SINT32 ioffset:IMMEDIATE:-:- {it:INT32} @far
st1w {z1.s}, p1, [z2.s, #124]
### op store [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 vidxreg:REGISTER:VEC:SINT32 ioffset:IMMEDIATE:-:- {it:INT32}
st1w {z1.s}, p1, [z2.s, #0]
### op store [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 vidxreg:REGISTER:VEC:SINT32 ioffset:IMMEDIATE:-:- {it:INT32} @far
st1w {z1.s}, p1, [z2.s, #124]
### op store [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 vidxreg:REGISTER:VEC:SINT64 ioffset:IMMEDIATE:-:- {it:INT64}
st1d {z1.d}, p1, [z2.d, #0]
### op store [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 vidxreg:REGISTER:VEC:SINT64 ioffset:IMMEDIATE:-:- {it:INT64} @far
st1d {z1.d}, p1, [z2.d, #248]
### op store [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 vidxreg:REGISTER:VEC:SINT32 ioffset:IMMEDIATE:-:- {it:INT32}
st1w {z1.s}, p1, [z2.s, #0]
### op store [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 vidxreg:REGISTER:VEC:SINT32 ioffset:IMMEDIATE:-:- {it:INT32} @far
st1w {z1.s}, p1, [z2.s, #124]
### op store [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 vidxreg:REGISTER:VEC:SINT64 ioffset:IMMEDIATE:-:- {it:INT64}
st1d {z1.d}, p1, [z2.d, #0]
### op store [IOFFSET,MASK,VINDEX] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 vidxreg:REGISTER:VEC:SINT64 ioffset:IMMEDIATE:-:- {it:INT64} @far
st1d {z1.d}, p1, [z2.d, #248]
### op store [IOFFSET] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
str d1, [x10]
### op store [IOFFSET] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
str b1, [x10]
### op store [IOFFSET] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
str b1, [x10]
### op store [IOFFSET] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
str h1, [x10]
### op store [IOFFSET] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
str s1, [x10]
### op store [IOFFSET] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
strh w10, [x11]
### op store [IOFFSET] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
str w10, [x11]
### op store [IOFFSET] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
str x10, [x11]
### op store [IOFFSET] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
strb w10, [x11]
### op store [IOFFSET] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
strh w10, [x11]
### op store [IOFFSET] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
str w10, [x11]
### op store [IOFFSET] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
str x10, [x11]
### op store [IOFFSET] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 ioffset:IMMEDIATE:-:SINT64
strb w10, [x11]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 ddreg:REGISTER:VEC:BF16 voffset:IMMEDIATE:-:- {nvectors:4}
stnt1h {z1.h, z5.h, z9.h, z13.h}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 ddreg:REGISTER:VEC:BF16 voffset:IMMEDIATE:-:- {nvectors:4} @far
stnt1h {z1.h, z5.h, z9.h, z13.h}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 voffset:IMMEDIATE:-:- {nvectors:2}
stnt1h {z1.h, z9.h}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 voffset:IMMEDIATE:-:- {nvectors:2} @far
stnt1h {z1.h, z9.h}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE voffset:IMMEDIATE:-:- {nvectors:4}
stnt1d {z1.d, z5.d, z9.d, z13.d}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE voffset:IMMEDIATE:-:- {nvectors:4} @far
stnt1d {z1.d, z5.d, z9.d, z13.d}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE voffset:IMMEDIATE:-:- {nvectors:2}
stnt1d {z1.d, z9.d}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE voffset:IMMEDIATE:-:- {nvectors:2} @far
stnt1d {z1.d, z9.d}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 voffset:IMMEDIATE:-:- {nvectors:4}
stnt1b {z1.b, z5.b, z9.b, z13.b}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 voffset:IMMEDIATE:-:- {nvectors:4} @far
stnt1b {z1.b, z5.b, z9.b, z13.b}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 voffset:IMMEDIATE:-:- {nvectors:2}
stnt1b {z1.b, z9.b}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 voffset:IMMEDIATE:-:- {nvectors:2} @far
stnt1b {z1.b, z9.b}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 voffset:IMMEDIATE:-:- {nvectors:4}
stnt1b {z1.b, z5.b, z9.b, z13.b}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 voffset:IMMEDIATE:-:- {nvectors:4} @far
stnt1b {z1.b, z5.b, z9.b, z13.b}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 voffset:IMMEDIATE:-:- {nvectors:2}
stnt1b {z1.b, z9.b}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 voffset:IMMEDIATE:-:- {nvectors:2} @far
stnt1b {z1.b, z9.b}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF voffset:IMMEDIATE:-:- {nvectors:4}
stnt1h {z1.h, z5.h, z9.h, z13.h}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF voffset:IMMEDIATE:-:- {nvectors:4} @far
stnt1h {z1.h, z5.h, z9.h, z13.h}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF voffset:IMMEDIATE:-:- {nvectors:2}
stnt1h {z1.h, z9.h}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF voffset:IMMEDIATE:-:- {nvectors:2} @far
stnt1h {z1.h, z9.h}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE voffset:IMMEDIATE:-:- {nvectors:4}
stnt1w {z1.s, z5.s, z9.s, z13.s}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE voffset:IMMEDIATE:-:- {nvectors:4} @far
stnt1w {z1.s, z5.s, z9.s, z13.s}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE voffset:IMMEDIATE:-:- {nvectors:2}
stnt1w {z1.s, z9.s}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE voffset:IMMEDIATE:-:- {nvectors:2} @far
stnt1w {z1.s, z9.s}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 voffset:IMMEDIATE:-:- {nvectors:4}
stnt1h {z1.h, z5.h, z9.h, z13.h}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 voffset:IMMEDIATE:-:- {nvectors:4} @far
stnt1h {z1.h, z5.h, z9.h, z13.h}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 voffset:IMMEDIATE:-:- {nvectors:2}
stnt1h {z1.h, z9.h}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 voffset:IMMEDIATE:-:- {nvectors:2} @far
stnt1h {z1.h, z9.h}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 voffset:IMMEDIATE:-:- {nvectors:4}
stnt1w {z1.s, z5.s, z9.s, z13.s}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 voffset:IMMEDIATE:-:- {nvectors:4} @far
stnt1w {z1.s, z5.s, z9.s, z13.s}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 voffset:IMMEDIATE:-:- {nvectors:2}
stnt1w {z1.s, z9.s}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 voffset:IMMEDIATE:-:- {nvectors:2} @far
stnt1w {z1.s, z9.s}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 voffset:IMMEDIATE:-:- {nvectors:4}
stnt1d {z1.d, z5.d, z9.d, z13.d}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 voffset:IMMEDIATE:-:- {nvectors:4} @far
stnt1d {z1.d, z5.d, z9.d, z13.d}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 voffset:IMMEDIATE:-:- {nvectors:2}
stnt1d {z1.d, z9.d}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 voffset:IMMEDIATE:-:- {nvectors:2} @far
stnt1d {z1.d, z9.d}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 voffset:IMMEDIATE:-:- {nvectors:4}
stnt1b {z1.b, z5.b, z9.b, z13.b}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 voffset:IMMEDIATE:-:- {nvectors:4} @far
stnt1b {z1.b, z5.b, z9.b, z13.b}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 voffset:IMMEDIATE:-:- {nvectors:2}
stnt1b {z1.b, z9.b}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 voffset:IMMEDIATE:-:- {nvectors:2} @far
stnt1b {z1.b, z9.b}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 voffset:IMMEDIATE:-:- {nvectors:4}
stnt1h {z1.h, z5.h, z9.h, z13.h}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 voffset:IMMEDIATE:-:- {nvectors:4} @far
stnt1h {z1.h, z5.h, z9.h, z13.h}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 voffset:IMMEDIATE:-:- {nvectors:2}
stnt1h {z1.h, z9.h}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 voffset:IMMEDIATE:-:- {nvectors:2} @far
stnt1h {z1.h, z9.h}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 voffset:IMMEDIATE:-:- {nvectors:4}
stnt1w {z1.s, z5.s, z9.s, z13.s}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 voffset:IMMEDIATE:-:- {nvectors:4} @far
stnt1w {z1.s, z5.s, z9.s, z13.s}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 voffset:IMMEDIATE:-:- {nvectors:2}
stnt1w {z1.s, z9.s}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 voffset:IMMEDIATE:-:- {nvectors:2} @far
stnt1w {z1.s, z9.s}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 voffset:IMMEDIATE:-:- {nvectors:4}
stnt1d {z1.d, z5.d, z9.d, z13.d}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 voffset:IMMEDIATE:-:- {nvectors:4} @far
stnt1d {z1.d, z5.d, z9.d, z13.d}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 voffset:IMMEDIATE:-:- {nvectors:2}
stnt1d {z1.d, z9.d}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 voffset:IMMEDIATE:-:- {nvectors:2} @far
stnt1d {z1.d, z9.d}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 voffset:IMMEDIATE:-:- {nvectors:4}
stnt1b {z1.b, z5.b, z9.b, z13.b}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 voffset:IMMEDIATE:-:- {nvectors:4} @far
stnt1b {z1.b, z5.b, z9.b, z13.b}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 voffset:IMMEDIATE:-:- {nvectors:2}
stnt1b {z1.b, z9.b}, p8, [x10, #-8, MUL VL]
### op store [MASK,MULTIVEC,NT,VOFFSET] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 voffset:IMMEDIATE:-:- {nvectors:2} @far
stnt1b {z1.b, z9.b}, p8, [x10, #7, MUL VL]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 ddreg:REGISTER:VEC:BF16 {nvectors:4}
stnt1h {z1.h, z5.h, z9.h, z13.h}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:VEC:BF16 bdreg:REGISTER:VEC:BF16 {nvectors:2}
stnt1h {z1.h, z9.h}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE {nvectors:4}
stnt1d {z1.d, z5.d, z9.d, z13.d}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE {nvectors:2}
stnt1d {z1.d, z9.d}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 {nvectors:4}
stnt1b {z1.b, z5.b, z9.b, z13.b}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 {nvectors:2}
stnt1b {z1.b, z9.b}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 {nvectors:4}
stnt1b {z1.b, z5.b, z9.b, z13.b}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 {nvectors:2}
stnt1b {z1.b, z9.b}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF {nvectors:4}
stnt1h {z1.h, z5.h, z9.h, z13.h}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF {nvectors:2}
stnt1h {z1.h, z9.h}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE {nvectors:4}
stnt1w {z1.s, z5.s, z9.s, z13.s}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE {nvectors:2}
stnt1w {z1.s, z9.s}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 {nvectors:4}
stnt1h {z1.h, z5.h, z9.h, z13.h}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16 {nvectors:2}
stnt1h {z1.h, z9.h}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 {nvectors:4}
stnt1w {z1.s, z5.s, z9.s, z13.s}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32 {nvectors:2}
stnt1w {z1.s, z9.s}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 {nvectors:4}
stnt1d {z1.d, z5.d, z9.d, z13.d}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64 {nvectors:2}
stnt1d {z1.d, z9.d}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 {nvectors:4}
stnt1b {z1.b, z5.b, z9.b, z13.b}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 {nvectors:2}
stnt1b {z1.b, z9.b}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 {nvectors:4}
stnt1h {z1.h, z5.h, z9.h, z13.h}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:VEC:UINT16 bdreg:REGISTER:VEC:UINT16 {nvectors:2}
stnt1h {z1.h, z9.h}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 {nvectors:4}
stnt1w {z1.s, z5.s, z9.s, z13.s}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:VEC:UINT32 bdreg:REGISTER:VEC:UINT32 {nvectors:2}
stnt1w {z1.s, z9.s}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 {nvectors:4}
stnt1d {z1.d, z5.d, z9.d, z13.d}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:VEC:UINT64 bdreg:REGISTER:VEC:UINT64 {nvectors:2}
stnt1d {z1.d, z9.d}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 {nvectors:4}
stnt1b {z1.b, z5.b, z9.b, z13.b}, p8, [x10]
### op store [MASK,MULTIVEC,NT] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 {nvectors:2}
stnt1b {z1.b, z9.b}, p8, [x10]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 ddreg:REGISTER:VEC:BF16 voffset:IMMEDIATE:-:- {nstructs:4}
st4h {z1.h, z2.h, z3.h, z4.h}, p1, [x10, #-32, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 ddreg:REGISTER:VEC:BF16 voffset:IMMEDIATE:-:- {nstructs:4} @far
st4h {z1.h, z2.h, z3.h, z4.h}, p1, [x10, #28, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 voffset:IMMEDIATE:-:- {nstructs:3}
st3h {z1.h, z2.h, z3.h}, p1, [x10, #-24, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 voffset:IMMEDIATE:-:- {nstructs:3} @far
st3h {z1.h, z2.h, z3.h}, p1, [x10, #21, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 voffset:IMMEDIATE:-:- {nstructs:2}
st2h {z1.h, z2.h}, p1, [x10, #-16, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 voffset:IMMEDIATE:-:- {nstructs:2} @far
st2h {z1.h, z2.h}, p1, [x10, #14, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE voffset:IMMEDIATE:-:- {nstructs:4}
st4d {z1.d, z2.d, z3.d, z4.d}, p1, [x10, #-32, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE voffset:IMMEDIATE:-:- {nstructs:4} @far
st4d {z1.d, z2.d, z3.d, z4.d}, p1, [x10, #28, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE voffset:IMMEDIATE:-:- {nstructs:3}
st3d {z1.d, z2.d, z3.d}, p1, [x10, #-24, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE voffset:IMMEDIATE:-:- {nstructs:3} @far
st3d {z1.d, z2.d, z3.d}, p1, [x10, #21, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE voffset:IMMEDIATE:-:- {nstructs:2}
st2d {z1.d, z2.d}, p1, [x10, #-16, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE voffset:IMMEDIATE:-:- {nstructs:2} @far
st2d {z1.d, z2.d}, p1, [x10, #14, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 voffset:IMMEDIATE:-:- {nstructs:4}
st4b {z1.b, z2.b, z3.b, z4.b}, p1, [x10, #-32, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 voffset:IMMEDIATE:-:- {nstructs:4} @far
st4b {z1.b, z2.b, z3.b, z4.b}, p1, [x10, #28, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 voffset:IMMEDIATE:-:- {nstructs:3}
st3b {z1.b, z2.b, z3.b}, p1, [x10, #-24, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 voffset:IMMEDIATE:-:- {nstructs:3} @far
st3b {z1.b, z2.b, z3.b}, p1, [x10, #21, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 voffset:IMMEDIATE:-:- {nstructs:2}
st2b {z1.b, z2.b}, p1, [x10, #-16, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 voffset:IMMEDIATE:-:- {nstructs:2} @far
st2b {z1.b, z2.b}, p1, [x10, #14, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 voffset:IMMEDIATE:-:- {nstructs:4}
st4b {z1.b, z2.b, z3.b, z4.b}, p1, [x10, #-32, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 voffset:IMMEDIATE:-:- {nstructs:4} @far
st4b {z1.b, z2.b, z3.b, z4.b}, p1, [x10, #28, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 voffset:IMMEDIATE:-:- {nstructs:3}
st3b {z1.b, z2.b, z3.b}, p1, [x10, #-24, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 voffset:IMMEDIATE:-:- {nstructs:3} @far
st3b {z1.b, z2.b, z3.b}, p1, [x10, #21, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 voffset:IMMEDIATE:-:- {nstructs:2}
st2b {z1.b, z2.b}, p1, [x10, #-16, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 voffset:IMMEDIATE:-:- {nstructs:2} @far
st2b {z1.b, z2.b}, p1, [x10, #14, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF voffset:IMMEDIATE:-:- {nstructs:4}
st4h {z1.h, z2.h, z3.h, z4.h}, p1, [x10, #-32, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF voffset:IMMEDIATE:-:- {nstructs:4} @far
st4h {z1.h, z2.h, z3.h, z4.h}, p1, [x10, #28, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF voffset:IMMEDIATE:-:- {nstructs:3}
st3h {z1.h, z2.h, z3.h}, p1, [x10, #-24, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF voffset:IMMEDIATE:-:- {nstructs:3} @far
st3h {z1.h, z2.h, z3.h}, p1, [x10, #21, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF voffset:IMMEDIATE:-:- {nstructs:2}
st2h {z1.h, z2.h}, p1, [x10, #-16, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF voffset:IMMEDIATE:-:- {nstructs:2} @far
st2h {z1.h, z2.h}, p1, [x10, #14, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE voffset:IMMEDIATE:-:- {nstructs:4}
st4w {z1.s, z2.s, z3.s, z4.s}, p1, [x10, #-32, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE voffset:IMMEDIATE:-:- {nstructs:4} @far
st4w {z1.s, z2.s, z3.s, z4.s}, p1, [x10, #28, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE voffset:IMMEDIATE:-:- {nstructs:3}
st3w {z1.s, z2.s, z3.s}, p1, [x10, #-24, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE voffset:IMMEDIATE:-:- {nstructs:3} @far
st3w {z1.s, z2.s, z3.s}, p1, [x10, #21, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE voffset:IMMEDIATE:-:- {nstructs:2}
st2w {z1.s, z2.s}, p1, [x10, #-16, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE voffset:IMMEDIATE:-:- {nstructs:2} @far
st2w {z1.s, z2.s}, p1, [x10, #14, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 voffset:IMMEDIATE:-:- {nstructs:4}
st4h {z1.h, z2.h, z3.h, z4.h}, p1, [x10, #-32, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 voffset:IMMEDIATE:-:- {nstructs:4} @far
st4h {z1.h, z2.h, z3.h, z4.h}, p1, [x10, #28, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 voffset:IMMEDIATE:-:- {nstructs:3}
st3h {z1.h, z2.h, z3.h}, p1, [x10, #-24, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 voffset:IMMEDIATE:-:- {nstructs:3} @far
st3h {z1.h, z2.h, z3.h}, p1, [x10, #21, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 voffset:IMMEDIATE:-:- {nstructs:2}
st2h {z1.h, z2.h}, p1, [x10, #-16, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 voffset:IMMEDIATE:-:- {nstructs:2} @far
st2h {z1.h, z2.h}, p1, [x10, #14, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 voffset:IMMEDIATE:-:- {nstructs:4}
st4w {z1.s, z2.s, z3.s, z4.s}, p1, [x10, #-32, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 voffset:IMMEDIATE:-:- {nstructs:4} @far
st4w {z1.s, z2.s, z3.s, z4.s}, p1, [x10, #28, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 voffset:IMMEDIATE:-:- {nstructs:3}
st3w {z1.s, z2.s, z3.s}, p1, [x10, #-24, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 voffset:IMMEDIATE:-:- {nstructs:3} @far
st3w {z1.s, z2.s, z3.s}, p1, [x10, #21, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 voffset:IMMEDIATE:-:- {nstructs:2}
st2w {z1.s, z2.s}, p1, [x10, #-16, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 voffset:IMMEDIATE:-:- {nstructs:2} @far
st2w {z1.s, z2.s}, p1, [x10, #14, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 voffset:IMMEDIATE:-:- {nstructs:4}
st4d {z1.d, z2.d, z3.d, z4.d}, p1, [x10, #-32, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 voffset:IMMEDIATE:-:- {nstructs:4} @far
st4d {z1.d, z2.d, z3.d, z4.d}, p1, [x10, #28, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 voffset:IMMEDIATE:-:- {nstructs:3}
st3d {z1.d, z2.d, z3.d}, p1, [x10, #-24, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 voffset:IMMEDIATE:-:- {nstructs:3} @far
st3d {z1.d, z2.d, z3.d}, p1, [x10, #21, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 voffset:IMMEDIATE:-:- {nstructs:2}
st2d {z1.d, z2.d}, p1, [x10, #-16, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 voffset:IMMEDIATE:-:- {nstructs:2} @far
st2d {z1.d, z2.d}, p1, [x10, #14, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 voffset:IMMEDIATE:-:- {nstructs:4}
st4b {z1.b, z2.b, z3.b, z4.b}, p1, [x10, #-32, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 voffset:IMMEDIATE:-:- {nstructs:4} @far
st4b {z1.b, z2.b, z3.b, z4.b}, p1, [x10, #28, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 voffset:IMMEDIATE:-:- {nstructs:3}
st3b {z1.b, z2.b, z3.b}, p1, [x10, #-24, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 voffset:IMMEDIATE:-:- {nstructs:3} @far
st3b {z1.b, z2.b, z3.b}, p1, [x10, #21, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 voffset:IMMEDIATE:-:- {nstructs:2}
st2b {z1.b, z2.b}, p1, [x10, #-16, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 voffset:IMMEDIATE:-:- {nstructs:2} @far
st2b {z1.b, z2.b}, p1, [x10, #14, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 voffset:IMMEDIATE:-:- {nstructs:4}
st4h {z1.h, z2.h, z3.h, z4.h}, p1, [x10, #-32, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 voffset:IMMEDIATE:-:- {nstructs:4} @far
st4h {z1.h, z2.h, z3.h, z4.h}, p1, [x10, #28, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 voffset:IMMEDIATE:-:- {nstructs:3}
st3h {z1.h, z2.h, z3.h}, p1, [x10, #-24, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 voffset:IMMEDIATE:-:- {nstructs:3} @far
st3h {z1.h, z2.h, z3.h}, p1, [x10, #21, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 voffset:IMMEDIATE:-:- {nstructs:2}
st2h {z1.h, z2.h}, p1, [x10, #-16, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 voffset:IMMEDIATE:-:- {nstructs:2} @far
st2h {z1.h, z2.h}, p1, [x10, #14, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 voffset:IMMEDIATE:-:- {nstructs:4}
st4w {z1.s, z2.s, z3.s, z4.s}, p1, [x10, #-32, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 voffset:IMMEDIATE:-:- {nstructs:4} @far
st4w {z1.s, z2.s, z3.s, z4.s}, p1, [x10, #28, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 voffset:IMMEDIATE:-:- {nstructs:3}
st3w {z1.s, z2.s, z3.s}, p1, [x10, #-24, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 voffset:IMMEDIATE:-:- {nstructs:3} @far
st3w {z1.s, z2.s, z3.s}, p1, [x10, #21, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 voffset:IMMEDIATE:-:- {nstructs:2}
st2w {z1.s, z2.s}, p1, [x10, #-16, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 voffset:IMMEDIATE:-:- {nstructs:2} @far
st2w {z1.s, z2.s}, p1, [x10, #14, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 voffset:IMMEDIATE:-:- {nstructs:4}
st4d {z1.d, z2.d, z3.d, z4.d}, p1, [x10, #-32, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 voffset:IMMEDIATE:-:- {nstructs:4} @far
st4d {z1.d, z2.d, z3.d, z4.d}, p1, [x10, #28, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 voffset:IMMEDIATE:-:- {nstructs:3}
st3d {z1.d, z2.d, z3.d}, p1, [x10, #-24, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 voffset:IMMEDIATE:-:- {nstructs:3} @far
st3d {z1.d, z2.d, z3.d}, p1, [x10, #21, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 voffset:IMMEDIATE:-:- {nstructs:2}
st2d {z1.d, z2.d}, p1, [x10, #-16, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 voffset:IMMEDIATE:-:- {nstructs:2} @far
st2d {z1.d, z2.d}, p1, [x10, #14, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 voffset:IMMEDIATE:-:- {nstructs:4}
st4b {z1.b, z2.b, z3.b, z4.b}, p1, [x10, #-32, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 voffset:IMMEDIATE:-:- {nstructs:4} @far
st4b {z1.b, z2.b, z3.b, z4.b}, p1, [x10, #28, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 voffset:IMMEDIATE:-:- {nstructs:3}
st3b {z1.b, z2.b, z3.b}, p1, [x10, #-24, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 voffset:IMMEDIATE:-:- {nstructs:3} @far
st3b {z1.b, z2.b, z3.b}, p1, [x10, #21, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 voffset:IMMEDIATE:-:- {nstructs:2}
st2b {z1.b, z2.b}, p1, [x10, #-16, MUL VL]
### op store [MASK,STRUCT,VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 voffset:IMMEDIATE:-:- {nstructs:2} @far
st2b {z1.b, z2.b}, p1, [x10, #14, MUL VL]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 ddreg:REGISTER:VEC:BF16 {nstructs:4}
st4h {z1.h, z2.h, z3.h, z4.h}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 cdreg:REGISTER:VEC:BF16 {nstructs:3}
st3h {z1.h, z2.h, z3.h}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16 {nstructs:2}
st2h {z1.h, z2.h}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE ddreg:REGISTER:VEC:DOUBLE {nstructs:4}
st4d {z1.d, z2.d, z3.d, z4.d}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE cdreg:REGISTER:VEC:DOUBLE {nstructs:3}
st3d {z1.d, z2.d, z3.d}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE {nstructs:2}
st2d {z1.d, z2.d}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 ddreg:REGISTER:VEC:FP8E4M3 {nstructs:4}
st4b {z1.b, z2.b, z3.b, z4.b}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:FP8E4M3 {nstructs:3}
st3b {z1.b, z2.b, z3.b}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 {nstructs:2}
st2b {z1.b, z2.b}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 ddreg:REGISTER:VEC:FP8E5M2 {nstructs:4}
st4b {z1.b, z2.b, z3.b, z4.b}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:FP8E5M2 {nstructs:3}
st3b {z1.b, z2.b, z3.b}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 {nstructs:2}
st2b {z1.b, z2.b}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF ddreg:REGISTER:VEC:HALF {nstructs:4}
st4h {z1.h, z2.h, z3.h, z4.h}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF cdreg:REGISTER:VEC:HALF {nstructs:3}
st3h {z1.h, z2.h, z3.h}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF {nstructs:2}
st2h {z1.h, z2.h}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE ddreg:REGISTER:VEC:SINGLE {nstructs:4}
st4w {z1.s, z2.s, z3.s, z4.s}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE cdreg:REGISTER:VEC:SINGLE {nstructs:3}
st3w {z1.s, z2.s, z3.s}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE {nstructs:2}
st2w {z1.s, z2.s}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 ddreg:REGISTER:VEC:SINT16 {nstructs:4}
st4h {z1.h, z2.h, z3.h, z4.h}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 cdreg:REGISTER:VEC:SINT16 {nstructs:3}
st3h {z1.h, z2.h, z3.h}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16 {nstructs:2}
st2h {z1.h, z2.h}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 ddreg:REGISTER:VEC:SINT32 {nstructs:4}
st4w {z1.s, z2.s, z3.s, z4.s}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 cdreg:REGISTER:VEC:SINT32 {nstructs:3}
st3w {z1.s, z2.s, z3.s}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32 {nstructs:2}
st2w {z1.s, z2.s}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 ddreg:REGISTER:VEC:SINT64 {nstructs:4}
st4d {z1.d, z2.d, z3.d, z4.d}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 cdreg:REGISTER:VEC:SINT64 {nstructs:3}
st3d {z1.d, z2.d, z3.d}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64 {nstructs:2}
st2d {z1.d, z2.d}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 ddreg:REGISTER:VEC:SINT8 {nstructs:4}
st4b {z1.b, z2.b, z3.b, z4.b}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT8 {nstructs:3}
st3b {z1.b, z2.b, z3.b}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8 {nstructs:2}
st2b {z1.b, z2.b}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 ddreg:REGISTER:VEC:UINT16 {nstructs:4}
st4h {z1.h, z2.h, z3.h, z4.h}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 cdreg:REGISTER:VEC:UINT16 {nstructs:3}
st3h {z1.h, z2.h, z3.h}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16 {nstructs:2}
st2h {z1.h, z2.h}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 ddreg:REGISTER:VEC:UINT32 {nstructs:4}
st4w {z1.s, z2.s, z3.s, z4.s}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 cdreg:REGISTER:VEC:UINT32 {nstructs:3}
st3w {z1.s, z2.s, z3.s}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32 {nstructs:2}
st2w {z1.s, z2.s}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 ddreg:REGISTER:VEC:UINT64 {nstructs:4}
st4d {z1.d, z2.d, z3.d, z4.d}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 cdreg:REGISTER:VEC:UINT64 {nstructs:3}
st3d {z1.d, z2.d, z3.d}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64 {nstructs:2}
st2d {z1.d, z2.d}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 ddreg:REGISTER:VEC:UINT8 {nstructs:4}
st4b {z1.b, z2.b, z3.b, z4.b}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT8 {nstructs:3}
st3b {z1.b, z2.b, z3.b}, p1, [x10]
### op store [MASK,STRUCT] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8 {nstructs:2}
st2b {z1.b, z2.b}, p1, [x10]
### op store [MASK,VINDEX] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE vidxreg:REGISTER:VEC:SINT32 {it:INT32}
st1d {z1.d}, p1, [x10, z2.d, sxtw]
### op store [MASK,VINDEX] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE vidxreg:REGISTER:VEC:SINT64 {it:INT64}
st1d {z1.d}, p1, [x10, z2.d]
### op store [MASK,VINDEX] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE vidxreg:REGISTER:VEC:SINT32 {it:INT32}
st1w {z1.s}, p1, [x10, z2.s, sxtw]
### op store [MASK,VINDEX] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 vidxreg:REGISTER:VEC:SINT32 {it:INT32}
st1w {z1.s}, p1, [x10, z2.s, sxtw]
### op store [MASK,VINDEX] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 vidxreg:REGISTER:VEC:SINT32 {it:INT32}
st1d {z1.d}, p1, [x10, z2.d, sxtw]
### op store [MASK,VINDEX] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 vidxreg:REGISTER:VEC:SINT64 {it:INT64}
st1d {z1.d}, p1, [x10, z2.d]
### op store [MASK,VINDEX] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 vidxreg:REGISTER:VEC:SINT32 {it:INT32}
st1w {z1.s}, p1, [x10, z2.s, sxtw]
### op store [MASK,VINDEX] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 vidxreg:REGISTER:VEC:SINT32 {it:INT32}
st1d {z1.d}, p1, [x10, z2.d, sxtw]
### op store [MASK,VINDEX] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 vidxreg:REGISTER:VEC:SINT64 {it:INT64}
st1d {z1.d}, p1, [x10, z2.d]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 voffset:IMMEDIATE:-:-
st1h {z1.h}, p1, [x10, #-8, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 voffset:IMMEDIATE:-:- @far
st1h {z1.h}, p1, [x10, #7, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE voffset:IMMEDIATE:-:-
st1d {z1.d}, p1, [x10, #-8, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE voffset:IMMEDIATE:-:- @far
st1d {z1.d}, p1, [x10, #7, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 voffset:IMMEDIATE:-:-
st1b {z1.b}, p1, [x10, #-8, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 voffset:IMMEDIATE:-:- @far
st1b {z1.b}, p1, [x10, #7, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 voffset:IMMEDIATE:-:-
st1b {z1.b}, p1, [x10, #-8, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 voffset:IMMEDIATE:-:- @far
st1b {z1.b}, p1, [x10, #7, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF voffset:IMMEDIATE:-:-
st1h {z1.h}, p1, [x10, #-8, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF voffset:IMMEDIATE:-:- @far
st1h {z1.h}, p1, [x10, #7, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE voffset:IMMEDIATE:-:-
st1w {z1.s}, p1, [x10, #-8, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE voffset:IMMEDIATE:-:- @far
st1w {z1.s}, p1, [x10, #7, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 voffset:IMMEDIATE:-:-
st1h {z1.h}, p1, [x10, #-8, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 voffset:IMMEDIATE:-:- @far
st1h {z1.h}, p1, [x10, #7, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 voffset:IMMEDIATE:-:-
st1w {z1.s}, p1, [x10, #-8, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 voffset:IMMEDIATE:-:- @far
st1w {z1.s}, p1, [x10, #7, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 voffset:IMMEDIATE:-:-
st1d {z1.d}, p1, [x10, #-8, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 voffset:IMMEDIATE:-:- @far
st1d {z1.d}, p1, [x10, #7, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 voffset:IMMEDIATE:-:-
st1b {z1.b}, p1, [x10, #-8, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 voffset:IMMEDIATE:-:- @far
st1b {z1.b}, p1, [x10, #7, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 voffset:IMMEDIATE:-:-
st1h {z1.h}, p1, [x10, #-8, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 voffset:IMMEDIATE:-:- @far
st1h {z1.h}, p1, [x10, #7, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 voffset:IMMEDIATE:-:-
st1w {z1.s}, p1, [x10, #-8, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 voffset:IMMEDIATE:-:- @far
st1w {z1.s}, p1, [x10, #7, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 voffset:IMMEDIATE:-:-
st1d {z1.d}, p1, [x10, #-8, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 voffset:IMMEDIATE:-:- @far
st1d {z1.d}, p1, [x10, #7, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 voffset:IMMEDIATE:-:-
st1b {z1.b}, p1, [x10, #-8, MUL VL]
### op store [MASK,VOFFSET] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 voffset:IMMEDIATE:-:- @far
st1b {z1.b}, p1, [x10, #7, MUL VL]
### op store [MASK] adreg:REGISTER:VEC:BF16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16
st1h {z1.h}, p1, [x10]
### op store [MASK] adreg:REGISTER:VEC:DOUBLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE
st1d {z1.d}, p1, [x10]
### op store [MASK] adreg:REGISTER:VEC:FP8E4M3 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3
st1b {z1.b}, p1, [x10]
### op store [MASK] adreg:REGISTER:VEC:FP8E5M2 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2
st1b {z1.b}, p1, [x10]
### op store [MASK] adreg:REGISTER:VEC:HALF agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF
st1h {z1.h}, p1, [x10]
### op store [MASK] adreg:REGISTER:VEC:SINGLE agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE
st1w {z1.s}, p1, [x10]
### op store [MASK] adreg:REGISTER:VEC:SINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16
st1h {z1.h}, p1, [x10]
### op store [MASK] adreg:REGISTER:VEC:SINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32
st1w {z1.s}, p1, [x10]
### op store [MASK] adreg:REGISTER:VEC:SINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64
st1d {z1.d}, p1, [x10]
### op store [MASK] adreg:REGISTER:VEC:SINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8
st1b {z1.b}, p1, [x10]
### op store [MASK] adreg:REGISTER:VEC:UINT16 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16
st1h {z1.h}, p1, [x10]
### op store [MASK] adreg:REGISTER:VEC:UINT32 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32
st1w {z1.s}, p1, [x10]
### op store [MASK] adreg:REGISTER:VEC:UINT64 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64
st1d {z1.d}, p1, [x10]
### op store [MASK] adreg:REGISTER:VEC:UINT8 agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8
st1b {z1.b}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:TILE:BF16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
st1h {za0v.h[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:TILE:BF16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
st1h {za0v.h[w12, 7]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:TILE:BF16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
st1h {za0h.h[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 adreg:REGISTER:TILE:BF16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
st1h {za0h.h[w12, 7]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:TILE:DOUBLE{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
st1d {za0v.d[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:TILE:DOUBLE{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
st1d {za0v.d[w12, 1]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:TILE:DOUBLE{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
st1d {za0h.d[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE adreg:REGISTER:TILE:DOUBLE{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
st1d {za0h.d[w12, 1]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:TILE:FP8E4M3{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
st1b {za0v.b[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:TILE:FP8E4M3{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
st1b {za0v.b[w12, 15]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:TILE:FP8E4M3{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
st1b {za0h.b[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 adreg:REGISTER:TILE:FP8E4M3{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
st1b {za0h.b[w12, 15]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:TILE:FP8E5M2{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
st1b {za0v.b[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:TILE:FP8E5M2{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
st1b {za0v.b[w12, 15]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:TILE:FP8E5M2{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
st1b {za0h.b[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 adreg:REGISTER:TILE:FP8E5M2{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
st1b {za0h.b[w12, 15]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:TILE:HALF{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
st1h {za0v.h[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:TILE:HALF{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
st1h {za0v.h[w12, 7]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:TILE:HALF{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
st1h {za0h.h[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF adreg:REGISTER:TILE:HALF{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
st1h {za0h.h[w12, 7]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:TILE:SINGLE{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
st1w {za0v.s[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:TILE:SINGLE{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
st1w {za0v.s[w12, 3]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:TILE:SINGLE{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
st1w {za0h.s[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE adreg:REGISTER:TILE:SINGLE{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
st1w {za0h.s[w12, 3]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:TILE:SINT16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
st1h {za0v.h[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:TILE:SINT16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
st1h {za0v.h[w12, 7]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:TILE:SINT16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
st1h {za0h.h[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 adreg:REGISTER:TILE:SINT16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
st1h {za0h.h[w12, 7]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:TILE:SINT32{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
st1w {za0v.s[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:TILE:SINT32{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
st1w {za0v.s[w12, 3]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:TILE:SINT32{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
st1w {za0h.s[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 adreg:REGISTER:TILE:SINT32{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
st1w {za0h.s[w12, 3]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:TILE:SINT64{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
st1d {za0v.d[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:TILE:SINT64{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
st1d {za0v.d[w12, 1]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:TILE:SINT64{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
st1d {za0h.d[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 adreg:REGISTER:TILE:SINT64{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
st1d {za0h.d[w12, 1]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:TILE:SINT8{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
st1b {za0v.b[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:TILE:SINT8{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
st1b {za0v.b[w12, 15]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:TILE:SINT8{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
st1b {za0h.b[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 adreg:REGISTER:TILE:SINT8{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
st1b {za0h.b[w12, 15]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:TILE:UINT16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
st1h {za0v.h[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:TILE:UINT16{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
st1h {za0v.h[w12, 7]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:TILE:UINT16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
st1h {za0h.h[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 adreg:REGISTER:TILE:UINT16{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
st1h {za0h.h[w12, 7]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:TILE:UINT32{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
st1w {za0v.s[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:TILE:UINT32{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
st1w {za0v.s[w12, 3]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:TILE:UINT32{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
st1w {za0h.s[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 adreg:REGISTER:TILE:UINT32{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
st1w {za0h.s[w12, 3]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:TILE:UINT64{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
st1d {za0v.d[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:TILE:UINT64{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
st1d {za0v.d[w12, 1]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:TILE:UINT64{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
st1d {za0h.d[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 adreg:REGISTER:TILE:UINT64{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
st1d {za0h.d[w12, 1]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:TILE:UINT8{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:-
st1b {za0v.b[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:TILE:UINT8{COL} adreg_colreg:REGISTER:GP:SINT32 adreg_immcol:IMMEDIATE:-:- @far
st1b {za0v.b[w12, 15]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:TILE:UINT8{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:-
st1b {za0h.b[w12, 0]}, p1, [x10]
### op store [MASK] agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 adreg:REGISTER:TILE:UINT8{ROW} adreg_rowreg:REGISTER:GP:SINT32 adreg_immrow:IMMEDIATE:-:- @far
st1b {za0h.b[w12, 15]}, p1, [x10]
### op store [PARAM] adreg:REGISTER:FP:DOUBLE param:NAME:-:-
str d1, %[p]
### op store [PARAM] adreg:REGISTER:FP:FP8E4M3 param:NAME:-:-
str b1, %[p]
### op store [PARAM] adreg:REGISTER:FP:FP8E5M2 param:NAME:-:-
str b1, %[p]
### op store [PARAM] adreg:REGISTER:FP:HALF param:NAME:-:-
str h1, %[p]
### op store [PARAM] adreg:REGISTER:FP:SINGLE param:NAME:-:-
str s1, %[p]
### op store [PARAM] adreg:REGISTER:GP:SINT16 param:NAME:-:-
strh w10, %[p]
### op store [PARAM] adreg:REGISTER:GP:SINT32 param:NAME:-:-
str w10, %[p]
### op store [PARAM] adreg:REGISTER:GP:SINT64 param:NAME:-:-
str x10, %[p]
### op store [PARAM] adreg:REGISTER:GP:SINT8 param:NAME:-:-
strb w10, %[p]
### op store [PARAM] adreg:REGISTER:GP:UINT16 param:NAME:-:-
strh w10, %[p]
### op store [PARAM] adreg:REGISTER:GP:UINT32 param:NAME:-:-
str w10, %[p]
### op store [PARAM] adreg:REGISTER:GP:UINT64 param:NAME:-:-
str x10, %[p]
### op store [PARAM] adreg:REGISTER:GP:UINT8 param:NAME:-:-
strb w10, %[p]
### op store [POSTINC] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
str d1, [x10], #-256
### op store [POSTINC] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
str d1, [x10], #255
### op store [POSTINC] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
str d1, [x10], x11
### op store [POSTINC] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
str b1, [x10], #-256
### op store [POSTINC] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
str b1, [x10], #255
### op store [POSTINC] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
str b1, [x10], x11
### op store [POSTINC] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
str b1, [x10], #-256
### op store [POSTINC] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
str b1, [x10], #255
### op store [POSTINC] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
str b1, [x10], x11
### op store [POSTINC] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
str h1, [x10], #-256
### op store [POSTINC] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
str h1, [x10], #255
### op store [POSTINC] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
str h1, [x10], x11
### op store [POSTINC] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
str s1, [x10], #-256
### op store [POSTINC] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
str s1, [x10], #255
### op store [POSTINC] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
str s1, [x10], x11
### op store [POSTINC] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
strh w10, [x11], #-256
### op store [POSTINC] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
strh w10, [x11], #255
### op store [POSTINC] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
strh w10, [x11], x12
### op store [POSTINC] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
str w10, [x11], #-256
### op store [POSTINC] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
str w10, [x11], #255
### op store [POSTINC] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
str w10, [x11], x12
### op store [POSTINC] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
str x10, [x11], #-256
### op store [POSTINC] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
str x10, [x11], #255
### op store [POSTINC] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
str x10, [x11], x12
### op store [POSTINC] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
strb w10, [x11], #-256
### op store [POSTINC] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
strb w10, [x11], #255
### op store [POSTINC] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
strb w10, [x11], x12
### op store [POSTINC] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
strh w10, [x11], #-256
### op store [POSTINC] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
strh w10, [x11], #255
### op store [POSTINC] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
strh w10, [x11], x12
### op store [POSTINC] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
str w10, [x11], #-256
### op store [POSTINC] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
str w10, [x11], #255
### op store [POSTINC] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
str w10, [x11], x12
### op store [POSTINC] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
str x10, [x11], #-256
### op store [POSTINC] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
str x10, [x11], #255
### op store [POSTINC] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
str x10, [x11], x12
### op store [POSTINC] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64
strb w10, [x11], #-256
### op store [POSTINC] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 iinc:IMMEDIATE:-:SINT64 @far
strb w10, [x11], #255
### op store [POSTINC] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
strb w10, [x11], x12
### op store [] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64
str d1, [x10]
### op store [] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64
str b1, [x10]
### op store [] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64
str b1, [x10]
### op store [] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64
str h1, [x10]
### op store [] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64
str s1, [x10]
### op store [] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64
strh w10, [x11]
### op store [] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64
str w10, [x11]
### op store [] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64
str x10, [x11]
### op store [] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64
strb w10, [x11]
### op store [] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64
strh w10, [x11]
### op store [] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64
str w10, [x11]
### op store [] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64
str x10, [x11]
### op store [] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64
strb w10, [x11]
### op sub [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64
sub x12,x10,x11
### op sub [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64{ISHIFT} cdreg:REGISTER:GP:SINT64 bdreg_shift:IMMEDIATE:-:-
sub x12,x10,x11
### op sub [] adreg:REGISTER:GP:SINT64 bdreg:REGISTER:GP:SINT64{ISHIFT} cdreg:REGISTER:GP:SINT64 bdreg_shift:IMMEDIATE:-:- @far
sub x12,x10,x11, LSL #63
### op sub [] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:-
sub x11,x10,#-4095
### op sub [] adreg:REGISTER:GP:SINT64 cdreg:REGISTER:GP:SINT64 bimm:IMMEDIATE:-:- @far
sub x11,x10,#4095
### op sub [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64
sub x12,x10,x11
### op sub [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64{ISHIFT} cdreg:REGISTER:GP:UINT64 bdreg_shift:IMMEDIATE:-:-
sub x12,x10,x11
### op sub [] adreg:REGISTER:GP:UINT64 bdreg:REGISTER:GP:UINT64{ISHIFT} cdreg:REGISTER:GP:UINT64 bdreg_shift:IMMEDIATE:-:- @far
sub x12,x10,x11, LSL #63
### op sub [] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:-
sub x11,x10,#-4095
### op sub [] adreg:REGISTER:GP:UINT64 cdreg:REGISTER:GP:UINT64 bimm:IMMEDIATE:-:- @far
sub x11,x10,#4095
