method c_simd_size_function()
method compiler_flags()
method create_callconv(name=default)
method enabled_features()
method freg(dt=DOUBLE, reg_idx=0)
method freg(dt=HALF, reg_idx=0)
method freg(dt=SINGLE, reg_idx=0)
method get_param_value(name=dummy)
method get_parameters()
method greg(reg_idx=0)
method is_vla()
method isaclear()
method jvzero(dt=DOUBLE, freg=s2, greg=x0, label=someloop, vreg1=z0, vreg2=z1)
method jvzero(dt=HALF, freg=s2, greg=x0, label=someloop, vreg1=z0, vreg2=z1)
method jvzero(dt=SINGLE, freg=s2, greg=x0, label=someloop, vreg1=z0, vreg2=z1)
method labelstr(label=label)
method loopbegin_nz(label=someloop, labelskip=someloop_nz, reg=x0)
method max_fregs()
method max_gregs()
method max_tregs(dt=DOUBLE)
method max_tregs(dt=HALF)
method max_tregs(dt=SINGLE)
method max_vregs()
method supported_on_host()
method supportedby_cpuinfo(cpuinfo=invalid_isa)
method tile_types()
method treg_tag(dt=DOUBLE)
method treg_tag(dt=HALF)
method treg_tag(dt=SINGLE)
method vreg(reg_idx=0)
op add [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE{BLOCKLANE} cdreg:REGISTER:VEC:DOUBLE bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:2}
op add [] adreg:REGISTER:VEC:DOUBLE bdreg:REGISTER:VEC:DOUBLE{BLOCKLANE} cdreg:REGISTER:VEC:DOUBLE bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:2} @far
op add [] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8}
op add [] adreg:REGISTER:VEC:HALF bdreg:REGISTER:VEC:HALF{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8} @far
op add [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:4}
op add [] adreg:REGISTER:VEC:SINGLE bdreg:REGISTER:VEC:SINGLE{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:4} @far
op add [] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{BLOCKLANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8}
op add [] adreg:REGISTER:VEC:SINT16 bdreg:REGISTER:VEC:SINT16{BLOCKLANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:8} @far
op add [] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32{BLOCKLANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:4}
op add [] adreg:REGISTER:VEC:SINT32 bdreg:REGISTER:VEC:SINT32{BLOCKLANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:4} @far
op add [] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64{BLOCKLANE} cdreg:REGISTER:VEC:SINT64 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:2}
op add [] adreg:REGISTER:VEC:SINT64 bdreg:REGISTER:VEC:SINT64{BLOCKLANE} cdreg:REGISTER:VEC:SINT64 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:2} @far
op add [] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:16}
op add [] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:16} @far
op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
op fma [NP,PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
op fma [NP,PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
op fma [NP,PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
op fma [NP,PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
op fma [NP,PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
op fma [NP,PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
op fma [NP,PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
op fma [NP,PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
op fma [NP,PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
op fma [NP,PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
op fma [NP,PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{BLOCKLANE} cdreg:REGISTER:VEC:UINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
op fma [NP,PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{BLOCKLANE} cdreg:REGISTER:VEC:UINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
op fma [NP,PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{BLOCKLANE} cdreg:REGISTER:VEC:UINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
op fma [NP,PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{BLOCKLANE} cdreg:REGISTER:VEC:UINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
op fma [NP] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:16}
op fma [NP] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:16} @far
op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
op fma [PART] adreg:REGISTER:VEC:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:HALF part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2 cdreg:REGISTER:VEC:SINGLE part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BLOCKLANE} cdreg:REGISTER:VEC:HALF bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
op fma [PART] adreg:REGISTER:VEC:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BLOCKLANE} cdreg:REGISTER:VEC:SINGLE bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8 cdreg:REGISTER:VEC:SINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
op fma [PART] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED}
op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8 cdreg:REGISTER:VEC:UINT32 part:IMMEDIATE:-:- {widening_method:SPLIT_INTERLEAVED} @far
op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{BLOCKLANE} cdreg:REGISTER:VEC:UINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{BLOCKLANE} cdreg:REGISTER:VEC:UINT16 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{BLOCKLANE} cdreg:REGISTER:VEC:UINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED}
op fma [PART] adreg:REGISTER:VEC:UINT8 bdreg:REGISTER:VEC:UINT8{BLOCKLANE} cdreg:REGISTER:VEC:UINT32 bdreg_lane:IMMEDIATE:-:- part:IMMEDIATE:-:- {bdreg_blocksize:16,widening_method:SPLIT_INTERLEAVED} @far
op fma [] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:16}
op fma [] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:16} @far
op load [MASK,STRUCT] adreg:REGISTER:VEC:BF16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16{BCAST} cdreg:REGISTER:VEC:BF16{BCAST} ddreg:REGISTER:VEC:BF16{BCAST} {nstructs:4}
op load [MASK,STRUCT] adreg:REGISTER:VEC:BF16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16{BCAST} cdreg:REGISTER:VEC:BF16{BCAST} {nstructs:3}
op load [MASK,STRUCT] adreg:REGISTER:VEC:BF16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:BF16 bdreg:REGISTER:VEC:BF16{BCAST} {nstructs:2}
op load [MASK,STRUCT] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE{BCAST} cdreg:REGISTER:VEC:DOUBLE{BCAST} ddreg:REGISTER:VEC:DOUBLE{BCAST} {nstructs:4}
op load [MASK,STRUCT] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE{BCAST} cdreg:REGISTER:VEC:DOUBLE{BCAST} {nstructs:3}
op load [MASK,STRUCT] adreg:REGISTER:VEC:DOUBLE{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE{BCAST} {nstructs:2}
op load [MASK,STRUCT] adreg:REGISTER:VEC:FP8E4M3{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BCAST} cdreg:REGISTER:VEC:FP8E4M3{BCAST} ddreg:REGISTER:VEC:FP8E4M3{BCAST} {nstructs:4}
op load [MASK,STRUCT] adreg:REGISTER:VEC:FP8E4M3{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BCAST} cdreg:REGISTER:VEC:FP8E4M3{BCAST} {nstructs:3}
op load [MASK,STRUCT] adreg:REGISTER:VEC:FP8E4M3{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BCAST} {nstructs:2}
op load [MASK,STRUCT] adreg:REGISTER:VEC:FP8E5M2{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BCAST} cdreg:REGISTER:VEC:FP8E5M2{BCAST} ddreg:REGISTER:VEC:FP8E5M2{BCAST} {nstructs:4}
op load [MASK,STRUCT] adreg:REGISTER:VEC:FP8E5M2{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BCAST} cdreg:REGISTER:VEC:FP8E5M2{BCAST} {nstructs:3}
op load [MASK,STRUCT] adreg:REGISTER:VEC:FP8E5M2{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BCAST} {nstructs:2}
op load [MASK,STRUCT] adreg:REGISTER:VEC:HALF{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF{BCAST} cdreg:REGISTER:VEC:HALF{BCAST} ddreg:REGISTER:VEC:HALF{BCAST} {nstructs:4}
op load [MASK,STRUCT] adreg:REGISTER:VEC:HALF{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF{BCAST} cdreg:REGISTER:VEC:HALF{BCAST} {nstructs:3}
op load [MASK,STRUCT] adreg:REGISTER:VEC:HALF{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF{BCAST} {nstructs:2}
op load [MASK,STRUCT] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE{BCAST} cdreg:REGISTER:VEC:SINGLE{BCAST} ddreg:REGISTER:VEC:SINGLE{BCAST} {nstructs:4}
op load [MASK,STRUCT] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE{BCAST} cdreg:REGISTER:VEC:SINGLE{BCAST} {nstructs:3}
op load [MASK,STRUCT] adreg:REGISTER:VEC:SINGLE{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE{BCAST} {nstructs:2}
op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16{BCAST} cdreg:REGISTER:VEC:SINT16{BCAST} ddreg:REGISTER:VEC:SINT16{BCAST} {nstructs:4}
op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16{BCAST} cdreg:REGISTER:VEC:SINT16{BCAST} {nstructs:3}
op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16{BCAST} {nstructs:2}
op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32{BCAST} cdreg:REGISTER:VEC:SINT32{BCAST} ddreg:REGISTER:VEC:SINT32{BCAST} {nstructs:4}
op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32{BCAST} cdreg:REGISTER:VEC:SINT32{BCAST} {nstructs:3}
op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT32{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32{BCAST} {nstructs:2}
op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64{BCAST} cdreg:REGISTER:VEC:SINT64{BCAST} ddreg:REGISTER:VEC:SINT64{BCAST} {nstructs:4}
op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64{BCAST} cdreg:REGISTER:VEC:SINT64{BCAST} {nstructs:3}
op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT64{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64{BCAST} {nstructs:2}
op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT8{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8{BCAST} cdreg:REGISTER:VEC:SINT8{BCAST} ddreg:REGISTER:VEC:SINT8{BCAST} {nstructs:4}
op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT8{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8{BCAST} cdreg:REGISTER:VEC:SINT8{BCAST} {nstructs:3}
op load [MASK,STRUCT] adreg:REGISTER:VEC:SINT8{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8{BCAST} {nstructs:2}
op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16{BCAST} cdreg:REGISTER:VEC:UINT16{BCAST} ddreg:REGISTER:VEC:UINT16{BCAST} {nstructs:4}
op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16{BCAST} cdreg:REGISTER:VEC:UINT16{BCAST} {nstructs:3}
op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT16{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16{BCAST} {nstructs:2}
op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32{BCAST} cdreg:REGISTER:VEC:UINT32{BCAST} ddreg:REGISTER:VEC:UINT32{BCAST} {nstructs:4}
op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32{BCAST} cdreg:REGISTER:VEC:UINT32{BCAST} {nstructs:3}
op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT32{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32{BCAST} {nstructs:2}
op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64{BCAST} cdreg:REGISTER:VEC:UINT64{BCAST} ddreg:REGISTER:VEC:UINT64{BCAST} {nstructs:4}
op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64{BCAST} cdreg:REGISTER:VEC:UINT64{BCAST} {nstructs:3}
op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT64{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64{BCAST} {nstructs:2}
op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT8{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8{BCAST} cdreg:REGISTER:VEC:UINT8{BCAST} ddreg:REGISTER:VEC:UINT8{BCAST} {nstructs:4}
op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT8{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8{BCAST} cdreg:REGISTER:VEC:UINT8{BCAST} {nstructs:3}
op load [MASK,STRUCT] adreg:REGISTER:VEC:UINT8{BCAST} agreg:REGISTER:GP:UINT64 amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8{BCAST} {nstructs:2}
op load [PARAM] adreg:REGISTER:FP:DOUBLE param:NAME:-:-
op load [PARAM] adreg:REGISTER:FP:FP8E4M3 param:NAME:-:-
op load [PARAM] adreg:REGISTER:FP:FP8E5M2 param:NAME:-:-
op load [PARAM] adreg:REGISTER:FP:HALF param:NAME:-:-
op load [PARAM] adreg:REGISTER:FP:SINGLE param:NAME:-:-
op load [PARAM] adreg:REGISTER:GP:SINT16 param:NAME:-:-
op load [PARAM] adreg:REGISTER:GP:SINT32 param:NAME:-:-
op load [PARAM] adreg:REGISTER:GP:SINT64 param:NAME:-:-
op load [PARAM] adreg:REGISTER:GP:SINT8 param:NAME:-:-
op load [PARAM] adreg:REGISTER:GP:UINT16 param:NAME:-:-
op load [PARAM] adreg:REGISTER:GP:UINT32 param:NAME:-:-
op load [PARAM] adreg:REGISTER:GP:UINT64 param:NAME:-:-
op load [PARAM] adreg:REGISTER:GP:UINT8 param:NAME:-:-
op load [POSTINC] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op load [POSTINC] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op load [POSTINC] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op load [POSTINC] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op load [POSTINC] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op load [POSTINC] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op load [POSTINC] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op load [POSTINC] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op load [POSTINC] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op load [POSTINC] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op load [POSTINC] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op load [POSTINC] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op load [POSTINC] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op move [MASK] amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE{BCAST} adreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:-
op move [MASK] amreg:REGISTER:MASK:DOUBLE bdreg:REGISTER:VEC:DOUBLE{BCAST} adreg:REGISTER:VEC:DOUBLE{ILANE} adreg_lane:IMMEDIATE:-:- @far
op move [MASK] amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BCAST} adreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:-
op move [MASK] amreg:REGISTER:MASK:FP8E4M3 bdreg:REGISTER:VEC:FP8E4M3{BCAST} adreg:REGISTER:VEC:FP8E4M3{ILANE} adreg_lane:IMMEDIATE:-:- @far
op move [MASK] amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BCAST} adreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:-
op move [MASK] amreg:REGISTER:MASK:FP8E5M2 bdreg:REGISTER:VEC:FP8E5M2{BCAST} adreg:REGISTER:VEC:FP8E5M2{ILANE} adreg_lane:IMMEDIATE:-:- @far
op move [MASK] amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF{BCAST} adreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:-
op move [MASK] amreg:REGISTER:MASK:HALF bdreg:REGISTER:VEC:HALF{BCAST} adreg:REGISTER:VEC:HALF{ILANE} adreg_lane:IMMEDIATE:-:- @far
op move [MASK] amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE{BCAST} adreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:-
op move [MASK] amreg:REGISTER:MASK:SINGLE bdreg:REGISTER:VEC:SINGLE{BCAST} adreg:REGISTER:VEC:SINGLE{ILANE} adreg_lane:IMMEDIATE:-:- @far
op move [MASK] amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16{BCAST} adreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:-
op move [MASK] amreg:REGISTER:MASK:SINT16 bdreg:REGISTER:VEC:SINT16{BCAST} adreg:REGISTER:VEC:SINT16{ILANE} adreg_lane:IMMEDIATE:-:- @far
op move [MASK] amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32{BCAST} adreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:-
op move [MASK] amreg:REGISTER:MASK:SINT32 bdreg:REGISTER:VEC:SINT32{BCAST} adreg:REGISTER:VEC:SINT32{ILANE} adreg_lane:IMMEDIATE:-:- @far
op move [MASK] amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64{BCAST} adreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:-
op move [MASK] amreg:REGISTER:MASK:SINT64 bdreg:REGISTER:VEC:SINT64{BCAST} adreg:REGISTER:VEC:SINT64{ILANE} adreg_lane:IMMEDIATE:-:- @far
op move [MASK] amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8{BCAST} adreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:-
op move [MASK] amreg:REGISTER:MASK:SINT8 bdreg:REGISTER:VEC:SINT8{BCAST} adreg:REGISTER:VEC:SINT8{ILANE} adreg_lane:IMMEDIATE:-:- @far
op move [MASK] amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16{BCAST} adreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:-
op move [MASK] amreg:REGISTER:MASK:UINT16 bdreg:REGISTER:VEC:UINT16{BCAST} adreg:REGISTER:VEC:UINT16{ILANE} adreg_lane:IMMEDIATE:-:- @far
op move [MASK] amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32{BCAST} adreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:-
op move [MASK] amreg:REGISTER:MASK:UINT32 bdreg:REGISTER:VEC:UINT32{BCAST} adreg:REGISTER:VEC:UINT32{ILANE} adreg_lane:IMMEDIATE:-:- @far
op move [MASK] amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64{BCAST} adreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:-
op move [MASK] amreg:REGISTER:MASK:UINT64 bdreg:REGISTER:VEC:UINT64{BCAST} adreg:REGISTER:VEC:UINT64{ILANE} adreg_lane:IMMEDIATE:-:- @far
op move [MASK] amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8{BCAST} adreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:-
op move [MASK] amreg:REGISTER:MASK:UINT8 bdreg:REGISTER:VEC:UINT8{BCAST} adreg:REGISTER:VEC:UINT8{ILANE} adreg_lane:IMMEDIATE:-:- @far
op move [] adreg:REGISTER:GP:SINT16 bdreg:REGISTER:VEC:SINT16{FILLOTHERS,ILANESHIFT} bdreg_irot:IMMEDIATE:-:-
op move [] adreg:REGISTER:GP:SINT32 bdreg:REGISTER:VEC:SINT32{FILLOTHERS,ILANESHIFT} bdreg_irot:IMMEDIATE:-:-
op move [] adreg:REGISTER:GP:SINT8 bdreg:REGISTER:VEC:SINT8{FILLOTHERS,ILANESHIFT} bdreg_irot:IMMEDIATE:-:-
op move [] adreg:REGISTER:GP:UINT16 bdreg:REGISTER:VEC:UINT16{FILLOTHERS,ILANESHIFT} bdreg_irot:IMMEDIATE:-:-
op move [] adreg:REGISTER:GP:UINT32 bdreg:REGISTER:VEC:UINT32{FILLOTHERS,ILANESHIFT} bdreg_irot:IMMEDIATE:-:-
op move [] adreg:REGISTER:GP:UINT8 bdreg:REGISTER:VEC:UINT8{FILLOTHERS,ILANESHIFT} bdreg_irot:IMMEDIATE:-:-
op mul [] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:16}
op mul [] adreg:REGISTER:VEC:SINT8 bdreg:REGISTER:VEC:SINT8{BLOCKLANE} cdreg:REGISTER:VEC:SINT8 bdreg_lane:IMMEDIATE:-:- {bdreg_blocksize:16} @far
op set [PARAM,VLEN] param:NAME:-:-
op store [PARAM] adreg:REGISTER:FP:DOUBLE param:NAME:-:-
op store [PARAM] adreg:REGISTER:FP:FP8E4M3 param:NAME:-:-
op store [PARAM] adreg:REGISTER:FP:FP8E5M2 param:NAME:-:-
op store [PARAM] adreg:REGISTER:FP:HALF param:NAME:-:-
op store [PARAM] adreg:REGISTER:FP:SINGLE param:NAME:-:-
op store [PARAM] adreg:REGISTER:GP:SINT16 param:NAME:-:-
op store [PARAM] adreg:REGISTER:GP:SINT32 param:NAME:-:-
op store [PARAM] adreg:REGISTER:GP:SINT64 param:NAME:-:-
op store [PARAM] adreg:REGISTER:GP:SINT8 param:NAME:-:-
op store [PARAM] adreg:REGISTER:GP:UINT16 param:NAME:-:-
op store [PARAM] adreg:REGISTER:GP:UINT32 param:NAME:-:-
op store [PARAM] adreg:REGISTER:GP:UINT64 param:NAME:-:-
op store [PARAM] adreg:REGISTER:GP:UINT8 param:NAME:-:-
op store [POSTINC] adreg:REGISTER:FP:DOUBLE agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op store [POSTINC] adreg:REGISTER:FP:FP8E4M3 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op store [POSTINC] adreg:REGISTER:FP:FP8E5M2 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op store [POSTINC] adreg:REGISTER:FP:HALF agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op store [POSTINC] adreg:REGISTER:FP:SINGLE agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op store [POSTINC] adreg:REGISTER:GP:SINT16 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op store [POSTINC] adreg:REGISTER:GP:SINT32 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op store [POSTINC] adreg:REGISTER:GP:SINT64 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op store [POSTINC] adreg:REGISTER:GP:SINT8 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op store [POSTINC] adreg:REGISTER:GP:UINT16 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op store [POSTINC] adreg:REGISTER:GP:UINT32 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op store [POSTINC] adreg:REGISTER:GP:UINT64 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
op store [POSTINC] adreg:REGISTER:GP:UINT8 agreg:REGISTER:GP:UINT64 increg:REGISTER:GP:UINT64
