Marisol Quintero
Senior ASIC Verification Engineer
marisol.quintero@example.com  +44 7700 900614  Valencia, Spain

PROFILE
Senior ASIC Verification Engineer with more than 12 years of experience verifying
complex SoC designs across networking, automotive and storage domains. Well-versed
in SystemVerilog/UVM constrained-random verification, formal property checking and
coverage closure, and comfortable across the full verification flow from planning
through to sign-off.

SKILL HIGHLIGHTS
- Building and maintaining reusable UVM verification environments at IP, subsystem and SoC level.
- Coverage-driven verification: defining, tracking and closing functional and code coverage.
- Assertion-based verification using SystemVerilog Assertions.
- Formal property checking of control logic and standard-bus interfaces.
- Mentoring junior engineers and owning regression triage and sign-off.

TOOLS
Xcelium, QuestaSim, VCS, JasperGold, VManager, Verdi, Git, Jenkins

EMPLOYMENT HISTORY
01/2021 - Present, Senior Verification Engineer, Larksong Semiconductors
Domain: Networking Switch ASICs - Packet Processing
- Led UVM verification of a packet-processing subsystem for a high-speed networking ASIC.
- Defined the coverage plan and drove functional and code coverage to closure.
- Performed formal property checking of the arbitration and scheduling logic using JasperGold.

06/2016 - 12/2020, Verification Engineer, Cindervale Microsystems
Domain: Automotive Safety Controllers
Project: ASIL-D Safety Island
- Developed UVM testbenches, sequences and assertions for an automotive safety island.
- Carried out fault-injection campaigns to demonstrate ISO 26262 ASIL-D diagnostic coverage.

03/2013 - 05/2016, Verification Engineer, Halden Logic
Domain: Storage Controllers - NVMe
- Built block-level UVM environments for an NVMe controller datapath.
- Verified AXI and APB interfaces and supported regression on the SoC testbench.

EDUCATION
MSc in Microelectronics Engineering, Mediterranean Institute of Technology (2007 - 2009)
BEng in Electronic Engineering, University of Valencia (2003 - 2007)

CERTIFICATIONS
- Cadence Certified UVM Specialist

LANGUAGES
English (fluent), Spanish (native), Catalan (native)
