PyICe.spi_interface

SPI Interface Hardware Drivers

Created on Feb 23, 2015 Heavily modified August 2016 to be more generic.

@author: JKapasi @author: DSimmons

The SPI interface is composed of two separate classes:

  1. shift_register

    abstracts individual bit-fields into integer representing contents of full-length shift register

  2. spiInterface: Defines the hardware interface including baudrate, mode (CPOL/CPHA), CS operation.

    Specific hardware implementations should overload this class and implement _shift_data method.

Functions

Classes

shift_register([bit_field_name, ...]) helper class to assemble multiple bit-fields together into a single larger integer and to disassemble received data into individual bit-fields.
spiInterface(CPOL, CPHA, ss_ctrl, word_size)
spi_bbone(CPOL, CPHA, ss_ctrl, word_size) The Beaglebone black will use the Adafruit BBIO, thus we can initialize this package for all purposes This instrument probably got a broken when the parent class interface was modified to support multiple interface hardware boards and more general SPI communication.
spi_bitbang(SCK_channel[, MOSI_channel, ...])
spi_buspirate(interface_raw_serial[, CPOL, ...])
spi_cfgpro(visa_interface, CPOL, CPHA[, ...])
spi_dc590(interface_stream[, ss_ctrl])
spi_dummy([delay, word_size])

Exceptions

SPIMasterError
class PyICe.spi_interface.shift_register(bit_field_name=None, bit_field_bit_count=None)[source]

Bases: object

helper class to assemble multiple bit-fields together into a single larger integer and to disassemble received data into individual bit-fields.

add_bit_field(bit_field_name, bit_field_bit_count)[source]

build SPI shift register data protocol sequentially MSB->LSB with repeated calls to add_bit_field

display()[source]

print ascii register structure graphic

keys()[source]

return list of bit-field names registered with instance

pack(bit_field_data_dict)[source]

pack bit fields into single larger integer. also return accumulated clk_count. Suitable for passing directly to spiInterface.transceive(*shift_register.pack(bit_field_data_dict)) bit_field_data_dict should contain one key-value pair for each defined bit_field

unpack(data)[source]

unpack single integer representing full-width shift register data into individual bit field values according to instance-defined boundaries. return dictionary with key-value pairs for each defined bit_field_name and bit_field data.

class PyICe.spi_interface.spi_bbone(CPOL, CPHA, ss_ctrl, word_size)[source]

Bases: PyICe.spi_interface.spiInterface

The Beaglebone black will use the Adafruit BBIO, thus we can initialize this package for all purposes This instrument probably got a broken when the parent class interface was modified to support multiple interface hardware boards and more general SPI communication. Needs testing/repair.

pack(data_list, word_size=8)

pack byte,word aligned pieces (list) from communication hardware into single integer comprising full shift register width. integer can then be broken up by shift_register object into bit field aligned pieces.

set_ss_ctrl(ss_ctrl_function)

change ss_ctrl function after instantiation. function should take single boolean argument. If true, assert slave select. If false, deassert slave select. There will typically be a logic inversion inside ss_ctrl to achieve active low _cs.

set_strict_alignment(strict)

If true, enforce that SPI master and slave hardware lengths match. If false, enable automatic padding to correct alignment.

transceive(data, clk_count)

send data word out MOSI with clk_count clocks. return word of same size read simultaneously on MISO. Frame entire transaction with slave select.

unpack(data, bit_count, word_size=8)

break full shift register width integer into byte,word aligned pieces. Return list of pieces MS first, LS last. helper to send byte-aligned pieces to hardware even if bit fields span bytes (or 1-bit, 16-bit 32-bit, etc words for other hardware)