Metadata-Version: 2.4
Name: peakrdl-viz
Version: 1.0.0
Summary: Generate visualization code for MakerChip VIZ framework.
Author: Ali Mohsen
License: LGPLv3
Project-URL: Source, https://github.com/balbal1/PeakRDL_Visualization_Plugin
Project-URL: Tracker, https://github.com/balbal1/PeakRDL_Visualization_Plugin/issues
Project-URL: Changelog, https://github.com/balbal1/PeakRDL_Visualization_Plugin/releases
Keywords: SystemRDL,PeakRDL,CSR,compiler,tool,registers,generator,MakerChip,visualization,VIZ,Verilog,SystemVerilog,TL-Verilog,FPGA,ASIC
Classifier: Development Status :: 5 - Production/Stable
Classifier: Programming Language :: Python
Classifier: Programming Language :: Python :: 3
Classifier: Programming Language :: Python :: 3 :: Only
Classifier: Intended Audience :: Developers
Classifier: License :: OSI Approved :: GNU Lesser General Public License v3 (LGPLv3)
Classifier: Operating System :: OS Independent
Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
Requires-Python: >=3.9
Description-Content-Type: text/markdown
Requires-Dist: systemrdl-compiler<2,>=1.29.0
Requires-Dist: Jinja2>=3.1.2

# PeakRDL_Visualization_Plugin

This is a draft repo for experimenting with Makerchip VIZ framework and PeakRDL

## How to use

for a quick test for the plugin:

```peakrdl viz-exporter --peakrdl-cfg my_config.toml -o output_files test_files/long_test.rdl --sv```

import the output .tlv file (inside output_files) to makerchip and test

### Output of the test file

![image](https://github.com/user-attachments/assets/2b8dd253-8fd0-4839-90af-6e9ffbd49b92)
