LICENSE
README.md
pyproject.toml
setup.py
benchmarks/benchmark.py
examples/axi/axi_lite_example.py
examples/axi/axi_stream_example.py
examples/axi/axi_crossbar_4x4/bench/axi_crossbar_4x4_bench.py
examples/axi/axi_crossbar_4x4/debug/debug_axi.py
examples/axi/axi_crossbar_4x4/debug/debug_width.py
examples/basics/alu.py
examples/basics/counter.py
examples/basics/fsm.py
examples/basics/shift_register.py
examples/basics/testbench.py
examples/composability/design_explorer.py
examples/composability/pipeline_generator.py
examples/composability/register_bank.py
examples/darkriscv/diag_compare.py
examples/darkriscv/profile_compiled.py
examples/darkriscv/run_fast.py
examples/darkriscv/run_sim.py
examples/debug/gen_partselect/test_gen_partselect.py
examples/debug/gen_port_partsel/test_gen_port_partsel.py
examples/debug/gen_unpacked_arr/test_gen_unpacked_arr.py
examples/femtorv/cosim_validate.py
examples/femtorv/gen_firmware.py
examples/femtorv/run_fast.py
examples/femtorv/run_sim.py
examples/ibex/gen_firmware.py
examples/ibex/model_test.py
examples/ibex/parse_test.py
examples/ibex/run_sim.py
examples/ibex/run_vcd.py
examples/ibex/vcd_compare_verilator.py
examples/library/cdc_example.py
examples/library/codec_example.py
examples/library/dsp_example.py
examples/library/fifo_example.py
examples/library/xilinx_example.py
examples/multi_iface_project/tb/multi_iface_tb.py
examples/pause_demo/pause_demo.py
examples/picorv32/cosim_validate.py
examples/picorv32/gen_firmware.py
examples/picorv32/run_fast.py
examples/picorv32/run_sim.py
examples/pulp/axi/axi_cdc/run_sim.py
examples/pulp/axi/axi_cdc/bench/axi_cdc_bench.py
examples/pulp/axi/axi_fifo/run_sim.py
examples/pulp/axi/axi_fifo/bench/axi_fifo_bench.py
examples/pulp/axi/axi_lite_dw_converter/run_sim.py
examples/pulp/axi/axi_lite_dw_converter/bench/axi_lite_dw_bench.py
examples/pulp/axi/axi_lite_mailbox/run_sim.py
examples/pulp/axi/axi_lite_mailbox/bench/axi_lite_mailbox_bench.py
examples/pulp/axi/axi_lite_regs/run_sim.py
examples/pulp/axi/axi_lite_regs/bench/axi_lite_regs_bench.py
examples/pulp/axi/axi_lite_to_axi/run_sim.py
examples/pulp/axi/axi_lite_to_axi/bench/axi_lite_to_axi_bench.py
examples/pulp/axi/axi_lite_xbar/run_sim.py
examples/pulp/axi/axi_lite_xbar/bench/axi_lite_xbar_bench.py
examples/pulp/axi/axi_mem_flat/bench/axi_mem_flat_bench.py
examples/pulp/axi/axi_to_axi_lite/run_sim.py
examples/pulp/axi/axi_to_axi_lite/bench/axi_to_axi_lite_bench.py
examples/pulp/axi/axi_xbar/run_sim.py
examples/pulp/axi/axi_xbar/bench/axi_xbar_bench.py
examples/pulp/common_cells/binary_to_gray/run_sim.py
examples/pulp/common_cells/cc_onehot/run_sim.py
examples/pulp/common_cells/cdc_2phase/run_sim.py
examples/pulp/common_cells/cdc_2phase_clearable/run_sim.py
examples/pulp/common_cells/cdc_4phase/run_sim.py
examples/pulp/common_cells/cdc_fifo/run_sim.py
examples/pulp/common_cells/cdc_fifo_gray/run_sim.py
examples/pulp/common_cells/cdc_reset_ctrlr/run_sim.py
examples/pulp/common_cells/counter/run_sim.py
examples/pulp/common_cells/credit_counter/run_sim.py
examples/pulp/common_cells/delta_counter/run_sim.py
examples/pulp/common_cells/edge_detect/run_sim.py
examples/pulp/common_cells/edge_propagator_ack/run_sim.py
examples/pulp/common_cells/edge_propagator_rx/run_sim.py
examples/pulp/common_cells/edge_propagator_tx/run_sim.py
examples/pulp/common_cells/exp_backoff/run_sim.py
examples/pulp/common_cells/fall_through_register/run_sim.py
examples/pulp/common_cells/fifo_v3/run_sim.py
examples/pulp/common_cells/gray_to_binary/run_sim.py
examples/pulp/common_cells/heaviside/run_sim.py
examples/pulp/common_cells/isochronous_4phase_handshake/run_sim.py
examples/pulp/common_cells/isochronous_spill_register/run_sim.py
examples/pulp/common_cells/lfsr_8bit/run_sim.py
examples/pulp/common_cells/lossy_valid_to_stream/run_sim.py
examples/pulp/common_cells/lzc/run_sim.py
examples/pulp/common_cells/max_counter/run_sim.py
examples/pulp/common_cells/onehot_to_bin/run_sim.py
examples/pulp/common_cells/passthrough_stream_fifo/run_sim.py
examples/pulp/common_cells/plru_tree/run_sim.py
examples/pulp/common_cells/popcount/run_sim.py
examples/pulp/common_cells/read/run_sim.py
examples/pulp/common_cells/ring_buffer/run_sim.py
examples/pulp/common_cells/rr_arb_tree/run_sim.py
examples/pulp/common_cells/rstgen/run_sim.py
examples/pulp/common_cells/rstgen_bypass/run_sim.py
examples/pulp/common_cells/serial_deglitch/run_sim.py
examples/pulp/common_cells/shift_reg/run_sim.py
examples/pulp/common_cells/spill_register/run_sim.py
examples/pulp/common_cells/spill_register/bench/spill_register_bench.py
examples/pulp/common_cells/spill_register_flushable/run_sim.py
examples/pulp/common_cells/stream_arbiter/run_sim.py
examples/pulp/common_cells/stream_arbiter_flushable/run_sim.py
examples/pulp/common_cells/stream_delay/run_sim.py
examples/pulp/common_cells/stream_demux/run_sim.py
examples/pulp/common_cells/stream_fifo/run_sim.py
examples/pulp/common_cells/stream_fifo/bench/stream_fifo_bench.py
examples/pulp/common_cells/stream_fifo_optimal_wrap/run_sim.py
examples/pulp/common_cells/stream_filter/run_sim.py
examples/pulp/common_cells/stream_fork/run_sim.py
examples/pulp/common_cells/stream_fork_dynamic/run_sim.py
examples/pulp/common_cells/stream_join/run_sim.py
examples/pulp/common_cells/stream_mux/run_sim.py
examples/pulp/common_cells/stream_omega_net/run_sim.py
examples/pulp/common_cells/stream_register/run_sim.py
examples/pulp/common_cells/stream_register/bench/stream_register_bench.py
examples/pulp/common_cells/stream_throttle/run_sim.py
examples/pulp/common_cells/stream_to_mem/run_sim.py
examples/pulp/common_cells/stream_xbar/run_sim.py
examples/pulp/common_cells/stream_xbar_typed/run_sim.py
examples/pulp/common_cells/sub_per_hash/oracle_vectors.py
examples/pulp/common_cells/sub_per_hash/run_sim.py
examples/pulp/common_cells/sync/run_sim.py
examples/pulp/common_cells/sync_wedge/run_sim.py
examples/pulp/common_cells/trip_counter/run_sim.py
examples/pulp/common_cells/unread/run_sim.py
examples/python_testbench/axi_stream_loopback.py
examples/python_testbench/multi_domain_axis.py
examples/serv/cosim_validate.py
examples/serv/gen_firmware.py
examples/serv/run_fast.py
examples/serv/run_sim.py
examples/taxi/tb/test_axil_ram.py
examples/taxi/tb/test_axis_adapter.py
examples/taxi/tb/test_axis_arb_mux.py
examples/taxi/tb/test_axis_async_fifo.py
examples/taxi/tb/test_axis_broadcast.py
examples/taxi/tb/test_axis_register.py
src/veriforge/__init__.py
src/veriforge/__main__.py
src/veriforge/_version.py
src/veriforge/preprocessor.py
src/veriforge/project.py
src/veriforge/scaffold.py
src/veriforge/verilog_parser.py
src/veriforge/analysis/__init__.py
src/veriforge/analysis/clock_reset.py
src/veriforge/analysis/const_fold.py
src/veriforge/analysis/lint.py
src/veriforge/analysis/resolver.py
src/veriforge/analysis/width_inference.py
src/veriforge/codegen/__init__.py
src/veriforge/codegen/format_style.py
src/veriforge/codegen/verilog_emitter.py
src/veriforge/codegen/verilog_formatter.py
src/veriforge/convert/__init__.py
src/veriforge/convert/to_dsl.py
src/veriforge/dsl/__init__.py
src/veriforge/dsl/builder.py
src/veriforge/dsl/interface.py
src/veriforge/dsl/ram.py
src/veriforge/dsl/testbench.py
src/veriforge/dsl/testbench_deps.py
src/veriforge/dsl/lib/__init__.py
src/veriforge/dsl/lib/axi.py
src/veriforge/dsl/lib/axi_stream.py
src/veriforge/dsl/lib/cdc.py
src/veriforge/dsl/lib/codec.py
src/veriforge/dsl/lib/dsp.py
src/veriforge/dsl/lib/fifo.py
src/veriforge/dsl/lib/xilinx.py
src/veriforge/lark_file/__init__.py
src/veriforge/lark_file/gen_tree.py
src/veriforge/lark_file/parse_metadata.py
src/veriforge/lark_file/verilog.lark
src/veriforge/model/__init__.py
src/veriforge/model/assignments.py
src/veriforge/model/base.py
src/veriforge/model/behavioral.py
src/veriforge/model/design.py
src/veriforge/model/expressions.py
src/veriforge/model/functions.py
src/veriforge/model/generate.py
src/veriforge/model/instances.py
src/veriforge/model/interface.py
src/veriforge/model/nets.py
src/veriforge/model/package.py
src/veriforge/model/parameters.py
src/veriforge/model/ports.py
src/veriforge/model/specify.py
src/veriforge/model/statements.py
src/veriforge/model/sv_types.py
src/veriforge/model/variables.py
src/veriforge/refactor/__init__.py
src/veriforge/refactor/_boundary_models.py
src/veriforge/refactor/_boundary_pull_push.py
src/veriforge/refactor/_boundary_selection.py
src/veriforge/refactor/_boundary_validation.py
src/veriforge/refactor/_extract_classify.py
src/veriforge/refactor/_extract_models.py
src/veriforge/refactor/_pull_up_engine.py
src/veriforge/refactor/_push_down_engine.py
src/veriforge/refactor/_refactor_utils.py
src/veriforge/refactor/diagnostics.py
src/veriforge/refactor/hierarchy_boundary.py
src/veriforge/refactor/hierarchy_collapse.py
src/veriforge/refactor/hierarchy_extract.py
src/veriforge/refactor/hierarchy_graph.py
src/veriforge/refactor/visualization.py
src/veriforge/sim/__init__.py
src/veriforge/sim/cosim.py
src/veriforge/sim/elaborate.py
src/veriforge/sim/evaluator.py
src/veriforge/sim/event_queue.py
src/veriforge/sim/example_runner.py
src/veriforge/sim/executor.py
src/veriforge/sim/scheduler.py
src/veriforge/sim/step_harness.py
src/veriforge/sim/testbench.py
src/veriforge/sim/trace.py
src/veriforge/sim/value.py
src/veriforge/sim/vcd.py
src/veriforge/sim/vcd_compare.py
src/veriforge/sim/bench/__init__.py
src/veriforge/sim/bench/interfaces.py
src/veriforge/sim/bench/lowering.py
src/veriforge/sim/bench/plan.py
src/veriforge/sim/bench/planner.py
src/veriforge/sim/bench/runtime.py
src/veriforge/sim/compiled/__init__.py
src/veriforge/sim/compiled/_codegen_utils.py
src/veriforge/sim/compiled/_expr_emitter.py
src/veriforge/sim/compiled/_gen_narrow_accessors.py
src/veriforge/sim/compiled/_gen_narrow_assign.py
src/veriforge/sim/compiled/_gen_narrow_stage.py
src/veriforge/sim/compiled/_gen_narrow_tail.py
src/veriforge/sim/compiled/_gen_sections.py
src/veriforge/sim/compiled/_gen_wide_section.py
src/veriforge/sim/compiled/_process_compiler.py
src/veriforge/sim/compiled/_stmt_emitters.py
src/veriforge/sim/compiled/_wide_emitter.py
src/veriforge/sim/compiled/codegen.py
src/veriforge/sim/compiled/compiled_scheduler.py
src/veriforge/sim/compiled/compiler.py
src/veriforge/sim/compiled/templates/narrow_accessors.pxi
src/veriforge/sim/compiled/templates/narrow_assign.pxi
src/veriforge/sim/compiled/templates/narrow_stage.pxi
src/veriforge/sim/compiled/templates/narrow_tail.pxi
src/veriforge/sim/endpoints/__init__.py
src/veriforge/sim/endpoints/_generator.py
src/veriforge/sim/endpoints/axi4_master.py
src/veriforge/sim/endpoints/axi4_responder.py
src/veriforge/sim/endpoints/axi_lite_common.py
src/veriforge/sim/endpoints/axi_lite_master.py
src/veriforge/sim/endpoints/axi_lite_request_driver.py
src/veriforge/sim/endpoints/axi_lite_responder.py
src/veriforge/sim/endpoints/axi_lite_response_driver.py
src/veriforge/sim/endpoints/axis_sink.py
src/veriforge/sim/endpoints/axis_source.py
src/veriforge/sim/endpoints/detect.py
src/veriforge/sim/endpoints/frame.py
src/veriforge/sim/endpoints/helpers.py
src/veriforge/sim/endpoints/membus_master.py
src/veriforge/sim/endpoints/membus_responder.py
src/veriforge/sim/endpoints/pause.py
src/veriforge/sim/endpoints/stream_sink.py
src/veriforge/sim/endpoints/stream_source.py
src/veriforge/sim/vm/__init__.py
src/veriforge/sim/vm/compiler.py
src/veriforge/sim/vm/interpreter.py
src/veriforge/sim/vm/opcodes.py
src/veriforge/sim/vm/vm_scheduler.py
src/veriforge/transforms/__init__.py
src/veriforge/transforms/_assignments.py
src/veriforge/transforms/_declarations.py
src/veriforge/transforms/_design_builder.py
src/veriforge/transforms/_expressions.py
src/veriforge/transforms/_functions_tasks.py
src/veriforge/transforms/_generate.py
src/veriforge/transforms/_instances.py
src/veriforge/transforms/_statements.py
src/veriforge/transforms/_tree_utils.py
src/veriforge/transforms/comment_extractor.py
src/veriforge/transforms/tree_to_model.py
tests/__init__.py
tests/conftest.py
tests/test_partial_assign.py
tests/test_analysis/test_block_locals.py
tests/test_analysis/test_clock_reset.py
tests/test_analysis/test_clock_reset_hier.py
tests/test_analysis/test_const_fold.py
tests/test_analysis/test_generate_improvements.py
tests/test_analysis/test_interface.py
tests/test_analysis/test_lint.py
tests/test_analysis/test_package.py
tests/test_analysis/test_struct_union.py
tests/test_analysis/test_typedef_enum.py
tests/test_analysis/test_width_inference.py
tests/test_dsl/__init__.py
tests/test_dsl/test_axi4_mem_example.py
tests/test_dsl/test_axi_cdc_pulp_example.py
tests/test_dsl/test_axi_fifo_pulp_example.py
tests/test_dsl/test_axi_lite_dw_pulp_example.py
tests/test_dsl/test_axi_lite_mailbox_pulp_example.py
tests/test_dsl/test_axi_lite_regs_example.py
tests/test_dsl/test_axi_lite_to_axi_pulp_example.py
tests/test_dsl/test_axi_lite_xbar_pulp_example.py
tests/test_dsl/test_axi_to_axi_lite_pulp_example.py
tests/test_dsl/test_axi_xbar_pulp_example.py
tests/test_dsl/test_builder.py
tests/test_dsl/test_builder_errors_m24.py
tests/test_dsl/test_builder_errors_m9.py
tests/test_dsl/test_convert_to_dsl.py
tests/test_dsl/test_dsl_boundary.py
tests/test_dsl/test_examples.py
tests/test_dsl/test_lib_axi.py
tests/test_dsl/test_lib_cdc.py
tests/test_dsl/test_lib_codec.py
tests/test_dsl/test_lib_dsp.py
tests/test_dsl/test_lib_fifo.py
tests/test_dsl/test_lib_xilinx.py
tests/test_dsl/test_ram.py
tests/test_dsl/test_roundtrip_dsl.py
tests/test_dsl/test_sv_dsl.py
tests/test_dsl/test_sv_interface_emit.py
tests/test_dsl/test_taxi_axil_ram.py
tests/test_dsl/test_taxi_axis_adapter.py
tests/test_dsl/test_taxi_axis_arb_mux.py
tests/test_dsl/test_taxi_axis_async_fifo.py
tests/test_dsl/test_taxi_axis_async_fifo_dualclk.py
tests/test_dsl/test_taxi_axis_broadcast.py
tests/test_dsl/test_taxi_axis_register.py
tests/test_dsl/test_testbench.py
tests/test_dsl/test_testbench_bench_style.py
tests/test_dsl/test_testbench_deps.py
tests/test_dsl/test_testbench_enhanced.py
tests/test_formatter/__init__.py
tests/test_formatter/test_formatter.py
tests/test_lsp/__init__.py
tests/test_lsp/test_lark_fallback.py
tests/test_lsp/test_navigation.py
tests/test_lsp/test_symbols.py
tests/test_lsp/test_trace.py
tests/test_model/__init__.py
tests/test_model/conftest.py
tests/test_model/test_analysis.py
tests/test_model/test_behavioral.py
tests/test_model/test_comment_roundtrip.py
tests/test_model/test_comments.py
tests/test_model/test_corpus.py
tests/test_model/test_functions_generate.py
tests/test_model/test_instances.py
tests/test_model/test_module.py
tests/test_model/test_roundtrip.py
tests/test_model/test_specify.py
tests/test_model/test_tree_to_model_characterization.py
tests/test_model/test_typed_sv_regressions.py
tests/test_preprocessor/__init__.py
tests/test_preprocessor/test_preprocessor.py
tests/test_project/__init__.py
tests/test_project/test_darkriscv.py
tests/test_project/test_project.py
tests/test_refactor/test_hierarchy_graph.py
tests/test_sim/__init__.py
tests/test_sim/test_axi_lite_master.py
tests/test_sim/test_axis_endpoints.py
tests/test_sim/test_axis_frame.py
tests/test_sim/test_bench_native.py
tests/test_sim/test_bench_plan.py
tests/test_sim/test_bench_planner.py
tests/test_sim/test_bench_runtime.py
tests/test_sim/test_combinational_coordinator.py
tests/test_sim/test_compiled.py
tests/test_sim/test_compiled_batch_run_propagation.py
tests/test_sim/test_compiled_latent_risks.py
tests/test_sim/test_coordinator_strict.py
tests/test_sim/test_darkriscv_constructs.py
tests/test_sim/test_evaluator.py
tests/test_sim/test_executor.py
tests/test_sim/test_function_task.py
tests/test_sim/test_generate.py
tests/test_sim/test_generator_endpoint.py
tests/test_sim/test_hierarchy.py
tests/test_sim/test_ibex_examples.py
tests/test_sim/test_interface_detection.py
tests/test_sim/test_membus_endpoints.py
tests/test_sim/test_memory.py
tests/test_sim/test_multi_domain_runner.py
tests/test_sim/test_param_width.py
tests/test_sim/test_planner_naming_fallback.py
tests/test_sim/test_precedence_and_fixes.py
tests/test_sim/test_pulp_axi_examples.py
tests/test_sim/test_pulp_common_cells_examples.py
tests/test_sim/test_pulp_ready_valid_examples.py
tests/test_sim/test_scheduler.py
tests/test_sim/test_sim_sv.py
tests/test_sim/test_stream_protocol.py
tests/test_sim/test_structural_patterns.py
tests/test_sim/test_testbench.py
tests/test_sim/test_value.py
tests/test_sim/test_value_widths.py
tests/test_sim/test_vcd.py
tests/test_sim/test_vm.py
tests/test_sim/test_wide_signal_catchall.py
tests/test_validation/__init__.py
tests/test_validation/test_iverilog_validation.py
tests/test_validation/test_vm_vs_reference.py
tests/test_verilog_parser/test_all.py
tests/test_verilog_parser/test_rule_examples.py
tests/test_verilog_parser/test_section_a1.py
tests/test_verilog_parser/test_section_a2.py
tests/test_verilog_parser/test_section_a6.py
tests/test_verilog_parser/test_section_a8.py
tests/test_verilog_parser/test_sv_features.py
tools/check_overview.py
tools/validate_compiled_pytest.py
veriforge.egg-info/PKG-INFO
veriforge.egg-info/SOURCES.txt
veriforge.egg-info/dependency_links.txt
veriforge.egg-info/entry_points.txt
veriforge.egg-info/requires.txt
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veriforge_lsp/__init__.py
veriforge_lsp/__main__.py
veriforge_lsp/index.py
veriforge_lsp/protocol.py
veriforge_lsp/server.py
veriforge_lsp/workspace.py
veriforge_lsp/handlers/__init__.py
veriforge_lsp/handlers/extended.py
veriforge_lsp/handlers/navigation.py
veriforge_lsp/handlers/symbols.py
veriforge_lsp/handlers/text_sync.py