
 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9 (git sha1 1979e0b1, i686-w64-mingw32.static-g++ 5.5.0 -Os)


-- Executing script file `sphere3hopf_synthesis_fixed.ys' --

1. Executing Verilog-2005 frontend: sphere3hopf_fsm_32bit_simple.v
Parsing Verilog input from `sphere3hopf_fsm_32bit_simple.v' to AST representation.
Generating RTLIL representation for module `\sphere3hopf_fsm_32bit_simple'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: vdcorput_fsm_32bit_simple.v
Parsing Verilog input from `vdcorput_fsm_32bit_simple.v' to AST representation.
Generating RTLIL representation for module `\vdcorput_fsm_32bit_simple'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: cordic_trig_16bit_simple_fixed.v
Parsing Verilog input from `cordic_trig_16bit_simple_fixed.v' to AST representation.
Generating RTLIL representation for module `\cordic_trig_16bit_simple_fixed'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: sqrt_approx_16_16.v
Parsing Verilog input from `sqrt_approx_16_16.v' to AST representation.
Generating RTLIL representation for module `\sqrt_approx_16_16'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: div_mod_3.v
Parsing Verilog input from `div_mod_3.v' to AST representation.
Generating RTLIL representation for module `\div_mod_3'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: div_mod_7.v
Parsing Verilog input from `div_mod_7.v' to AST representation.
Generating RTLIL representation for module `\div_mod_7'.
Successfully finished Verilog frontend.

7. Executing HIERARCHY pass (managing design hierarchy).

7.1. Analyzing design hierarchy..
Top module:  \sphere3hopf_fsm_32bit_simple
Used module:     \cordic_trig_16bit_simple_fixed
Used module:     \vdcorput_fsm_32bit_simple
Used module:         \div_mod_7
Used module:         \div_mod_3

7.2. Analyzing design hierarchy..
Top module:  \sphere3hopf_fsm_32bit_simple
Used module:     \cordic_trig_16bit_simple_fixed
Used module:     \vdcorput_fsm_32bit_simple
Used module:         \div_mod_7
Used module:         \div_mod_3
Removing unused module `\sqrt_approx_16_16'.
Removed 1 unused modules.

8. Executing PROC pass (convert processes to netlists).

8.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

8.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 10 switch rules as full_case in process $proc$cordic_trig_16bit_simple_fixed.v:108$145 in module cordic_trig_16bit_simple_fixed.
Marked 3 switch rules as full_case in process $proc$cordic_trig_16bit_simple_fixed.v:92$143 in module cordic_trig_16bit_simple_fixed.
Marked 1 switch rules as full_case in process $proc$cordic_trig_16bit_simple_fixed.v:83$141 in module cordic_trig_16bit_simple_fixed.
Marked 3 switch rules as full_case in process $proc$vdcorput_fsm_32bit_simple.v:94$114 in module vdcorput_fsm_32bit_simple.
Marked 3 switch rules as full_case in process $proc$vdcorput_fsm_32bit_simple.v:74$112 in module vdcorput_fsm_32bit_simple.
Marked 1 switch rules as full_case in process $proc$vdcorput_fsm_32bit_simple.v:65$110 in module vdcorput_fsm_32bit_simple.
Marked 7 switch rules as full_case in process $proc$sphere3hopf_fsm_32bit_simple.v:230$6 in module sphere3hopf_fsm_32bit_simple.
Marked 6 switch rules as full_case in process $proc$sphere3hopf_fsm_32bit_simple.v:200$5 in module sphere3hopf_fsm_32bit_simple.
Marked 1 switch rules as full_case in process $proc$sphere3hopf_fsm_32bit_simple.v:191$3 in module sphere3hopf_fsm_32bit_simple.
Removed a total of 0 dead cases.

8.3. Executing PROC_INIT pass (extract init attributes).

8.4. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \rst_n in `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:108$145'.
Found async reset \rst_n in `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:83$141'.
Found async reset \rst_n in `\vdcorput_fsm_32bit_simple.$proc$vdcorput_fsm_32bit_simple.v:94$114'.
Found async reset \rst_n in `\vdcorput_fsm_32bit_simple.$proc$vdcorput_fsm_32bit_simple.v:65$110'.
Found async reset \rst_n in `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
Found async reset \rst_n in `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:191$3'.

8.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
     1/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:79$140_DATA[15:0]$233
     2/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:79$140_ADDR[31:0]$232
     3/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:78$139_DATA[15:0]$231
     4/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:78$139_ADDR[31:0]$230
     5/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:77$138_DATA[15:0]$229
     6/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:77$138_ADDR[31:0]$228
     7/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:76$137_DATA[15:0]$227
     8/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:76$137_ADDR[31:0]$226
     9/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:75$136_DATA[15:0]$225
    10/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:75$136_ADDR[31:0]$224
    11/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:74$135_DATA[15:0]$223
    12/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:74$135_ADDR[31:0]$222
    13/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:73$134_DATA[15:0]$221
    14/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:73$134_ADDR[31:0]$220
    15/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:72$133_DATA[15:0]$219
    16/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:72$133_ADDR[31:0]$218
    17/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:71$132_DATA[15:0]$217
    18/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:71$132_ADDR[31:0]$216
    19/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:70$131_DATA[15:0]$215
    20/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:70$131_ADDR[31:0]$214
    21/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:69$130_DATA[15:0]$213
    22/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:69$130_ADDR[31:0]$212
    23/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:68$129_DATA[15:0]$211
    24/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:68$129_ADDR[31:0]$210
    25/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:67$128_DATA[15:0]$209
    26/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:67$128_ADDR[31:0]$208
    27/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:66$127_DATA[15:0]$207
    28/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:66$127_ADDR[31:0]$206
    29/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:65$126_DATA[15:0]$205
    30/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:65$126_ADDR[31:0]$204
    31/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:64$125_DATA[15:0]$203
    32/32: $0$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:64$125_ADDR[31:0]$202
Creating decoders for process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:108$145'.
     1/34: $5\sin_result[31:0]
     2/34: $5\cos_result[31:0]
     3/34: $4\sin_result[31:0]
     4/34: $4\cos_result[31:0]
     5/34: $3\sin_result[31:0]
     6/34: $3\cos_result[31:0]
     7/34: $6\reduced_angle[15:0]
     8/34: $5\reduced_angle[15:0]
     9/34: $4\reduced_angle[15:0]
    10/34: $3\reduced_angle[15:0]
    11/34: $2\reduced_angle[15:0]
    12/34: $2\sin_result[31:0]
    13/34: $2\cos_result[31:0]
    14/34: $2\y_scaled[31:0]
    15/34: $2\x_scaled[31:0]
    16/34: $1\sin_result[31:0]
    17/34: $1\cos_result[31:0]
    18/34: $1\y_scaled[31:0]
    19/34: $1\reduced_angle[15:0]
    20/34: $1\x_scaled[31:0]
    21/34: $0\sin_result[31:0]
    22/34: $0\cos_result[31:0]
    23/34: $0\y_scaled[31:0]
    24/34: $0\reduced_angle[15:0]
    25/34: $0\x_scaled[31:0]
    26/34: $0\angle_reg[15:0]
    27/34: $0\z[15:0]
    28/34: $0\y[16:0]
    29/34: $0\x[16:0]
    30/34: $0\iteration[3:0]
    31/34: $0\sine[31:0]
    32/34: $0\cosine[31:0]
    33/34: $0\ready[0:0]
    34/34: $0\done[0:0]
Creating decoders for process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:92$143'.
     1/4: $3\next_state[1:0]
     2/4: $2\next_state[1:0]
     3/4: $1\next_state[1:0]
     4/4: $0\next_state[1:0]
Creating decoders for process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:83$141'.
     1/1: $0\state[1:0]
Creating decoders for process `\vdcorput_fsm_32bit_simple.$proc$vdcorput_fsm_32bit_simple.v:94$114'.
     1/9: $0\quotient_reg[31:0]
     2/9: $0\remainder_reg[31:0]
     3/9: $0\base_reg[31:0]
     4/9: $0\power_reg[31:0]
     5/9: $0\acc_reg[31:0]
     6/9: $0\result[31:0]
     7/9: $0\k_reg[31:0]
     8/9: $0\ready[0:0]
     9/9: $0\done[0:0]
Creating decoders for process `\vdcorput_fsm_32bit_simple.$proc$vdcorput_fsm_32bit_simple.v:74$112'.
     1/4: $3\next_state[2:0]
     2/4: $2\next_state[2:0]
     3/4: $1\next_state[2:0]
     4/4: $0\next_state[2:0]
Creating decoders for process `\vdcorput_fsm_32bit_simple.$proc$vdcorput_fsm_32bit_simple.v:65$110'.
     1/1: $0\current_state[2:0]
Creating decoders for process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
     1/93: $4$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\y2[31:0]$96
     2/93: $4$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\x_div_y1[63:0]$97
     3/93: $4$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\y1[31:0]$89
     4/93: $4$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\x_div_y0[63:0]$90
     5/93: $4$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\y2[31:0]$81
     6/93: $4$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\x_div_y1[63:0]$82
     7/93: $4$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\y1[31:0]$74
     8/93: $4$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\x_div_y0[63:0]$75
     9/93: $3$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\sqrt_approx[31:0]$62
    10/93: $3$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\x_div_y1[63:0]$68
    11/93: $3$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\y2[31:0]$66
    12/93: $3$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\x_div_y0[63:0]$67
    13/93: $3$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\y1[31:0]$65
    14/93: $3$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\y0[31:0]$64
    15/93: $3$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\x[31:0]$63
    16/93: $3$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\sqrt_approx[31:0]$55
    17/93: $3$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\x_div_y1[63:0]$61
    18/93: $3$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\y2[31:0]$59
    19/93: $3$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\x_div_y0[63:0]$60
    20/93: $3$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\y1[31:0]$58
    21/93: $3$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\y0[31:0]$57
    22/93: $3$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\x[31:0]$56
    23/93: $3\one_minus_vdc[31:0]
    24/93: $3\vdc_sq[63:0]
    25/93: $2$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\x_div_y1[63:0]$49
    26/93: $2$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\x_div_y0[63:0]$48
    27/93: $2$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\y2[31:0]$47
    28/93: $2$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\y1[31:0]$46
    29/93: $2$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\y0[31:0]$45
    30/93: $2$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\x[31:0]$44
    31/93: $2$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\sqrt_approx[31:0]$43
    32/93: $2$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\x_div_y1[63:0]$42
    33/93: $2$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\x_div_y0[63:0]$41
    34/93: $2$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\y2[31:0]$40
    35/93: $2$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\y1[31:0]$39
    36/93: $2$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\y0[31:0]$38
    37/93: $2$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\x[31:0]$37
    38/93: $2$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\sqrt_approx[31:0]$36
    39/93: $2\one_minus_vdc[31:0]
    40/93: $2\vdc_sq[63:0]
    41/93: $1$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\x_div_y1[63:0]$35
    42/93: $1$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\x_div_y0[63:0]$34
    43/93: $1$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\y2[31:0]$33
    44/93: $1$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\y1[31:0]$32
    45/93: $1$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\y0[31:0]$31
    46/93: $1$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\x[31:0]$30
    47/93: $1$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\sqrt_approx[31:0]$29
    48/93: $1$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\x_div_y1[63:0]$28
    49/93: $1$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\x_div_y0[63:0]$27
    50/93: $1$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\y2[31:0]$26
    51/93: $1$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\y1[31:0]$25
    52/93: $1$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\y0[31:0]$24
    53/93: $1$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\x[31:0]$23
    54/93: $1$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\sqrt_approx[31:0]$22
    55/93: $1\one_minus_vdc[31:0]
    56/93: $1\vdc_sq[63:0]
    57/93: $0$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\x_div_y1[63:0]$20
    58/93: $0$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\x_div_y0[63:0]$19
    59/93: $0$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\y2[31:0]$18
    60/93: $0$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\y1[31:0]$17
    61/93: $0$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\y0[31:0]$16
    62/93: $0$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\x[31:0]$15
    63/93: $0$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\sqrt_approx[31:0]$14
    64/93: $0$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\x_div_y1[63:0]$13
    65/93: $0$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\x_div_y0[63:0]$12
    66/93: $0$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\y2[31:0]$11
    67/93: $0$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\y1[31:0]$10
    68/93: $0$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\y0[31:0]$9
    69/93: $0$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\x[31:0]$8
    70/93: $0$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\sqrt_approx[31:0]$7
    71/93: $0\one_minus_vdc[31:0]
    72/93: $0\vdc_sq[63:0]
    73/93: $0\trig_angle[31:0]
    74/93: $0\trig_start[0:0]
    75/93: $0\vdc2_start[0:0]
    76/93: $0\vdc1_start[0:0]
    77/93: $0\vdc0_start[0:0]
    78/93: $0\sin_phi_psi_reg[31:0]
    79/93: $0\cos_phi_psi_reg[31:0]
    80/93: $0\sin_psi_reg[31:0]
    81/93: $0\cos_psi_reg[31:0]
    82/93: $0\sin_eta_reg[31:0]
    83/93: $0\cos_eta_reg[31:0]
    84/93: $0\vdc_reg[31:0]
    85/93: $0\psi_reg[31:0]
    86/93: $0\phi_reg[31:0]
    87/93: $0\k_reg[31:0]
    88/93: $0\ready[0:0]
    89/93: $0\done[0:0]
    90/93: $0\result_w[31:0]
    91/93: $0\result_z[31:0]
    92/93: $0\result_y[31:0]
    93/93: $0\result_x[31:0]
Creating decoders for process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:200$5'.
     1/7: $6\next_state[4:0]
     2/7: $5\next_state[4:0]
     3/7: $4\next_state[4:0]
     4/7: $3\next_state[4:0]
     5/7: $2\next_state[4:0]
     6/7: $1\next_state[4:0]
     7/7: $0\next_state[4:0]
Creating decoders for process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:191$3'.
     1/1: $0\current_state[4:0]

8.6. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:64$125_ADDR' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:64$125_DATA' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:65$126_ADDR' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:65$126_DATA' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:66$127_ADDR' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:66$127_DATA' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:67$128_ADDR' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:67$128_DATA' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:68$129_ADDR' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:68$129_DATA' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:69$130_ADDR' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:69$130_DATA' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:70$131_ADDR' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:70$131_DATA' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:71$132_ADDR' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:71$132_DATA' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:72$133_ADDR' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:72$133_DATA' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:73$134_ADDR' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:73$134_DATA' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:74$135_ADDR' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:74$135_DATA' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:75$136_ADDR' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:75$136_DATA' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:76$137_ADDR' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:76$137_DATA' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:77$138_ADDR' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:77$138_DATA' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:78$139_ADDR' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:78$139_DATA' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:79$140_ADDR' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.$memwr$\atan_table$cordic_trig_16bit_simple_fixed.v:79$140_DATA' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
No latch inferred for signal `\cordic_trig_16bit_simple_fixed.\next_state' from process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:92$143'.
No latch inferred for signal `\vdcorput_fsm_32bit_simple.\next_state' from process `\vdcorput_fsm_32bit_simple.$proc$vdcorput_fsm_32bit_simple.v:74$112'.
No latch inferred for signal `\sphere3hopf_fsm_32bit_simple.\next_state' from process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:200$5'.

8.7. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\cordic_trig_16bit_simple_fixed.\done' using process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:108$145'.
  created $adff cell `$procdff$1155' with positive edge clock and negative level reset.
Creating register for signal `\cordic_trig_16bit_simple_fixed.\ready' using process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:108$145'.
  created $adff cell `$procdff$1156' with positive edge clock and negative level reset.
Creating register for signal `\cordic_trig_16bit_simple_fixed.\cosine' using process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:108$145'.
  created $adff cell `$procdff$1157' with positive edge clock and negative level reset.
Creating register for signal `\cordic_trig_16bit_simple_fixed.\sine' using process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:108$145'.
  created $adff cell `$procdff$1158' with positive edge clock and negative level reset.
Creating register for signal `\cordic_trig_16bit_simple_fixed.\x_scaled' using process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:108$145'.
  created $adff cell `$procdff$1159' with positive edge clock and negative level reset.
Creating register for signal `\cordic_trig_16bit_simple_fixed.\iteration' using process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:108$145'.
  created $adff cell `$procdff$1160' with positive edge clock and negative level reset.
Creating register for signal `\cordic_trig_16bit_simple_fixed.\x' using process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:108$145'.
  created $adff cell `$procdff$1161' with positive edge clock and negative level reset.
Creating register for signal `\cordic_trig_16bit_simple_fixed.\y' using process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:108$145'.
  created $adff cell `$procdff$1162' with positive edge clock and negative level reset.
Creating register for signal `\cordic_trig_16bit_simple_fixed.\z' using process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:108$145'.
  created $adff cell `$procdff$1163' with positive edge clock and negative level reset.
Creating register for signal `\cordic_trig_16bit_simple_fixed.\angle_reg' using process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:108$145'.
  created $dff cell `$procdff$1164' with positive edge clock.
Creating register for signal `\cordic_trig_16bit_simple_fixed.\reduced_angle' using process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:108$145'.
  created $adff cell `$procdff$1165' with positive edge clock and negative level reset.
Creating register for signal `\cordic_trig_16bit_simple_fixed.\y_scaled' using process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:108$145'.
  created $adff cell `$procdff$1166' with positive edge clock and negative level reset.
Creating register for signal `\cordic_trig_16bit_simple_fixed.\cos_result' using process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:108$145'.
  created $adff cell `$procdff$1167' with positive edge clock and negative level reset.
Creating register for signal `\cordic_trig_16bit_simple_fixed.\sin_result' using process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:108$145'.
  created $adff cell `$procdff$1168' with positive edge clock and negative level reset.
Creating register for signal `\cordic_trig_16bit_simple_fixed.\state' using process `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:83$141'.
  created $adff cell `$procdff$1169' with positive edge clock and negative level reset.
Creating register for signal `\vdcorput_fsm_32bit_simple.\done' using process `\vdcorput_fsm_32bit_simple.$proc$vdcorput_fsm_32bit_simple.v:94$114'.
  created $adff cell `$procdff$1170' with positive edge clock and negative level reset.
Creating register for signal `\vdcorput_fsm_32bit_simple.\ready' using process `\vdcorput_fsm_32bit_simple.$proc$vdcorput_fsm_32bit_simple.v:94$114'.
  created $adff cell `$procdff$1171' with positive edge clock and negative level reset.
Creating register for signal `\vdcorput_fsm_32bit_simple.\k_reg' using process `\vdcorput_fsm_32bit_simple.$proc$vdcorput_fsm_32bit_simple.v:94$114'.
  created $adff cell `$procdff$1172' with positive edge clock and negative level reset.
Creating register for signal `\vdcorput_fsm_32bit_simple.\result' using process `\vdcorput_fsm_32bit_simple.$proc$vdcorput_fsm_32bit_simple.v:94$114'.
  created $adff cell `$procdff$1173' with positive edge clock and negative level reset.
Creating register for signal `\vdcorput_fsm_32bit_simple.\acc_reg' using process `\vdcorput_fsm_32bit_simple.$proc$vdcorput_fsm_32bit_simple.v:94$114'.
  created $adff cell `$procdff$1174' with positive edge clock and negative level reset.
Creating register for signal `\vdcorput_fsm_32bit_simple.\power_reg' using process `\vdcorput_fsm_32bit_simple.$proc$vdcorput_fsm_32bit_simple.v:94$114'.
  created $adff cell `$procdff$1175' with positive edge clock and negative level reset.
Creating register for signal `\vdcorput_fsm_32bit_simple.\base_reg' using process `\vdcorput_fsm_32bit_simple.$proc$vdcorput_fsm_32bit_simple.v:94$114'.
  created $adff cell `$procdff$1176' with positive edge clock and negative level reset.
Creating register for signal `\vdcorput_fsm_32bit_simple.\remainder_reg' using process `\vdcorput_fsm_32bit_simple.$proc$vdcorput_fsm_32bit_simple.v:94$114'.
  created $adff cell `$procdff$1177' with positive edge clock and negative level reset.
Creating register for signal `\vdcorput_fsm_32bit_simple.\quotient_reg' using process `\vdcorput_fsm_32bit_simple.$proc$vdcorput_fsm_32bit_simple.v:94$114'.
  created $adff cell `$procdff$1178' with positive edge clock and negative level reset.
Creating register for signal `\vdcorput_fsm_32bit_simple.\current_state' using process `\vdcorput_fsm_32bit_simple.$proc$vdcorput_fsm_32bit_simple.v:65$110'.
  created $adff cell `$procdff$1179' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\result_x' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1180' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\result_y' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1181' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\result_z' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1182' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\result_w' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1183' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\done' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1184' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\ready' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1185' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\k_reg' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1186' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\phi_reg' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1187' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\psi_reg' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1188' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\vdc_reg' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1189' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\cos_eta_reg' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1190' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\sin_eta_reg' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1191' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\cos_psi_reg' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1192' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\sin_psi_reg' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1193' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\cos_phi_psi_reg' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1194' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\sin_phi_psi_reg' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1195' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\vdc_sq' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $dff cell `$procdff$1196' with positive edge clock.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\one_minus_vdc' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $dff cell `$procdff$1197' with positive edge clock.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\vdc0_start' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1198' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\vdc1_start' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1199' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\vdc2_start' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1200' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\trig_start' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1201' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\trig_angle' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1202' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\sqrt_approx' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1203' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\x' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1204' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\y0' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1205' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\y1' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1206' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\y2' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1207' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\x_div_y0' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1208' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:327$1$\x_div_y1' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1209' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\sqrt_approx' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1210' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\x' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1211' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\y0' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1212' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\y1' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1213' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\y2' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1214' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\x_div_y0' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1215' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.$func$\sqrt_approx$sphere3hopf_fsm_32bit_simple.v:328$2$\x_div_y1' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
  created $adff cell `$procdff$1216' with positive edge clock and negative level reset.
Creating register for signal `\sphere3hopf_fsm_32bit_simple.\current_state' using process `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:191$3'.
  created $adff cell `$procdff$1217' with positive edge clock and negative level reset.

8.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:62$201'.
Found and cleaned up 9 empty switches in `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:108$145'.
Removing empty process `cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:108$145'.
Found and cleaned up 3 empty switches in `\cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:92$143'.
Removing empty process `cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:92$143'.
Removing empty process `cordic_trig_16bit_simple_fixed.$proc$cordic_trig_16bit_simple_fixed.v:83$141'.
Found and cleaned up 6 empty switches in `\vdcorput_fsm_32bit_simple.$proc$vdcorput_fsm_32bit_simple.v:94$114'.
Removing empty process `vdcorput_fsm_32bit_simple.$proc$vdcorput_fsm_32bit_simple.v:94$114'.
Found and cleaned up 3 empty switches in `\vdcorput_fsm_32bit_simple.$proc$vdcorput_fsm_32bit_simple.v:74$112'.
Removing empty process `vdcorput_fsm_32bit_simple.$proc$vdcorput_fsm_32bit_simple.v:74$112'.
Removing empty process `vdcorput_fsm_32bit_simple.$proc$vdcorput_fsm_32bit_simple.v:65$110'.
Found and cleaned up 11 empty switches in `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
Removing empty process `sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:230$6'.
Found and cleaned up 6 empty switches in `\sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:200$5'.
Removing empty process `sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:200$5'.
Removing empty process `sphere3hopf_fsm_32bit_simple.$proc$sphere3hopf_fsm_32bit_simple.v:191$3'.
Cleaned up 38 empty switches.

9. Executing OPT pass (performing simple optimizations).

9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module div_mod_3.
Optimizing module div_mod_7.
Optimizing module cordic_trig_16bit_simple_fixed.
<suppressed ~20 debug messages>
Optimizing module vdcorput_fsm_32bit_simple.
<suppressed ~11 debug messages>
Optimizing module sphere3hopf_fsm_32bit_simple.
<suppressed ~24 debug messages>

9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\div_mod_3'.
<suppressed ~3 debug messages>
Finding identical cells in module `\div_mod_7'.
<suppressed ~3 debug messages>
Finding identical cells in module `\cordic_trig_16bit_simple_fixed'.
<suppressed ~111 debug messages>
Finding identical cells in module `\vdcorput_fsm_32bit_simple'.
<suppressed ~69 debug messages>
Finding identical cells in module `\sphere3hopf_fsm_32bit_simple'.
<suppressed ~255 debug messages>
Removed a total of 147 cells.

9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \div_mod_3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \div_mod_7..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \cordic_trig_16bit_simple_fixed..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $procmux$489.
    dead port 2/2 on $mux $procmux$481.
    dead port 2/2 on $mux $procmux$372.
    dead port 2/2 on $mux $procmux$364.
    dead port 2/2 on $mux $procmux$362.
    dead port 2/2 on $mux $procmux$353.
    dead port 2/2 on $mux $procmux$351.
    dead port 1/2 on $mux $procmux$349.
    dead port 2/2 on $mux $procmux$339.
    dead port 2/2 on $mux $procmux$337.
    dead port 1/2 on $mux $procmux$335.
    dead port 1/2 on $mux $procmux$332.
    dead port 2/2 on $mux $procmux$322.
    dead port 2/2 on $mux $procmux$316.
    dead port 2/2 on $mux $procmux$310.
    dead port 1/2 on $mux $procmux$308.
    dead port 2/2 on $mux $procmux$301.
    dead port 1/2 on $mux $procmux$299.
    dead port 2/2 on $mux $procmux$292.
    dead port 1/2 on $mux $procmux$290.
    dead port 1/2 on $mux $procmux$287.
    dead port 2/2 on $mux $procmux$280.
    dead port 1/2 on $mux $procmux$278.
    dead port 1/2 on $mux $procmux$275.
Running muxtree optimizer on module \vdcorput_fsm_32bit_simple..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $procmux$582.
    dead port 2/2 on $mux $procmux$570.
Running muxtree optimizer on module \sphere3hopf_fsm_32bit_simple..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 1/2 on $mux $procmux$877.
    dead port 2/2 on $mux $procmux$877.
    dead port 1/2 on $mux $procmux$872.
    dead port 2/2 on $mux $procmux$872.
    dead port 2/2 on $mux $procmux$1139.
    dead port 1/2 on $mux $procmux$867.
    dead port 2/2 on $mux $procmux$867.
    dead port 1/2 on $mux $procmux$862.
    dead port 2/2 on $mux $procmux$862.
    dead port 1/2 on $mux $procmux$857.
    dead port 2/2 on $mux $procmux$857.
    dead port 2/2 on $mux $procmux$1122.
    dead port 1/2 on $mux $procmux$852.
    dead port 2/2 on $mux $procmux$852.
    dead port 1/2 on $mux $procmux$847.
    dead port 2/2 on $mux $procmux$847.
    dead port 1/2 on $mux $procmux$842.
    dead port 2/2 on $mux $procmux$842.
    dead port 2/2 on $mux $procmux$1107.
    dead port 1/2 on $mux $procmux$837.
    dead port 2/2 on $mux $procmux$837.
    dead port 1/2 on $mux $procmux$832.
    dead port 2/2 on $mux $procmux$832.
    dead port 1/2 on $mux $procmux$827.
    dead port 2/2 on $mux $procmux$827.
    dead port 2/2 on $mux $procmux$1094.
    dead port 1/2 on $mux $procmux$822.
    dead port 2/2 on $mux $procmux$822.
    dead port 1/2 on $mux $procmux$817.
    dead port 2/2 on $mux $procmux$817.
    dead port 1/2 on $mux $procmux$812.
    dead port 2/2 on $mux $procmux$812.
    dead port 2/2 on $mux $procmux$1083.
    dead port 2/2 on $mux $procmux$807.
    dead port 2/2 on $mux $procmux$799.
    dead port 1/2 on $mux $procmux$791.
    dead port 2/2 on $mux $procmux$791.
    dead port 1/2 on $mux $procmux$789.
    dead port 2/2 on $mux $procmux$789.
    dead port 1/2 on $mux $procmux$783.
    dead port 2/2 on $mux $procmux$783.
    dead port 1/2 on $mux $procmux$781.
    dead port 2/2 on $mux $procmux$781.
    dead port 1/2 on $mux $procmux$775.
    dead port 2/2 on $mux $procmux$775.
    dead port 1/2 on $mux $procmux$773.
    dead port 2/2 on $mux $procmux$773.
    dead port 1/2 on $mux $procmux$767.
    dead port 2/2 on $mux $procmux$767.
    dead port 1/2 on $mux $procmux$765.
    dead port 2/2 on $mux $procmux$765.
    dead port 1/2 on $mux $procmux$759.
    dead port 2/2 on $mux $procmux$759.
    dead port 1/2 on $mux $procmux$757.
    dead port 2/2 on $mux $procmux$757.
    dead port 1/2 on $mux $procmux$751.
    dead port 2/2 on $mux $procmux$751.
    dead port 1/2 on $mux $procmux$749.
    dead port 2/2 on $mux $procmux$749.
    dead port 1/2 on $mux $procmux$743.
    dead port 2/2 on $mux $procmux$743.
    dead port 1/2 on $mux $procmux$741.
    dead port 2/2 on $mux $procmux$741.
    dead port 1/2 on $mux $procmux$735.
    dead port 2/2 on $mux $procmux$735.
    dead port 1/2 on $mux $procmux$733.
    dead port 2/2 on $mux $procmux$733.
    dead port 1/2 on $mux $procmux$727.
    dead port 2/2 on $mux $procmux$727.
    dead port 1/2 on $mux $procmux$725.
    dead port 2/2 on $mux $procmux$725.
    dead port 1/2 on $mux $procmux$719.
    dead port 2/2 on $mux $procmux$719.
    dead port 1/2 on $mux $procmux$717.
    dead port 2/2 on $mux $procmux$717.
    dead port 1/2 on $mux $procmux$711.
    dead port 2/2 on $mux $procmux$711.
    dead port 1/2 on $mux $procmux$709.
    dead port 2/2 on $mux $procmux$709.
    dead port 1/2 on $mux $procmux$703.
    dead port 2/2 on $mux $procmux$703.
    dead port 1/2 on $mux $procmux$701.
    dead port 2/2 on $mux $procmux$701.
    dead port 1/2 on $mux $procmux$695.
    dead port 2/2 on $mux $procmux$695.
    dead port 1/2 on $mux $procmux$693.
    dead port 2/2 on $mux $procmux$693.
    dead port 1/2 on $mux $procmux$687.
    dead port 2/2 on $mux $procmux$687.
    dead port 1/2 on $mux $procmux$685.
    dead port 2/2 on $mux $procmux$685.
    dead port 1/2 on $mux $procmux$679.
    dead port 2/2 on $mux $procmux$679.
    dead port 1/2 on $mux $procmux$677.
    dead port 2/2 on $mux $procmux$677.
    dead port 1/2 on $mux $procmux$675.
    dead port 2/2 on $mux $procmux$675.
    dead port 1/2 on $mux $procmux$657.
    dead port 2/2 on $mux $procmux$657.
    dead port 1/2 on $mux $procmux$655.
    dead port 2/2 on $mux $procmux$655.
    dead port 1/2 on $mux $procmux$653.
    dead port 2/2 on $mux $procmux$653.
    dead port 2/2 on $mux $procmux$646.
    dead port 2/2 on $mux $procmux$644.
    dead port 1/2 on $mux $procmux$635.
    dead port 2/2 on $mux $procmux$635.
    dead port 1/2 on $mux $procmux$633.
    dead port 2/2 on $mux $procmux$633.
    dead port 1/2 on $mux $procmux$631.
    dead port 2/2 on $mux $procmux$631.
    dead port 1/2 on $mux $procmux$613.
    dead port 2/2 on $mux $procmux$613.
    dead port 1/2 on $mux $procmux$611.
    dead port 2/2 on $mux $procmux$611.
    dead port 1/2 on $mux $procmux$609.
    dead port 2/2 on $mux $procmux$609.
    dead port 2/2 on $mux $procmux$602.
    dead port 2/2 on $mux $procmux$600.
Removed 145 multiplexer ports.
<suppressed ~60 debug messages>

9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \div_mod_3.
  Optimizing cells in module \div_mod_7.
  Optimizing cells in module \cordic_trig_16bit_simple_fixed.
  Optimizing cells in module \vdcorput_fsm_32bit_simple.
  Optimizing cells in module \sphere3hopf_fsm_32bit_simple.
Performed a total of 0 changes.

9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\div_mod_3'.
Finding identical cells in module `\div_mod_7'.
Finding identical cells in module `\cordic_trig_16bit_simple_fixed'.
Finding identical cells in module `\vdcorput_fsm_32bit_simple'.
Finding identical cells in module `\sphere3hopf_fsm_32bit_simple'.
Removed a total of 0 cells.

9.6. Executing OPT_RMDFF pass (remove dff with constant values).
Removing $procdff$1203 ($adff) from module sphere3hopf_fsm_32bit_simple.
Removing $procdff$1208 ($adff) from module sphere3hopf_fsm_32bit_simple.
Replaced 2 DFF cells.

9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \div_mod_3..
Finding unused cells or wires in module \div_mod_7..
Finding unused cells or wires in module \cordic_trig_16bit_simple_fixed..
Finding unused cells or wires in module \vdcorput_fsm_32bit_simple..
Finding unused cells or wires in module \sphere3hopf_fsm_32bit_simple..
Removed 20 unused cells and 613 unused wires.
<suppressed ~35 debug messages>

9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module cordic_trig_16bit_simple_fixed.
Optimizing module div_mod_3.
Optimizing module div_mod_7.
Optimizing module sphere3hopf_fsm_32bit_simple.
Optimizing module vdcorput_fsm_32bit_simple.

9.9. Rerunning OPT passes. (Maybe there is more to do..)

9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \cordic_trig_16bit_simple_fixed..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \div_mod_3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \div_mod_7..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \sphere3hopf_fsm_32bit_simple..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \vdcorput_fsm_32bit_simple..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~48 debug messages>

9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \cordic_trig_16bit_simple_fixed.
  Optimizing cells in module \div_mod_3.
  Optimizing cells in module \div_mod_7.
  Optimizing cells in module \sphere3hopf_fsm_32bit_simple.
  Optimizing cells in module \vdcorput_fsm_32bit_simple.
Performed a total of 0 changes.

9.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cordic_trig_16bit_simple_fixed'.
Finding identical cells in module `\div_mod_3'.
Finding identical cells in module `\div_mod_7'.
Finding identical cells in module `\sphere3hopf_fsm_32bit_simple'.
Finding identical cells in module `\vdcorput_fsm_32bit_simple'.
Removed a total of 0 cells.

9.13. Executing OPT_RMDFF pass (remove dff with constant values).

9.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cordic_trig_16bit_simple_fixed..
Finding unused cells or wires in module \div_mod_3..
Finding unused cells or wires in module \div_mod_7..
Finding unused cells or wires in module \sphere3hopf_fsm_32bit_simple..
Finding unused cells or wires in module \vdcorput_fsm_32bit_simple..

9.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module cordic_trig_16bit_simple_fixed.
Optimizing module div_mod_3.
Optimizing module div_mod_7.
Optimizing module sphere3hopf_fsm_32bit_simple.
Optimizing module vdcorput_fsm_32bit_simple.

9.16. Finished OPT passes. (There is nothing left to do.)

10. Executing FSM pass (extract and optimize FSM).

10.1. Executing FSM_DETECT pass (finding FSMs in design).
Found FSM state register cordic_trig_16bit_simple_fixed.state.
Found FSM state register sphere3hopf_fsm_32bit_simple.current_state.
Found FSM state register vdcorput_fsm_32bit_simple.base_reg.
Found FSM state register vdcorput_fsm_32bit_simple.current_state.

10.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\state' from module `\cordic_trig_16bit_simple_fixed'.
  found $adff cell for state register: $procdff$1169
  root of input selection tree: \next_state
  found reset state: 2'00 (from async reset)
  found ctrl input: $procmux$281_CMP
  found ctrl input: $procmux$405_CMP
  found ctrl input: $procmux$340_CMP
  found ctrl input: $eq$cordic_trig_16bit_simple_fixed.v:99$144_Y
  found state code: 2'10
  found ctrl input: \start
  found state code: 2'01
  found ctrl output: $procmux$281_CMP
  found ctrl output: $procmux$405_CMP
  found ctrl output: $procmux$340_CMP
  ctrl inputs: { $eq$cordic_trig_16bit_simple_fixed.v:99$144_Y \start }
  ctrl outputs: { $procmux$405_CMP $procmux$340_CMP $procmux$281_CMP \next_state }
  transition:       2'00 2'-0 ->       2'00 5'01000
  transition:       2'00 2'-1 ->       2'01 5'01001
  transition:       2'10 2'-- ->       2'00 5'00100
  transition:       2'01 2'0- ->       2'01 5'10001
  transition:       2'01 2'1- ->       2'10 5'10010
Extracting FSM `\current_state' from module `\sphere3hopf_fsm_32bit_simple'.
  found $adff cell for state register: $procdff$1217
  root of input selection tree: \next_state
  found reset state: 5'00000 (from async reset)
  found ctrl input: $procmux$1063_CMP
  found ctrl input: $procmux$1145_CMP
  found ctrl input: $procmux$1084_CMP
  found ctrl input: $procmux$1147_CMP
  found ctrl input: $procmux$1095_CMP
  found ctrl input: $procmux$1149_CMP
  found ctrl input: $procmux$1009_CMP
  found ctrl input: $procmux$1151_CMP
  found ctrl input: $procmux$1023_CMP
  found ctrl input: $procmux$1153_CMP
  found ctrl input: $procmux$1039_CMP
  found state code: 5'01011
  found state code: 5'01010
  found ctrl input: \trig_done
  found state code: 5'01001
  found state code: 5'01000
  found ctrl input: \vdc2_done
  found state code: 5'00111
  found state code: 5'00110
  found ctrl input: \vdc1_done
  found state code: 5'00101
  found state code: 5'00100
  found ctrl input: \vdc0_done
  found state code: 5'00011
  found state code: 5'00010
  found ctrl input: \start
  found state code: 5'00001
  found ctrl output: $procmux$1058_CMP
  found ctrl output: $procmux$1063_CMP
  found ctrl output: $procmux$1145_CMP
  found ctrl output: $procmux$1084_CMP
  found ctrl output: $procmux$1147_CMP
  found ctrl output: $procmux$1095_CMP
  found ctrl output: $procmux$1149_CMP
  found ctrl output: $procmux$1009_CMP
  found ctrl output: $procmux$1151_CMP
  found ctrl output: $procmux$1023_CMP
  found ctrl output: $procmux$1153_CMP
  found ctrl output: $procmux$1039_CMP
  ctrl inputs: { \trig_done \vdc2_done \vdc1_done \vdc0_done \start }
  ctrl outputs: { $procmux$1153_CMP $procmux$1151_CMP $procmux$1149_CMP $procmux$1145_CMP $procmux$1147_CMP $procmux$1095_CMP $procmux$1084_CMP $procmux$1063_CMP $procmux$1058_CMP $procmux$1039_CMP $procmux$1023_CMP $procmux$1009_CMP \next_state }
  transition:    5'00000 5'----0 ->    5'00000 17'00000000010000000
  transition:    5'00000 5'----1 ->    5'00001 17'00000000010000001
  transition:    5'01000 5'0---- ->    5'01000 17'00000010000001000
  transition:    5'01000 5'1---- ->    5'01001 17'00000010000001001
  transition:    5'00100 5'--0-- ->    5'00100 17'00000000000100100
  transition:    5'00100 5'--1-- ->    5'00101 17'00000000000100101
  transition:    5'00010 5'---0- ->    5'00010 17'00000000001000010
  transition:    5'00010 5'---1- ->    5'00011 17'00000000001000011
  transition:    5'01010 5'----- ->    5'01011 17'00000001000001011
  transition:    5'00110 5'-0--- ->    5'00110 17'00000100000000110
  transition:    5'00110 5'-1--- ->    5'00111 17'00000100000000111
  transition:    5'00001 5'----- ->    5'00010 17'10000000000000010
  transition:    5'01001 5'----- ->    5'01010 17'00010000000001010
  transition:    5'00101 5'----- ->    5'00110 17'00100000000000110
  transition:    5'00011 5'----- ->    5'00100 17'01000000000000100
  transition:    5'01011 5'----- ->    5'00000 17'00000000100000000
  transition:    5'00111 5'----- ->    5'01000 17'00001000000001000
Extracting FSM `\base_reg' from module `\vdcorput_fsm_32bit_simple'.
  found $adff cell for state register: $procdff$1176
  root of input selection tree: $0\base_reg[31:0]
  found reset state: 2 (from async reset)
  found ctrl input: $procmux$525_CMP
  found ctrl input: $procmux$522_CMP
  found ctrl input: $procmux$523_CMP
  found state code: 7
  found state code: 3
  found ctrl output: $procmux$501_CMP
  found ctrl output: $procmux$502_CMP
  found ctrl output: $procmux$503_CMP
  ctrl inputs: { $procmux$525_CMP $procmux$523_CMP $procmux$522_CMP }
  ctrl outputs: { $procmux$503_CMP $procmux$502_CMP $procmux$501_CMP $0\base_reg[31:0] }
  transition:          2 3'0-- ->          2 35'10000000000000000000000000000000010
  transition:          2 3'100 ->          2 35'10000000000000000000000000000000010
  transition:          2 3'11- ->          3 35'10000000000000000000000000000000011
  transition:          2 3'1-1 ->          7 35'10000000000000000000000000000000111
  transition:          3 3'0-- ->          3 35'01000000000000000000000000000000011
  transition:          3 3'100 ->          2 35'01000000000000000000000000000000010
  transition:          3 3'11- ->          3 35'01000000000000000000000000000000011
  transition:          3 3'1-1 ->          7 35'01000000000000000000000000000000111
  transition:          7 3'0-- ->          7 35'00100000000000000000000000000000111
  transition:          7 3'100 ->          2 35'00100000000000000000000000000000010
  transition:          7 3'11- ->          3 35'00100000000000000000000000000000011
  transition:          7 3'1-1 ->          7 35'00100000000000000000000000000000111
Extracting FSM `\current_state' from module `\vdcorput_fsm_32bit_simple'.
  found $adff cell for state register: $procdff$1179
  root of input selection tree: \next_state
  found reset state: 3'000 (from async reset)
  found ctrl input: $procmux$571_CMP
  found ctrl input: $procmux$532_CMP
  found ctrl input: $procmux$543_CMP
  found ctrl input: $procmux$505_CMP
  found ctrl input: $procmux$525_CMP
  found ctrl input: $procmux$552_CMP
  found ctrl input: $eq$vdcorput_fsm_32bit_simple.v:85$113_Y
  found state code: 3'010
  found state code: 3'110
  found state code: 3'101
  found state code: 3'100
  found state code: 3'011
  found ctrl input: \start
  found state code: 3'001
  found ctrl output: $procmux$546_CMP
  found ctrl output: $procmux$571_CMP
  found ctrl output: $procmux$532_CMP
  found ctrl output: $procmux$543_CMP
  found ctrl output: $procmux$505_CMP
  found ctrl output: $procmux$525_CMP
  found ctrl output: $procmux$552_CMP
  ctrl inputs: { $eq$vdcorput_fsm_32bit_simple.v:85$113_Y \start }
  ctrl outputs: { $procmux$571_CMP $procmux$552_CMP $procmux$546_CMP $procmux$543_CMP $procmux$532_CMP $procmux$525_CMP $procmux$505_CMP \next_state }
  transition:      3'000 2'-0 ->      3'000 10'0100000000
  transition:      3'000 2'-1 ->      3'001 10'0100000001
  transition:      3'100 2'-- ->      3'101 10'0000100101
  transition:      3'010 2'-- ->      3'011 10'0000001011
  transition:      3'110 2'-- ->      3'000 10'0010000000
  transition:      3'001 2'-- ->      3'010 10'0000010010
  transition:      3'101 2'0- ->      3'010 10'1000000010
  transition:      3'101 2'1- ->      3'110 10'1000000110
  transition:      3'011 2'-- ->      3'100 10'0001000100

10.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\state$1218' from module `\cordic_trig_16bit_simple_fixed'.
Optimizing FSM `$fsm$\current_state$1223' from module `\sphere3hopf_fsm_32bit_simple'.
Optimizing FSM `$fsm$\current_state$1242' from module `\vdcorput_fsm_32bit_simple'.
Optimizing FSM `$fsm$\base_reg$1237' from module `\vdcorput_fsm_32bit_simple'.

10.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cordic_trig_16bit_simple_fixed..
Finding unused cells or wires in module \div_mod_3..
Finding unused cells or wires in module \div_mod_7..
Finding unused cells or wires in module \sphere3hopf_fsm_32bit_simple..
Finding unused cells or wires in module \vdcorput_fsm_32bit_simple..
Removed 43 unused cells and 43 unused wires.
<suppressed ~46 debug messages>

10.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\state$1218' from module `\cordic_trig_16bit_simple_fixed'.
  Removing unused output signal \next_state [0].
  Removing unused output signal \next_state [1].
Optimizing FSM `$fsm$\current_state$1223' from module `\sphere3hopf_fsm_32bit_simple'.
  Removing unused output signal \next_state [0].
  Removing unused output signal \next_state [1].
  Removing unused output signal \next_state [2].
  Removing unused output signal \next_state [3].
  Removing unused output signal \next_state [4].
Optimizing FSM `$fsm$\base_reg$1237' from module `\vdcorput_fsm_32bit_simple'.
  Removing unused output signal $0\base_reg[31:0] [0].
  Removing unused output signal $0\base_reg[31:0] [1].
  Removing unused output signal $0\base_reg[31:0] [2].
  Removing unused output signal $0\base_reg[31:0] [3].
  Removing unused output signal $0\base_reg[31:0] [4].
  Removing unused output signal $0\base_reg[31:0] [5].
  Removing unused output signal $0\base_reg[31:0] [6].
  Removing unused output signal $0\base_reg[31:0] [7].
  Removing unused output signal $0\base_reg[31:0] [8].
  Removing unused output signal $0\base_reg[31:0] [9].
  Removing unused output signal $0\base_reg[31:0] [10].
  Removing unused output signal $0\base_reg[31:0] [11].
  Removing unused output signal $0\base_reg[31:0] [12].
  Removing unused output signal $0\base_reg[31:0] [13].
  Removing unused output signal $0\base_reg[31:0] [14].
  Removing unused output signal $0\base_reg[31:0] [15].
  Removing unused output signal $0\base_reg[31:0] [16].
  Removing unused output signal $0\base_reg[31:0] [17].
  Removing unused output signal $0\base_reg[31:0] [18].
  Removing unused output signal $0\base_reg[31:0] [19].
  Removing unused output signal $0\base_reg[31:0] [20].
  Removing unused output signal $0\base_reg[31:0] [21].
  Removing unused output signal $0\base_reg[31:0] [22].
  Removing unused output signal $0\base_reg[31:0] [23].
  Removing unused output signal $0\base_reg[31:0] [24].
  Removing unused output signal $0\base_reg[31:0] [25].
  Removing unused output signal $0\base_reg[31:0] [26].
  Removing unused output signal $0\base_reg[31:0] [27].
  Removing unused output signal $0\base_reg[31:0] [28].
  Removing unused output signal $0\base_reg[31:0] [29].
  Removing unused output signal $0\base_reg[31:0] [30].
  Removing unused output signal $0\base_reg[31:0] [31].
Optimizing FSM `$fsm$\current_state$1242' from module `\vdcorput_fsm_32bit_simple'.
  Removing unused output signal \next_state [0].
  Removing unused output signal \next_state [1].
  Removing unused output signal \next_state [2].
  Removing unused output signal $procmux$571_CMP.

10.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\state$1218' from module `\cordic_trig_16bit_simple_fixed' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00 -> --1
  10 -> -1-
  01 -> 1--
Recoding FSM `$fsm$\current_state$1223' from module `\sphere3hopf_fsm_32bit_simple' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00000 -> -----------1
  01000 -> ----------1-
  00100 -> ---------1--
  00010 -> --------1---
  01010 -> -------1----
  00110 -> ------1-----
  00001 -> -----1------
  01001 -> ----1-------
  00101 -> ---1--------
  00011 -> --1---------
  01011 -> -1----------
  00111 -> 1-----------
Recoding FSM `$fsm$\base_reg$1237' from module `\vdcorput_fsm_32bit_simple' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00000000000000000000000000000010 -> --1
  00000000000000000000000000000011 -> -1-
  00000000000000000000000000000111 -> 1--
Recoding FSM `$fsm$\current_state$1242' from module `\vdcorput_fsm_32bit_simple' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ------1
  100 -> -----1-
  010 -> ----1--
  110 -> ---1---
  001 -> --1----
  101 -> -1-----
  011 -> 1------

10.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\state$1218' from module `\cordic_trig_16bit_simple_fixed':
-------------------------------------

  Information on FSM $fsm$\state$1218 (\state):

  Number of input signals:    2
  Number of output signals:   3
  Number of state bits:       3

  Input signals:
    0: \start
    1: $eq$cordic_trig_16bit_simple_fixed.v:99$144_Y

  Output signals:
    0: $procmux$281_CMP
    1: $procmux$340_CMP
    2: $procmux$405_CMP

  State encoding:
    0:      3'--1  <RESET STATE>
    1:      3'-1-
    2:      3'1--

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 2'-0   ->     0 3'010
      1:     0 2'-1   ->     2 3'010
      2:     1 2'--   ->     0 3'001
      3:     2 2'1-   ->     1 3'100
      4:     2 2'0-   ->     2 3'100

-------------------------------------

FSM `$fsm$\current_state$1223' from module `\sphere3hopf_fsm_32bit_simple':
-------------------------------------

  Information on FSM $fsm$\current_state$1223 (\current_state):

  Number of input signals:    5
  Number of output signals:  12
  Number of state bits:      12

  Input signals:
    0: \start
    1: \vdc0_done
    2: \vdc1_done
    3: \vdc2_done
    4: \trig_done

  Output signals:
    0: $procmux$1009_CMP
    1: $procmux$1023_CMP
    2: $procmux$1039_CMP
    3: $procmux$1058_CMP
    4: $procmux$1063_CMP
    5: $procmux$1084_CMP
    6: $procmux$1095_CMP
    7: $procmux$1147_CMP
    8: $procmux$1145_CMP
    9: $procmux$1149_CMP
   10: $procmux$1151_CMP
   11: $procmux$1153_CMP

  State encoding:
    0: 12'-----------1  <RESET STATE>
    1: 12'----------1-
    2: 12'---------1--
    3: 12'--------1---
    4: 12'-------1----
    5: 12'------1-----
    6: 12'-----1------
    7: 12'----1-------
    8: 12'---1--------
    9: 12'--1---------
   10: 12'-1----------
   11: 12'1-----------

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 5'----0   ->     0 12'000000000100
      1:     0 5'----1   ->     6 12'000000000100
      2:     1 5'0----   ->     1 12'000000100000
      3:     1 5'1----   ->     7 12'000000100000
      4:     2 5'--0--   ->     2 12'000000000001
      5:     2 5'--1--   ->     8 12'000000000001
      6:     3 5'---0-   ->     3 12'000000000010
      7:     3 5'---1-   ->     9 12'000000000010
      8:     4 5'-----   ->    10 12'000000010000
      9:     5 5'-0---   ->     5 12'000001000000
     10:     5 5'-1---   ->    11 12'000001000000
     11:     6 5'-----   ->     3 12'100000000000
     12:     7 5'-----   ->     4 12'000100000000
     13:     8 5'-----   ->     5 12'001000000000
     14:     9 5'-----   ->     2 12'010000000000
     15:    10 5'-----   ->     0 12'000000001000
     16:    11 5'-----   ->     1 12'000010000000

-------------------------------------

FSM `$fsm$\base_reg$1237' from module `\vdcorput_fsm_32bit_simple':
-------------------------------------

  Information on FSM $fsm$\base_reg$1237 (\base_reg):

  Number of input signals:    3
  Number of output signals:   3
  Number of state bits:       3

  Input signals:
    0: $procmux$522_CMP
    1: $procmux$523_CMP
    2: $procmux$525_CMP

  Output signals:
    0: $procmux$501_CMP
    1: $procmux$502_CMP
    2: $procmux$503_CMP

  State encoding:
    0:      3'--1  <RESET STATE>
    1:      3'-1-
    2:      3'1--

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 3'100   ->     0 3'100
      1:     0 3'0--   ->     0 3'100
      2:     0 3'11-   ->     1 3'100
      3:     0 3'1-1   ->     2 3'100
      4:     1 3'100   ->     0 3'010
      5:     1 3'11-   ->     1 3'010
      6:     1 3'0--   ->     1 3'010
      7:     1 3'1-1   ->     2 3'010
      8:     2 3'100   ->     0 3'001
      9:     2 3'11-   ->     1 3'001
     10:     2 3'1-1   ->     2 3'001
     11:     2 3'0--   ->     2 3'001

-------------------------------------

FSM `$fsm$\current_state$1242' from module `\vdcorput_fsm_32bit_simple':
-------------------------------------

  Information on FSM $fsm$\current_state$1242 (\current_state):

  Number of input signals:    2
  Number of output signals:   6
  Number of state bits:       7

  Input signals:
    0: \start
    1: $eq$vdcorput_fsm_32bit_simple.v:85$113_Y

  Output signals:
    0: $procmux$505_CMP
    1: $procmux$525_CMP
    2: $procmux$532_CMP
    3: $procmux$543_CMP
    4: $procmux$546_CMP
    5: $procmux$552_CMP

  State encoding:
    0:  7'------1  <RESET STATE>
    1:  7'-----1-
    2:  7'----1--
    3:  7'---1---
    4:  7'--1----
    5:  7'-1-----
    6:  7'1------

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 2'-0   ->     0 6'100000
      1:     0 2'-1   ->     4 6'100000
      2:     1 2'--   ->     5 6'000100
      3:     2 2'--   ->     6 6'000001
      4:     3 2'--   ->     0 6'010000
      5:     4 2'--   ->     2 6'000010
      6:     5 2'0-   ->     2 6'000000
      7:     5 2'1-   ->     3 6'000000
      8:     6 2'--   ->     1 6'001000

-------------------------------------

10.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\state$1218' from module `\cordic_trig_16bit_simple_fixed'.
Mapping FSM `$fsm$\current_state$1223' from module `\sphere3hopf_fsm_32bit_simple'.
Mapping FSM `$fsm$\base_reg$1237' from module `\vdcorput_fsm_32bit_simple'.
Mapping FSM `$fsm$\current_state$1242' from module `\vdcorput_fsm_32bit_simple'.

11. Executing OPT pass (performing simple optimizations).

11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module cordic_trig_16bit_simple_fixed.
<suppressed ~4 debug messages>
Optimizing module div_mod_3.
Optimizing module div_mod_7.
Optimizing module sphere3hopf_fsm_32bit_simple.
<suppressed ~10 debug messages>
Optimizing module vdcorput_fsm_32bit_simple.
<suppressed ~7 debug messages>

11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cordic_trig_16bit_simple_fixed'.
Finding identical cells in module `\div_mod_3'.
Finding identical cells in module `\div_mod_7'.
Finding identical cells in module `\sphere3hopf_fsm_32bit_simple'.
Finding identical cells in module `\vdcorput_fsm_32bit_simple'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \cordic_trig_16bit_simple_fixed..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \div_mod_3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \div_mod_7..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \sphere3hopf_fsm_32bit_simple..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \vdcorput_fsm_32bit_simple..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~44 debug messages>

11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \cordic_trig_16bit_simple_fixed.
  Optimizing cells in module \div_mod_3.
  Optimizing cells in module \div_mod_7.
  Optimizing cells in module \sphere3hopf_fsm_32bit_simple.
    New input vector for $reduce_or cell $auto$fsm_map.cc:144:implement_pattern_cache$1281: { \current_state [10] $auto$fsm_map.cc:118:implement_pattern_cache$1279 }
    New input vector for $reduce_or cell $auto$fsm_map.cc:144:implement_pattern_cache$1286: { \current_state [11] $auto$fsm_map.cc:118:implement_pattern_cache$1284 }
    New input vector for $reduce_or cell $auto$fsm_map.cc:144:implement_pattern_cache$1291: { \current_state [9] $auto$fsm_map.cc:118:implement_pattern_cache$1289 }
    New input vector for $reduce_or cell $auto$fsm_map.cc:144:implement_pattern_cache$1296: { \current_state [6] $auto$fsm_map.cc:118:implement_pattern_cache$1294 }
    New input vector for $reduce_or cell $auto$fsm_map.cc:144:implement_pattern_cache$1301: { \current_state [8] $auto$fsm_map.cc:118:implement_pattern_cache$1299 }
  Optimizing cells in module \sphere3hopf_fsm_32bit_simple.
  Optimizing cells in module \vdcorput_fsm_32bit_simple.
    New input vector for $reduce_or cell $auto$fsm_map.cc:144:implement_pattern_cache$1360: { \current_state [4] $auto$fsm_map.cc:118:implement_pattern_cache$1358 }
    New input vector for $reduce_or cell $auto$fsm_map.cc:144:implement_pattern_cache$1332: { $auto$fsm_map.cc:74:implement_pattern_cache$1326 $auto$fsm_map.cc:118:implement_pattern_cache$1330 }
    New input vector for $reduce_or cell $auto$fsm_map.cc:144:implement_pattern_cache$1339: { $auto$fsm_map.cc:74:implement_pattern_cache$1333 $auto$fsm_map.cc:118:implement_pattern_cache$1337 }
    New input vector for $reduce_or cell $auto$fsm_map.cc:144:implement_pattern_cache$1355: { \current_state [3] $auto$fsm_map.cc:118:implement_pattern_cache$1353 }
  Optimizing cells in module \vdcorput_fsm_32bit_simple.
Performed a total of 9 changes.

11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cordic_trig_16bit_simple_fixed'.
Finding identical cells in module `\div_mod_3'.
Finding identical cells in module `\div_mod_7'.
Finding identical cells in module `\sphere3hopf_fsm_32bit_simple'.
Finding identical cells in module `\vdcorput_fsm_32bit_simple'.
Removed a total of 0 cells.

11.6. Executing OPT_RMDFF pass (remove dff with constant values).

11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cordic_trig_16bit_simple_fixed..
Finding unused cells or wires in module \div_mod_3..
Finding unused cells or wires in module \div_mod_7..
Finding unused cells or wires in module \sphere3hopf_fsm_32bit_simple..
Finding unused cells or wires in module \vdcorput_fsm_32bit_simple..
Removed 0 unused cells and 48 unused wires.
<suppressed ~6 debug messages>

11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module cordic_trig_16bit_simple_fixed.
Optimizing module div_mod_3.
Optimizing module div_mod_7.
Optimizing module sphere3hopf_fsm_32bit_simple.
Optimizing module vdcorput_fsm_32bit_simple.

11.9. Rerunning OPT passes. (Maybe there is more to do..)

11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \cordic_trig_16bit_simple_fixed..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \div_mod_3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \div_mod_7..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \sphere3hopf_fsm_32bit_simple..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \vdcorput_fsm_32bit_simple..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~44 debug messages>

11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \cordic_trig_16bit_simple_fixed.
  Optimizing cells in module \div_mod_3.
  Optimizing cells in module \div_mod_7.
  Optimizing cells in module \sphere3hopf_fsm_32bit_simple.
  Optimizing cells in module \vdcorput_fsm_32bit_simple.
Performed a total of 0 changes.

11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cordic_trig_16bit_simple_fixed'.
Finding identical cells in module `\div_mod_3'.
Finding identical cells in module `\div_mod_7'.
Finding identical cells in module `\sphere3hopf_fsm_32bit_simple'.
Finding identical cells in module `\vdcorput_fsm_32bit_simple'.
Removed a total of 0 cells.

11.13. Executing OPT_RMDFF pass (remove dff with constant values).

11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cordic_trig_16bit_simple_fixed..
Finding unused cells or wires in module \div_mod_3..
Finding unused cells or wires in module \div_mod_7..
Finding unused cells or wires in module \sphere3hopf_fsm_32bit_simple..
Finding unused cells or wires in module \vdcorput_fsm_32bit_simple..

11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module cordic_trig_16bit_simple_fixed.
Optimizing module div_mod_3.
Optimizing module div_mod_7.
Optimizing module sphere3hopf_fsm_32bit_simple.
Optimizing module vdcorput_fsm_32bit_simple.

11.16. Finished OPT passes. (There is nothing left to do.)

12. Executing MEMORY pass.

12.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
Checking cell `$memrd$\atan_table$cordic_trig_16bit_simple_fixed.v:176$163' in module `\cordic_trig_16bit_simple_fixed': no (compatible) $dff found.

12.2. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cordic_trig_16bit_simple_fixed..
Finding unused cells or wires in module \div_mod_3..
Finding unused cells or wires in module \div_mod_7..
Finding unused cells or wires in module \sphere3hopf_fsm_32bit_simple..
Finding unused cells or wires in module \vdcorput_fsm_32bit_simple..

12.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cordic_trig_16bit_simple_fixed..
Finding unused cells or wires in module \div_mod_3..
Finding unused cells or wires in module \div_mod_7..
Finding unused cells or wires in module \sphere3hopf_fsm_32bit_simple..
Finding unused cells or wires in module \vdcorput_fsm_32bit_simple..

12.5. Executing MEMORY_COLLECT pass (generating $mem cells).
Collecting $memrd, $memwr and $meminit for memory `\atan_table' in module `\cordic_trig_16bit_simple_fixed':
  $meminit$\atan_table$cordic_trig_16bit_simple_fixed.v:64$185 ($meminit)
  $meminit$\atan_table$cordic_trig_16bit_simple_fixed.v:65$186 ($meminit)
  $meminit$\atan_table$cordic_trig_16bit_simple_fixed.v:66$187 ($meminit)
  $meminit$\atan_table$cordic_trig_16bit_simple_fixed.v:67$188 ($meminit)
  $meminit$\atan_table$cordic_trig_16bit_simple_fixed.v:68$189 ($meminit)
  $meminit$\atan_table$cordic_trig_16bit_simple_fixed.v:69$190 ($meminit)
  $meminit$\atan_table$cordic_trig_16bit_simple_fixed.v:70$191 ($meminit)
  $meminit$\atan_table$cordic_trig_16bit_simple_fixed.v:71$192 ($meminit)
  $meminit$\atan_table$cordic_trig_16bit_simple_fixed.v:72$193 ($meminit)
  $meminit$\atan_table$cordic_trig_16bit_simple_fixed.v:73$194 ($meminit)
  $meminit$\atan_table$cordic_trig_16bit_simple_fixed.v:74$195 ($meminit)
  $meminit$\atan_table$cordic_trig_16bit_simple_fixed.v:75$196 ($meminit)
  $meminit$\atan_table$cordic_trig_16bit_simple_fixed.v:76$197 ($meminit)
  $meminit$\atan_table$cordic_trig_16bit_simple_fixed.v:77$198 ($meminit)
  $meminit$\atan_table$cordic_trig_16bit_simple_fixed.v:78$199 ($meminit)
  $meminit$\atan_table$cordic_trig_16bit_simple_fixed.v:79$200 ($meminit)
  $memrd$\atan_table$cordic_trig_16bit_simple_fixed.v:176$163 ($memrd)

12.6. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
Mapping memory cell \atan_table in module \cordic_trig_16bit_simple_fixed:
  created 16 $dff cells and 0 static cells of width 16.
  read interface: 0 $dff and 15 $mux cells.
  write interface: 0 write mux blocks.

13. Executing OPT pass (performing simple optimizations).

13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module cordic_trig_16bit_simple_fixed.
Optimizing module div_mod_3.
Optimizing module div_mod_7.
Optimizing module sphere3hopf_fsm_32bit_simple.
Optimizing module vdcorput_fsm_32bit_simple.

13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cordic_trig_16bit_simple_fixed'.
Finding identical cells in module `\div_mod_3'.
Finding identical cells in module `\div_mod_7'.
Finding identical cells in module `\sphere3hopf_fsm_32bit_simple'.
Finding identical cells in module `\vdcorput_fsm_32bit_simple'.
Removed a total of 0 cells.

13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \cordic_trig_16bit_simple_fixed..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \div_mod_3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \div_mod_7..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \sphere3hopf_fsm_32bit_simple..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \vdcorput_fsm_32bit_simple..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~45 debug messages>

13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \cordic_trig_16bit_simple_fixed.
  Optimizing cells in module \div_mod_3.
  Optimizing cells in module \div_mod_7.
  Optimizing cells in module \sphere3hopf_fsm_32bit_simple.
  Optimizing cells in module \vdcorput_fsm_32bit_simple.
Performed a total of 0 changes.

13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cordic_trig_16bit_simple_fixed'.
Finding identical cells in module `\div_mod_3'.
Finding identical cells in module `\div_mod_7'.
Finding identical cells in module `\sphere3hopf_fsm_32bit_simple'.
Finding identical cells in module `\vdcorput_fsm_32bit_simple'.
Removed a total of 0 cells.

13.6. Executing OPT_RMDFF pass (remove dff with constant values).
Removing $memory\atan_table[15]$1400 ($dff) from module cordic_trig_16bit_simple_fixed.
Removing $memory\atan_table[14]$1398 ($dff) from module cordic_trig_16bit_simple_fixed.
Removing $memory\atan_table[13]$1396 ($dff) from module cordic_trig_16bit_simple_fixed.
Removing $memory\atan_table[12]$1394 ($dff) from module cordic_trig_16bit_simple_fixed.
Removing $memory\atan_table[11]$1392 ($dff) from module cordic_trig_16bit_simple_fixed.
Removing $memory\atan_table[10]$1390 ($dff) from module cordic_trig_16bit_simple_fixed.
Removing $memory\atan_table[9]$1388 ($dff) from module cordic_trig_16bit_simple_fixed.
Removing $memory\atan_table[8]$1386 ($dff) from module cordic_trig_16bit_simple_fixed.
Removing $memory\atan_table[7]$1384 ($dff) from module cordic_trig_16bit_simple_fixed.
Removing $memory\atan_table[6]$1382 ($dff) from module cordic_trig_16bit_simple_fixed.
Removing $memory\atan_table[5]$1380 ($dff) from module cordic_trig_16bit_simple_fixed.
Removing $memory\atan_table[4]$1378 ($dff) from module cordic_trig_16bit_simple_fixed.
Removing $memory\atan_table[3]$1376 ($dff) from module cordic_trig_16bit_simple_fixed.
Removing $memory\atan_table[2]$1374 ($dff) from module cordic_trig_16bit_simple_fixed.
Removing $memory\atan_table[1]$1372 ($dff) from module cordic_trig_16bit_simple_fixed.
Removing $memory\atan_table[0]$1370 ($dff) from module cordic_trig_16bit_simple_fixed.
Replaced 16 DFF cells.

13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cordic_trig_16bit_simple_fixed..
Finding unused cells or wires in module \div_mod_3..
Finding unused cells or wires in module \div_mod_7..
Finding unused cells or wires in module \sphere3hopf_fsm_32bit_simple..
Finding unused cells or wires in module \vdcorput_fsm_32bit_simple..
Removed 0 unused cells and 32 unused wires.
<suppressed ~1 debug messages>

13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module cordic_trig_16bit_simple_fixed.
Optimizing module div_mod_3.
Optimizing module div_mod_7.
Optimizing module sphere3hopf_fsm_32bit_simple.
Optimizing module vdcorput_fsm_32bit_simple.

13.9. Rerunning OPT passes. (Maybe there is more to do..)

13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \cordic_trig_16bit_simple_fixed..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \div_mod_3..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \div_mod_7..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \sphere3hopf_fsm_32bit_simple..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Running muxtree optimizer on module \vdcorput_fsm_32bit_simple..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~45 debug messages>

13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \cordic_trig_16bit_simple_fixed.
  Optimizing cells in module \div_mod_3.
  Optimizing cells in module \div_mod_7.
  Optimizing cells in module \sphere3hopf_fsm_32bit_simple.
  Optimizing cells in module \vdcorput_fsm_32bit_simple.
Performed a total of 0 changes.

13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cordic_trig_16bit_simple_fixed'.
Finding identical cells in module `\div_mod_3'.
Finding identical cells in module `\div_mod_7'.
Finding identical cells in module `\sphere3hopf_fsm_32bit_simple'.
Finding identical cells in module `\vdcorput_fsm_32bit_simple'.
Removed a total of 0 cells.

13.13. Executing OPT_RMDFF pass (remove dff with constant values).

13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cordic_trig_16bit_simple_fixed..
Finding unused cells or wires in module \div_mod_3..
Finding unused cells or wires in module \div_mod_7..
Finding unused cells or wires in module \sphere3hopf_fsm_32bit_simple..
Finding unused cells or wires in module \vdcorput_fsm_32bit_simple..

13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module cordic_trig_16bit_simple_fixed.
Optimizing module div_mod_3.
Optimizing module div_mod_7.
Optimizing module sphere3hopf_fsm_32bit_simple.
Optimizing module vdcorput_fsm_32bit_simple.

13.16. Finished OPT passes. (There is nothing left to do.)

14. Executing TECHMAP pass (map to technology primitives).

14.1. Executing Verilog-2005 frontend: <techmap.v>
Parsing Verilog input from `<techmap.v>' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

14.2. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $and.
Running "alumacc" on wrapper $extern:wrap:$mul:A_SIGNED=0:A_WIDTH=32:B_SIGNED=0:B_WIDTH=32:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$mul:A_SIGNED=0:A_WIDTH=32:B_SIGNED=0:B_WIDTH=32:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$mul:A_SIGNED=0:A_WIDTH=32:B_SIGNED=0:B_WIDTH=32:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=32:B_SIGNED=0:B_WIDTH=32:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=32:B_SIGNED=0:B_WIDTH=32:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=32:B_SIGNED=0:B_WIDTH=32:Y_WIDTH=32:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$mul:A_SIGNED=0:A_WIDTH=32:B_SIGNED=0:B_WIDTH=32:Y_WIDTH=64:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$mul:A_SIGNED=0:A_WIDTH=32:B_SIGNED=0:B_WIDTH=32:Y_WIDTH=64:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$mul:A_SIGNED=0:A_WIDTH=32:B_SIGNED=0:B_WIDTH=32:Y_WIDTH=64:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=32:B_SIGNED=0:B_WIDTH=64:Y_WIDTH=64:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=32:B_SIGNED=0:B_WIDTH=64:Y_WIDTH=64:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:A_SIGNED=0:A_WIDTH=32:B_SIGNED=0:B_WIDTH=64:Y_WIDTH=64:394426c56d1a028ba8fdd5469b163e04011def47.
Using extmapper simplemap for cells of type $reduce_bool.
Using template $paramod\_90_div\A_SIGNED=0\B_SIGNED=0\A_WIDTH=64\B_WIDTH=32\Y_WIDTH=64 for cells of type $div.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $mux.
Using template $paramod\_90_pmux\WIDTH=32\S_WIDTH=2 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=3 for cells of type $pmux.
Using template $paramod\_90_pmux\WIDTH=1\S_WIDTH=2 for cells of type $pmux.
Using extmapper simplemap for cells of type $adff.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=64\Y_WIDTH=64 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=32\B_WIDTH=32\Y_WIDTH=32 for cells of type $alu.
Using template $paramod\$__div_mod\A_SIGNED=0\B_SIGNED=0\A_WIDTH=64\B_WIDTH=32\Y_WIDTH=64 for cells of type $__div_mod.
Using extmapper maccmap for cells of type $macc.
  add \sin_eta_reg * \sin_phi_psi_reg (32x32 bits, unsigned)
  add \sin_eta_reg * \cos_phi_psi_reg (32x32 bits, unsigned)
  add \cos_eta_reg * \sin_psi_reg (32x32 bits, unsigned)
  add \cos_eta_reg * \cos_psi_reg (32x32 bits, unsigned)
  add \vdc_reg * \vdc_reg (32x32 bits, unsigned)
  add \vdc0_result * 411774 (32x32 bits, unsigned)
  add \vdc1_result * 411774 (32x32 bits, unsigned)
Using extmapper simplemap for cells of type $xor.
Using template $paramod\_90_lcu\WIDTH=64 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu\WIDTH=32 for cells of type $lcu.
Using extmapper simplemap for cells of type $ne.
Running "alumacc" on wrapper $extern:wrap:$neg:Y_WIDTH=64:A_WIDTH=64:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$neg:Y_WIDTH=64:A_WIDTH=64:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$neg:Y_WIDTH=64:A_WIDTH=64:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod\$__div_mod_u\WIDTH=64 for cells of type $__div_mod_u.
Using template $paramod\_90_fa\WIDTH=32 for cells of type $fa.
Using template $paramod\_90_fa\WIDTH=64 for cells of type $fa.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=64\B_WIDTH=64\Y_WIDTH=64 for cells of type $alu.
Using template $paramod\_90_alu\A_SIGNED=0\B_SIGNED=0\A_WIDTH=0\B_WIDTH=64\Y_WIDTH=64 for cells of type $alu.
Using extmapper simplemap for cells of type $or.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=64:B_WIDTH=64:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=64:B_WIDTH=64:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=64:B_WIDTH=64:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=64:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=64:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=64:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=65:B_WIDTH=65:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=65:B_WIDTH=65:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=65:B_WIDTH=65:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=65:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=65:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=65:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=66:B_WIDTH=66:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=66:B_WIDTH=66:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=66:B_WIDTH=66:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=66:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=66:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=66:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=67:B_WIDTH=67:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=67:B_WIDTH=67:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=67:B_WIDTH=67:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=67:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=67:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=67:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=68:B_WIDTH=68:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=68:B_WIDTH=68:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=68:B_WIDTH=68:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=68:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=68:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=68:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=69:B_WIDTH=69:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=69:B_WIDTH=69:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=69:B_WIDTH=69:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=69:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=69:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=69:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=70:B_WIDTH=70:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=70:B_WIDTH=70:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=70:B_WIDTH=70:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=70:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=70:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=70:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=71:B_WIDTH=71:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=71:B_WIDTH=71:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=71:B_WIDTH=71:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=71:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=71:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=71:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=72:B_WIDTH=72:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=72:B_WIDTH=72:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=72:B_WIDTH=72:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=72:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=72:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=72:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=73:B_WIDTH=73:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=73:B_WIDTH=73:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=73:B_WIDTH=73:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=73:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=73:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=73:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=74:B_WIDTH=74:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=74:B_WIDTH=74:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=74:B_WIDTH=74:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=74:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=74:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=74:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=75:B_WIDTH=75:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=75:B_WIDTH=75:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=75:B_WIDTH=75:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=75:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=75:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=75:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=76:B_WIDTH=76:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=76:B_WIDTH=76:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=76:B_WIDTH=76:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=76:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=76:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=76:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=77:B_WIDTH=77:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=77:B_WIDTH=77:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=77:B_WIDTH=77:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=77:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=77:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=77:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=78:B_WIDTH=78:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=78:B_WIDTH=78:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=78:B_WIDTH=78:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=78:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=78:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=78:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=79:B_WIDTH=79:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=79:B_WIDTH=79:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=79:B_WIDTH=79:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=79:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=79:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=79:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=80:B_WIDTH=80:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=80:B_WIDTH=80:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=80:B_WIDTH=80:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=80:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=80:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=80:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=81:B_WIDTH=81:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=81:B_WIDTH=81:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=81:B_WIDTH=81:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=81:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=81:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=81:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=82:B_WIDTH=82:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=82:B_WIDTH=82:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=82:B_WIDTH=82:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=82:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=82:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=82:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=83:B_WIDTH=83:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=83:B_WIDTH=83:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=83:B_WIDTH=83:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=83:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=83:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=83:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=84:B_WIDTH=84:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=84:B_WIDTH=84:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=84:B_WIDTH=84:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=84:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=84:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=84:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=85:B_WIDTH=85:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=85:B_WIDTH=85:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=85:B_WIDTH=85:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=85:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=85:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=85:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=86:B_WIDTH=86:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=86:B_WIDTH=86:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=86:B_WIDTH=86:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=86:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=86:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=86:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=87:B_WIDTH=87:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=87:B_WIDTH=87:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=87:B_WIDTH=87:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=87:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=87:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=87:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=88:B_WIDTH=88:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=88:B_WIDTH=88:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=88:B_WIDTH=88:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=88:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=88:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=88:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=89:B_WIDTH=89:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=89:B_WIDTH=89:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=89:B_WIDTH=89:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=89:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=89:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=89:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=90:B_WIDTH=90:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=90:B_WIDTH=90:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=90:B_WIDTH=90:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=90:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=90:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=90:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=91:B_WIDTH=91:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=91:B_WIDTH=91:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=91:B_WIDTH=91:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=91:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=91:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=91:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=92:B_WIDTH=92:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=92:B_WIDTH=92:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=92:B_WIDTH=92:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=92:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=92:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=92:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=93:B_WIDTH=93:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=93:B_WIDTH=93:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=93:B_WIDTH=93:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=93:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=93:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=93:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=94:B_WIDTH=94:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=94:B_WIDTH=94:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=94:B_WIDTH=94:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=94:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=94:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=94:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=95:B_WIDTH=95:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=95:B_WIDTH=95:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=95:B_WIDTH=95:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=95:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=95:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=95:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=96:B_WIDTH=96:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=96:B_WIDTH=96:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=96:B_WIDTH=96:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=96:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=96:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=96:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=97:B_WIDTH=97:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=97:B_WIDTH=97:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=97:B_WIDTH=97:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=97:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=97:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=97:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=98:B_WIDTH=98:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=98:B_WIDTH=98:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=98:B_WIDTH=98:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=98:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=98:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=98:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=99:B_WIDTH=99:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=99:B_WIDTH=99:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=99:B_WIDTH=99:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=99:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=99:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=99:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=100:B_WIDTH=100:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=100:B_WIDTH=100:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=100:B_WIDTH=100:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=100:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=100:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=100:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=101:B_WIDTH=101:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=101:B_WIDTH=101:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=101:B_WIDTH=101:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=101:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=101:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=101:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=102:B_WIDTH=102:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$sub:Y_WIDTH=102:B_WIDTH=102:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$sub:Y_WIDTH=102:B_WIDTH=102:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=102:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=102:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$ge:Y_WIDTH=1:B_WIDTH=102:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
Running "alumacc" on wrapper $extern:wrap:$sub:Y_WIDTH=103:B_WIDTH=103:A_WIDTH=64:B_SIGNED=0:A_SIGNED=0:394426c56d1a028ba8fdd5469b163e04011def47.
