FCN Designer
Width (X)
Height (Y)
Resize Layout
Reset Layout
Reset Editor
Import Verilog
Import Layout
Export Layout
Export DOT Layout
Export QCA Layout
Export hexagonalized SiDB Layout
PI
PO
INV
BUF
Crossing
Crossing
AND
OR
NOR
XOR
XNOR
Connect
Move
Delete
Cancel
ortho
IO SDN
exact
Specify Exact Algorithm Parameters
Upper Bound X
Number of tiles to use as an upper bound in x direction.
Upper Bound Y
Number of tiles to use as an upper bound in y direction.
Fixed Size
No
Yes
Investigate only aspect ratios matching the upper bounds.
Number of Threads
Number of threads to use for exploring aspect ratios.
Crossings Allowed
No
Yes
Allow crossings in the layout.
Border IO
No
Yes
Place I/Os at the layout's border.
Straight Inverters
No
Yes
Use straight inverters over bend ones.
Desynchronize
No
Yes
Allow discrepancies in fan-in path lengths.
Minimize Wires
No
Yes
Minimize the number of wires used.
Minimize Crossings
No
Yes
Minimize the number of crossings used.
Timeout (ms)
Set a timeout in milliseconds for the solving process.
gold
Specify Gold Parameters
Return Layout Option
Return Best Found Layout
Return First Found Layout
Effort Mode
High Efficiency
High Effort
Highest Effort
Timeout (ms)
Specify the maximum time in milliseconds before the process times out. Available range: 1-10000.
Number of Vertex Expansions
Define how many vertices can be expanded during the layout design. Available range: 1-100.
Planarity
Permit Crossings
Fully Planar
Cost
Layout Area
Number of Wires
Number of Crossings
Area-Crossing Product
Choose the primary metric for evaluating layout costs.
Enable Multithreading
Enable multi-threading to improve performance on multi-core processors.
Optimize Layout
Specify Optimization Parameters
Max Gate Relocations
Max
Custom
Enter Custom Number of Relocations
Specify a custom number of gate relocations. Leave as 0 for wiring reduction only.
Optimize Gate Positions
All Gates
POs only
Choose which gate positions should be optimized.
Planarity
Enable Crossings
Reduce Crossings/ Keep Planarity
Enable planar optimization to ensure that no new crossings are created and planar layouts stay planar.
Timeout (ms)
Specify the maximum time in milliseconds before the optimization process times out. Available range: 1-10000.
Check Design Rules
Check Equivalence
Please create a layout to get started.
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Design Rule Violations:
Equivalence: