dmcontrol

This bit controls the reset signal from the DM to the rest of the system.

The signal should reset every part of the system, including every hart, except for the DM and any logic required to access the DM.

To perform a system reset the debugger writes 1, and then writes 0 to deassert the reset.

This bit serves as a reset signal for the Debug Module itself.

• 0: The module's state, including authentication mechanism, takes its reset values (the dmactive bit is the only bit which can be written to something other than its reset value).
• 1: The module functions normally. No other mechanism should exist that may result in resetting the Debug Module after power up, with the possible (but not recommended) exception of a global reset signal that resets the entire platform.

A debugger may pulse this bit low to get the Debug Module into a known state.

Implementations may pay attention to this bit to further aid debugging, for example by preventing the Debug Module from being power gated while debugging is active.