// Generated for: spectre
// Generated on: Apr 28 17:49:09 2019
// Design library name: DC_converter
// Design cell name: 2019_04_28_comparator_testbench
// Design view name: schematic
simulator lang=spectre
global 0

// Library name: DC_converter
// Cell name: 23Dec_2017_comparator_symbol
// View name: schematic
subckt DC_converter_23Dec_2017_comparator_symbol_schematic Vn Vout Vp Vdd \
        cgnd
    M21 (net44 cgnd Vdd Vdd) pmos l=1.32u w=120.0n m=1 nf=1
       
       
    M5 (net10 Vn net7 cgnd) nmos lr=120.0n wr=600n nr=1 sigma=1 m=1
       
    M0 (net5 Vp net7 cgnd) nmos lr=120.0n wr=600n nr=1 sigma=1 m=1
       
    M11 (net7 net44 cgnd cgnd) nmos lr=120.0n wr=1.2u nr=1 sigma=1 m=1
       
    M9 (net44 net44 cgnd cgnd) nmos lr=120.0n wr=600n nr=1 sigma=1 m=1
       
    M10 (Vop Von net18 cgnd) nmos lr=120.0n wr=600n nr=1 sigma=1 m=1
       
    M8 (Von Vop net18 cgnd) nmos lr=120.0n wr=600n nr=1 sigma=1 m=1
       
    M7 (Von Von net18 cgnd) nmos lr=120.0n wr=600n nr=1 sigma=1 m=1
       
    M6 (Vop Vop net18 cgnd) nmos lr=120.0n wr=600n nr=1 sigma=1 m=1
       
    M20 (net18 net18 cgnd cgnd) nmos lr=120.0n wr=6u nr=1 sigma=1 m=1
       
    M18 (net17 net13 cgnd cgnd) nmos lr=120.0n wr=600n nr=1 sigma=1 m=1
       
    M16 (Vout net23 cgnd cgnd) nmos lr=120.0n wr=600n nr=1 sigma=1 m=1
       
    M14 (net23 Vop net17 cgnd) nmos lr=120.0n wr=600n nr=1 sigma=1 m=1
       
    M12 (net13 Von net17 cgnd) nmos lr=120.0n wr=600n nr=1 sigma=1 m=1
       
    M3 (Vop net5 Vdd Vdd) pmos lr=240.0n wr=1.8u nr=1 sigma=1 m=1
       
    M2 (net5 net5 Vdd Vdd) pmos lr=240.0n wr=1.8u nr=1 sigma=1 m=1
       
    M4 (Von net10 Vdd Vdd) pmos lr=240.0n wr=1.8u nr=1 sigma=1 m=1
       
    M1 (net10 net10 Vdd Vdd) pmos lr=240.0n wr=1.8u nr=1 sigma=1 m=1
       
    M19 (net14 net13 Vdd Vdd) pmos lr=120.0n wr=900n nr=1 sigma=1 m=1
       
    M17 (Vout net23 Vdd Vdd) pmos lr=120.0n wr=900n nr=1 sigma=1 m=1
       
    M15 (net23 Vop net14 net14) pmos lr=120.0n wr=900n nr=1 sigma=1 m=1
       
    M13 (net13 Von net14 net14) pmos lr=120.0n wr=900n nr=1 sigma=1 m=1
       
ends DC_converter_23Dec_2017_comparator_symbol_schematic
// End of subcircuit definition.

// Library name: DC_converter
// Cell name: 2019_04_28_comparator_testbench
// View name: schematic
I0 (vn vout vp vdd vss) DC_converter_23Dec_2017_comparator_symbol_schematic
V3 (vss 0) vsource dc=0 type=dc
V2 (vp 0) vsource dc=500m type=dc
V0 (vdd 0) vsource dc=1 type=dc
V1 (vn 0) vsource dc=500m type=sine ampl=500m freq=100M

