// Generated for: spectre
// Generated on: Nov  2 11:59:19 2018
// Design library name: DC_converter
// Design cell name:
//2018_11_2_fully_diff_cascoded_current_mirror_ota_symbol_database
// Design view name: schematic
global 0 vdd!

// Library name: DC_converter
// Cell name:
//2018_11_2_fully_diff_cascoded_current_mirror_ota_symbol_database
// View name: schematic
M15 (net020 Vbiasp net021 net021) pmos l=130.0n w=3u m=1 nf=1 
M14 (net010 Vbiasp net013 net013) pmos l=130.0n w=3u m=1 nf=1 
M5 (Voutn Vbiasp net6 net6) pmos l=200n w=12.305u m=1 nf=1 
M4 (net6 net010 vdd! vdd!) pmos l=200n w=10.77u m=1 nf=1 
M3 (Voutp Vbiasp net23 net23) pmos l=200n w=12.305u m=1 nf=1 
M2 (net23 net020 vdd! vdd!) pmos l=200n w=10.77u m=1 nf=1 
M1 (net021 net020 vdd! vdd!) pmos l=130.0n w=4.25u m=1 nf=1 
M0 (net013 net010 vdd! vdd!) pmos l=130.0n w=4.25u m=1 nf=1 
M13 (net11 net11 0 0) nmos l=130.0n w=2u m=1 nf=1 
M12 (net17 net11 0 0) nmos l=130.0n w=2u m=1 nf=1 
M11 (Voutp Vbiasn net38 0) nmos l=200n w=10.9u m=1 nf=1 
M10 (net38 Vbiasnd 0 0) nmos l=300n w=11.5u m=1 nf=1 
M9 (Voutn Vbiasn net39 0) nmos l=200n w=10.9u m=1 nf=1 
M8 (net39 Vbiasnd 0 0) nmos l=300n w=11.5u m=1 nf=1 
M7 (net020 Vinp net17 0) nmos l=130.0n w=3.56u m=1 nf=1 
M6 (net010 Vinn net17 0) nmos l=130.0n w=3.56u m=1 nf=1 
I4 (vdd! net11) isource dc=200u type=dc
V2 (Vbiascmfb 0) vsource dc=449m type=dc
V1 (Vbiasn 0) vsource dc=700m type=dc
V0 (Vbiasp 0) vsource dc=410m type=dc
C1 (Voutp Vbiasnd) capacitor c=10f
C0 (Voutn Vbiasnd) capacitor c=10f

