{
  "path": "EXAMPLES/adder.sv",
  "modules": [
    {
      "name": "adder",
      "params": [
        {
          "ptype": "integer",
          "name": "DATA_WIDTH",
          "default": "8",
          "comment": [
            "Width of input operands"
          ]
        },
        {
          "ptype": "integer",
          "name": "OUTPUT_WIDTH",
          "default": "4",
          "comment": [
            "Test configuration value"
          ]
        }
      ],
      "ports": [
        {
          "direction": "input",
          "ptype": "logic",
          "dtype": "unsigned",
          "name": "A",
          "dim": "[DATA_WIDTH-1:0]",
          "comment": [
            "Packed input operand A"
          ]
        },
        {
          "direction": "input",
          "ptype": "logic",
          "dtype": "unsigned",
          "name": "B",
          "dim": "[DATA_WIDTH-1:0]",
          "comment": [
            "Packed input operand B"
          ]
        },
        {
          "direction": "output",
          "ptype": "logic",
          "dtype": "unsigned",
          "name": "X",
          "dim": "[DATA_WIDTH:0]",
          "comment": [
            "Packed sum output"
          ]
        },
        {
          "direction": "input",
          "ptype": "logic",
          "name": "byte_p",
          "dim": "[7:0]",
          "comment": [
            "Packed byte input"
          ]
        },
        {
          "direction": "input",
          "ptype": "logic",
          "name": "word_p",
          "dim": "[3:0][7:0]",
          "comment": [
            "Packed 32-bit word (4 bytes)"
          ]
        },
        {
          "direction": "input",
          "ptype": "logic",
          "name": "flag_u",
          "comment": [
            "Unpacked single bit"
          ]
        },
        {
          "direction": "input",
          "ptype": "logic",
          "name": "arr_u",
          "dim": "[7:0]",
          "dim_unpacked": "[0:3]",
          "comment": [
            "Unpacked byte array"
          ]
        }
      ],
      "insts": [
        {
          "name": "u_test_module",
          "module": "test_module",
          "connections": [
            {
              "port": "test_input",
              "con": "a_port",
              "comment": [
                "Connected to a_port"
              ]
            },
            {
              "port": "test_output",
              "con": "b_port",
              "comment": [
                "Connected to b_port"
              ]
            }
          ]
        }
      ]
    }
  ]
}
{
  "path": "EXAMPLES/instances_example.sv",
  "modules": [
    {
      "name": "top1",
      "ports": [
        {
          "direction": "input",
          "name": "clk"
        },
        {
          "direction": "input",
          "name": "rst_n"
        },
        {
          "direction": "input",
          "name": "enable"
        },
        {
          "direction": "input",
          "name": "data_rx_1",
          "dim": "[9:0]"
        },
        {
          "direction": "input",
          "name": "data_rx_2",
          "dim": "[9:0]"
        },
        {
          "direction": "output",
          "name": "data_tx_2",
          "dim": "[9:0]"
        }
      ],
      "insts": [
        {
          "name": "subcomponent_instance_name",
          "module": "subcomponent",
          "connections": [
            {
              "port": "clk",
              "con": "clk"
            },
            {
              "port": "rst_n",
              "con": "rst_n"
            },
            {
              "port": "data_rx",
              "con": "data_rx_1"
            },
            {
              "port": "data_tx",
              "con": "data_tx"
            }
          ]
        }
      ]
    },
    {
      "name": "top2",
      "ports": [
        {
          "direction": "input",
          "name": "clk"
        },
        {
          "direction": "input",
          "name": "rst_n"
        },
        {
          "direction": "input",
          "name": "enable"
        },
        {
          "direction": "input",
          "name": "data_rx_1",
          "dim": "[9:0]"
        },
        {
          "direction": "input",
          "name": "data_rx_2",
          "dim": "[9:0]"
        },
        {
          "direction": "output",
          "name": "data_tx_2",
          "dim": "[9:0]"
        }
      ],
      "insts": [
        {
          "name": "subcomponent_instance_name",
          "module": "subcomponent",
          "connections": [
            {
              "port": "clk",
              "con": "clk",
              "comment": [
                "input"
              ]
            },
            {
              "port": "rst_n",
              "con": "rst_n_bar",
              "comment": [
                "input"
              ],
              "ifdefs": [
                "BAR"
              ]
            },
            {
              "port": "rst_n",
              "con": "rst_n_else",
              "comment": [
                "input"
              ],
              "ifdefs": [
                "!BAR"
              ]
            },
            {
              "port": "data_rx",
              "con": "data_rx_1",
              "comment": [
                "input  [9:0]"
              ]
            },
            {
              "port": "data_tx",
              "con": "data_tx",
              "comment": [
                "output [9:0]"
              ]
            }
          ]
        }
      ]
    },
    {
      "name": "top3",
      "ports": [
        {
          "direction": "input",
          "name": "clk"
        },
        {
          "direction": "input",
          "name": "rst_n"
        },
        {
          "direction": "input",
          "name": "enable"
        },
        {
          "direction": "input",
          "name": "data_rx_1",
          "dim": "[9:0]"
        },
        {
          "direction": "input",
          "name": "data_rx_2",
          "dim": "[9:0]"
        },
        {
          "direction": "output",
          "name": "data_tx_2",
          "dim": "[9:0]"
        }
      ],
      "insts": [
        {
          "name": "subcomponent_instance_name",
          "module": "subcomponent",
          "connections": [
            {
              "port": "clk",
              "con": "clk",
              "comment": [
                "input **Auto connect**"
              ]
            },
            {
              "port": "rst_n",
              "con": "rst_n",
              "comment": [
                "input **Auto connect**"
              ]
            },
            {
              "port": "data_rx",
              "con": "data_rx_1",
              "comment": [
                "input  [9:0]"
              ]
            },
            {
              "port": "data_tx",
              "con": "data_tx",
              "comment": [
                "output [9:0]"
              ]
            }
          ]
        }
      ]
    },
    {
      "name": "top4",
      "ports": [
        {
          "direction": "input",
          "name": "clk"
        },
        {
          "direction": "input",
          "name": "rst_n"
        },
        {
          "direction": "input",
          "name": "enable"
        },
        {
          "direction": "input",
          "name": "data_rx_1",
          "dim": "[9:0]"
        },
        {
          "direction": "input",
          "name": "data_rx_2",
          "dim": "[9:0]"
        },
        {
          "direction": "output",
          "name": "data_tx_2",
          "dim": "[9:0]"
        }
      ],
      "insts": [
        {
          "name": "subcomponent_instance_name",
          "module": "subcomponent",
          "connections": [
            {
              "port": "data_rx",
              "con": "data_rx_1",
              "comment": [
                "input  [9:0]"
              ]
            },
            {
              "port": "data_tx",
              "con": "data_tx",
              "comment": [
                "output [9:0]"
              ]
            }
          ]
        }
      ]
    },
    {
      "name": "top0",
      "ports": [
        {
          "direction": "input",
          "name": "clk"
        },
        {
          "direction": "input",
          "name": "rst_n"
        },
        {
          "direction": "input",
          "name": "enable"
        },
        {
          "direction": "input",
          "name": "data_rx_1",
          "dim": "[9:0]"
        },
        {
          "direction": "input",
          "name": "data_rx_2",
          "dim": "[9:0]"
        },
        {
          "direction": "output",
          "name": "data_tx_2",
          "dim": "[9:0]"
        }
      ],
      "insts": [
        {
          "name": "subcomponent_instance_name",
          "module": "subcomponent",
          "connections": [
            {
              "con": "clk,",
              "ifdefs": [
                "SYNTHESIS"
              ]
            },
            {
              "con": "rst_n,",
              "ifdefs": [
                "SYNTHESIS"
              ]
            },
            {
              "con": "data_rx_1,",
              "ifdefs": [
                "SYNTHESIS"
              ]
            },
            {
              "con": "data_tx ",
              "ifdefs": [
                "SYNTHESIS"
              ]
            }
          ],
          "ifdefs": [
            "SYNTHESIS"
          ]
        }
      ]
    }
  ]
}
{
  "path": "EXAMPLES/packed_unpacked.sv",
  "modules": [
    {
      "name": "packed_unpacked",
      "params": [
        {
          "name": "P_VEC",
          "dim": "[4:0]",
          "default": "0"
        },
        {
          "name": "P_MATRIX",
          "dim": "[4:0][3:0]",
          "default": "0"
        },
        {
          "name": "P_UNPACK",
          "dim_unpacked": "[4:0]",
          "default": "0"
        },
        {
          "name": "P_VEC_UNPACK",
          "dim": "[3:0]",
          "dim_unpacked": "[4:0]",
          "default": "0"
        }
      ],
      "ports": [
        {
          "direction": "input",
          "name": "vec_i",
          "dim": "[4:0]"
        },
        {
          "direction": "input",
          "name": "matrix_i",
          "dim": "[4:0][3:0]"
        },
        {
          "direction": "input",
          "name": "unpack_i",
          "dim_unpacked": "[4:0]"
        },
        {
          "direction": "input",
          "name": "vec_unpack_i",
          "dim": "[3:0]",
          "dim_unpacked": "[4:0]"
        },
        {
          "direction": "output",
          "name": "out_o"
        }
      ]
    }
  ]
}
{
  "path": "EXAMPLES/bcd_adder.sv",
  "modules": [
    {
      "name": "bcd_adder",
      "ports": [
        {
          "direction": "input",
          "name": "a",
          "dim": "[3:0]"
        },
        {
          "direction": "input",
          "name": "b",
          "dim": "[3:0]"
        },
        {
          "direction": "input",
          "name": "cin"
        },
        {
          "direction": "output",
          "name": "sum",
          "dim": "[3:0]"
        },
        {
          "direction": "output",
          "name": "cout"
        }
      ]
    },
    {
      "name": "tb_bcdadder",
      "insts": [
        {
          "name": "uut",
          "module": "bcd_adder",
          "connections": [
            {
              "port": "a",
              "con": "a"
            },
            {
              "port": "b",
              "con": "b"
            },
            {
              "port": "cin",
              "con": "cin"
            },
            {
              "port": "sum",
              "con": "sum"
            },
            {
              "port": "cout",
              "con": "cout"
            }
          ]
        }
      ]
    }
  ]
}
