{% extends 'base.html' %} {% block title %}Generate Outputs{% endblock %} {% block head %} {% endblock %} {% block content %}

Generate Outputs

Produce VHDL modules, documentation, and header files from your design.

Configuration
Destination folder for all generated files.
Axi-Lite wrappers
IP-XACT compatible
Human-readable config
Machine-readable specs
Driver definitions
Register map (.md)
Styled web page (.html)
{% from 'components/activity_log.html' import activity_log %} {{ activity_log(id="consoleOutput", height="400px", title="Activity Log", subtitle="Idle", placeholder="Ready to generate...") }}
{% endblock %}