Metadata-Version: 2.4
Name: aurig-sentinel
Version: 0.1.0
Summary: Automated FPGA/VHDL build pipeline with regression testing and synthesis
Project-URL: Homepage, https://github.com/aurig-fpga/aurig-sentinel
Project-URL: Repository, https://github.com/aurig-fpga/aurig-sentinel
Project-URL: Issues, https://github.com/aurig-fpga/aurig-sentinel/issues
Project-URL: Changelog, https://github.com/aurig-fpga/aurig-sentinel/blob/main/CHANGELOG.md
Author-email: Andrea Campera <a.campera@logimentor.com>
License-Expression: Apache-2.0
License-File: LICENSE
Classifier: Development Status :: 3 - Alpha
Classifier: Intended Audience :: Developers
Classifier: Programming Language :: Python :: 3
Classifier: Programming Language :: Python :: 3.9
Classifier: Programming Language :: Python :: 3.11
Classifier: Programming Language :: Python :: 3.12
Classifier: Programming Language :: Python :: 3.13
Classifier: Topic :: Software Development :: Build Tools
Requires-Python: >=3.9
Requires-Dist: gitpython>=3.1.40
Requires-Dist: pyyaml>=6.0
Provides-Extra: regression
Requires-Dist: vunit-hdl>=4.0; extra == 'regression'
Provides-Extra: test
Requires-Dist: pytest>=7; extra == 'test'
