Metadata-Version: 2.2
Name: HDLconv
Version: 0.1.1
Summary: HDL converter, based on GHDL, Yosys, and the plugins ghdl-yosys-plugin and yosys-slang
Home-page: https://github.com/PyFPGA/HDLconv
Author: Rodrigo A. Melo
Author-email: rodrigomelo9@gmail.com
License: GPLv3
Classifier: Development Status :: 3 - Alpha
Classifier: Environment :: Console
Classifier: Intended Audience :: Developers
Classifier: License :: OSI Approved :: GNU General Public License v3 (GPLv3)
Classifier: Operating System :: OS Independent
Classifier: Programming Language :: Python :: 3.8
Classifier: Programming Language :: Python :: 3.9
Classifier: Programming Language :: Python :: 3.10
Classifier: Programming Language :: Python :: 3.11
Classifier: Programming Language :: Python :: 3.12
Classifier: Topic :: Utilities
Classifier: Topic :: Software Development :: Build Tools
Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
Description-Content-Type: text/markdown
License-File: LICENSE
Requires-Dist: jinja2
Dynamic: author
Dynamic: author-email
Dynamic: classifier
Dynamic: description
Dynamic: description-content-type
Dynamic: home-page
Dynamic: license
Dynamic: requires-dist
Dynamic: summary

# HDLconv

HDL converter (between VHDL, SystemVerilog and/or Verilog), based on [GHDL](https://github.com/ghdl/ghdl), [Yosys](https://github.com/YosysHQ/yosys), [Synlig](https://github.com/chipsalliance/synlig) and the plugins [ghdl-yosys-plugin](https://github.com/ghdl/ghdl-yosys-plugin) and [yosys-slang](https://github.com/povik/yosys-slang).
It relies on [Docker](https://docs.docker.com/get-docker) and [PyFPGA containers](https://github.com/PyFPGA/containers).

> Known limitation: the files must be located either under the `$HOME` directory or under the current working directory (`$PWD`) for Docker to be able to find and access them.

* `vhdl2vhdl`: converts from a newer VHDL to VHDL'93 (using `ghdl`).
* `vhdl2vlog`: converts from VHDL to Verilog (backends: `ghdl` or `yosys`).
* `slog2vlog`: converts from SystemVerilog to Verilog (frontends: `slang`, `synlig` or `yosys`).

# Documentation

```
usage: vhdl2vhdl [-h] [-v] [-g GENERIC VALUE] [-a ARCH] [-f FILENAME]
                 [-o PATH] -t TOPNAME
                 FILE[,LIBRARY] [FILE[,LIBRARY] ...]

VHDL to VHDL

positional arguments:
  FILE[,LIBRARY]        VHDL file/s (with an optional LIBRARY specification)

optional arguments:
  -h, --help            show this help message and exit
  -v, --version         show program's version number and exit
  -g GENERIC VALUE, --generic GENERIC VALUE
                        specify a top-level Generic (can be specified multiple
                        times)
  -a ARCH, --arch ARCH  specify a top-level Architecture
  -f FILENAME, --filename FILENAME
                        resulting file name [<TOPNAME>.<EXT>]
  -o PATH, --odir PATH  output directory [results]
  -t TOPNAME, --top TOPNAME
                        specify the top-level of the design
```

```
usage: vhdl2vlog [-h] [-v] [--backend TOOL] [-g GENERIC VALUE] [-a ARCH]
                 [-f FILENAME] [-o PATH] -t TOPNAME
                 FILE[,LIBRARY] [FILE[,LIBRARY] ...]

VHDL to Verilog

positional arguments:
  FILE[,LIBRARY]        VHDL file/s (with an optional LIBRARY specification)

optional arguments:
  -h, --help            show this help message and exit
  -v, --version         show program's version number and exit
  --backend TOOL        backend tool [ghdl]
  -g GENERIC VALUE, --generic GENERIC VALUE
                        specify a top-level Generic (can be specified multiple
                        times)
  -a ARCH, --arch ARCH  specify a top-level Architecture
  -f FILENAME, --filename FILENAME
                        resulting file name [<TOPNAME>.<EXT>]
  -o PATH, --odir PATH  output directory [results]
  -t TOPNAME, --top TOPNAME
                        specify the top-level of the design
```

```
usage: slog2vlog [-h] [-v] [--frontend TOOL] [-p PARAM VALUE]
                 [-d DEFINE VALUE] [-i PATH] [-f FILENAME] [-o PATH] -t
                 TOPNAME
                 FILE [FILE ...]

SystemVerilog to Verilog

positional arguments:
  FILE                  System Verilog file/s

optional arguments:
  -h, --help            show this help message and exit
  -v, --version         show program's version number and exit
  --frontend TOOL       frontend tool [slang]
  -p PARAM VALUE, --param PARAM VALUE
                        specify a top-level Parameter (can be specified
                        multiple times)
  -d DEFINE VALUE, --define DEFINE VALUE
                        specify a Define (can be specified multiple times)
  -i PATH, --include PATH
                        specify an Include Path (can be specified multiple
                        times)
  -f FILENAME, --filename FILENAME
                        resulting file name [<TOPNAME>.<EXT>]
  -o PATH, --odir PATH  output directory [results]
  -t TOPNAME, --top TOPNAME
                        specify the top-level of the design
```
