/target
crates/*/target/
crates/*/Cargo.lock
/book
/compile_commands.json
.cache

# Python
__pycache__/
*.pyc
*.swp
.pdm-python

# macOS Finder metadata
**/.DS_Store

# Claude Code session data
.claude/

# tldr local cache + ignore config
.tldr/
.tldrignore

# Simulation artifacts
*.vvp
*.vcd
# Committed cosim regression goldens (CpuBackend CI diffs against these).
!tests/xprop_cosim/expected/*.vcd
# Stage C flash cosim golden (mcu_soc; CpuBackend == Metal, #105).
!tests/mcu_soc/expected/*.vcd
*.tar.gz
debug_trace.csv
*_watchlist.json
api_artifacts/
tb_verify_sim

# Binary timing IR. Commit JSON dumps (e.g. via timing-ir-diff's
# pretty-printed output) instead — *.jtir.json is intentionally not
# ignored so those can be checked in.
*.jtir
# WS4 corpus goldens are the deliberate exception — the .jtir is the
# canonical binary the regression test diffs against; the .json sidecar
# is for PR-time review. Both ship.
!tests/timing_ir/corpus/**/*.jtir
# Pre-generated timing IR for CI (Metal runner lacks OpenSTA + Liberty)
!tests/timing_test/inv_chain_pnr/inv_chain.jtir

# Build output directories
**/build/results/

# ChipFlow design build artifacts
designs/*/build/
designs/*/.doit.db

# Test build artifacts (binary firmware, netlists)
tests/*/build/

# uv lock file
uv.lock

# IP fetched via cf-ipm at build time
/ip/
