[globcfg]
base_address = 0
data_width = 32
address_width = 10
register_reset = sync_neg
address_increment = data_width
address_alignment = data_width
force_name_case = none
regmap_path = xibif-regs.json

[vhdl]
read_filler = 0
interface = axil
generator = vhdl
path = ../src/XiBIF_regs.vhd

[py]
path = ../../sw/regs.py
generator = Python

[doc]
path = ../../doc/registers/xibif_regs.md
title = Register map
print_images = True
image_dir = md_img
print_conventions = True
generator = Markdown

[c_header]
prefix = XIBIF_REG
add_json = True
generator = CHeader
path = ../vitis/xibif/src/XiBIF_regs.h