[globcfg]
base_address = 0
data_width = 32
address_width = 10
register_reset = sync_neg
address_increment = data_width
address_alignment = data_width
force_name_case = none
regmap_path = xibif-stream.json

[vhdl]
path = ../src/XiBIF_stream_regs.vhd
read_filler = 0
interface = axil
generator = Vhdl

[c_header]
path = ../vitis/xibif/src/XiBIF_stream_regs.h
prefix = XIBIF_SREG
generator = CHeader

[vhdl_package]
path = ../tb/tb_stream_regs_package.vhd
module_name = XiBIF_stream_regs
generator = VhdlPackage