Metadata-Version: 2.4
Name: simplhdl
Version: 0.11.0
Summary: A framework for simulating and implementing HDL designs
Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
License: MIT License
        
        Copyright (c) 2024 SimplHDL
        
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Project-URL: Documentation, https://simplhdl.readthedocs.io/en/latest/
Project-URL: Homepage, https://github.com/SimplHDL
Project-URL: Issues, https://github.com/SimplHDL/simplhdl/issues
Project-URL: Repository, https://github.com/SimplHDL/simplhdl.git
Classifier: Development Status :: 4 - Beta
Classifier: Intended Audience :: Developers
Classifier: License :: OSI Approved :: MIT License
Classifier: Operating System :: OS Independent
Classifier: Programming Language :: Python :: 3 :: Only
Classifier: Programming Language :: Python :: 3.8
Classifier: Programming Language :: Python :: 3.9
Classifier: Programming Language :: Python :: 3.10
Classifier: Programming Language :: Python :: 3.11
Classifier: Programming Language :: Python :: 3.12
Classifier: Programming Language :: Python :: 3.13
Classifier: Programming Language :: Python :: 3.14
Requires-Python: >=3.8
Description-Content-Type: text/markdown
License-File: LICENSE
Requires-Dist: argcomplete
Requires-Dist: black
Requires-Dist: flake8
Requires-Dist: gitpython
Requires-Dist: importlib-resources; python_version < "3.9"
Requires-Dist: jinja2
Requires-Dist: matplotlib
Requires-Dist: networkx
Requires-Dist: peakrdl-html
Requires-Dist: peakrdl-pyuvm
Requires-Dist: peakrdl-regblock>=1.2
Requires-Dist: pyyaml
Requires-Dist: rich
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Requires-Dist: systemrdl-compiler
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Provides-Extra: docs
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Requires-Dist: sphinx-pyproject; extra == "docs"
Dynamic: license-file

## Introduction

SimplHDL is a plugin-based command-line application for simplifying FPGA and ASIC development regardless of EDA tools
and flows.

The goal is to embrase structured and reusable designs by creating a generic project model that can be used in any hdl
development flow regardless of project structure and EDA tool requirements.

The plugin based architecture allows for SimplHDL to be migrated into any existing project, replacing ad-hoc simulation
and implementation scripts while providing a intuitive command-line interface for HDL design and verification engineers.

I wide vararity of languages, standards and tools are supported.

### HDL languages

- Verilog / System Verilog
- VHDL
- Chisel
- SystemRDL
- IPXact
- Vivado IP containers (.xci, .xcix)
- Quartus IP containers (.ip)

### Methodologies

- UVM
- OSVMM
- UVVM
- Cocotb
- pyuvm

### EDA Tools

- Vivado
- Quartus
- Modelsim
- Questasim
- Xsim
- Vcs
- Riviera Pro
- Xcelium (coming)
- Verilator (coming)
- Icarus (coming)
- GHDL (coming)

## Getting Started

SimplHDL currently works on Linux and Windows WSL. It is written in Python and can be installed with _pip_. To run
SimplHDL Python 3.8 or later is required. The tools for the flows you wish to run also need to be installed and set up
correctly in the shell environment. SimplHDL can be installed on your system's Python installation, but it is highly
recommended to install and run SimplHDL in a Python virtual environment or a Conda environment.

## Example

To quickly try out SimplHDL follow these steps. In this example, we will use Vivado and QuestaSim. The prerequisites are
that SimplHDL install installed and Vivado and QuestaSim are correctly set up in your shell environment.

1. Clone Git repository from GitHub

```console
git clone https://github.com/SimplHDL/simplhdl.git
```

2. install SimplHDL from source

```console
pip install ./simplhdl
```

3. Run simulation

```console
cd simplhdl/examples/hdl/alu/sim
simpl questasim
```

4. Run simulation interactively in Gui.

```console
cd simplhdl/examples/hdl/alu/sim
simpl questasim --gui
```

5. Run implementation

```console
cd ../syn
simpl vivado
```

6. Run implementation interactively in Gui.

```console
simpl vivado --gui
```

In this example, the project specification is written in Yaml. This format is only meant as a demonstration. To
integrate SimplHDL into your project, you have to write a parser plugin for your specific project specification format.
See the documentation and plugin examples for more information.

## Links

- Homepage:
- Source: <https://github.com/SimplHDL/simplhdl>
- Tracker: <https://github.com/SimplHDL/simplhdl/issues>
