.gitignore
.readthedocs.yaml
CONTRIBUTING.md
LICENSE
MANIFEST.in
MERGE_NOTES.md
README.md
hdl-src
pyproject.toml
.github/pull_request_template.md
.github/ISSUE_TEMPLATE/bug_report.md
.github/ISSUE_TEMPLATE/feature_request.md
.github/ISSUE_TEMPLATE/question.md
.github/workflows/build.yml
docs/Makefile
docs/api.rst
docs/architecture.rst
docs/conf.py
docs/configuring.rst
docs/faq.rst
docs/hwif.rst
docs/index.rst
docs/licensing.rst
docs/limitations.rst
docs/requirements.txt
docs/cpuif/apb.rst
docs/cpuif/avalon.rst
docs/cpuif/axi4lite.rst
docs/cpuif/customizing.rst
docs/cpuif/internal_protocol.rst
docs/cpuif/introduction.rst
docs/cpuif/obi.rst
docs/cpuif/passthrough.rst
docs/cpuif/wishbone.rst
docs/dev_notes/Alpha-Beta Versioning
docs/dev_notes/Hierarchy-and-Indexing
docs/dev_notes/Program Flow
docs/dev_notes/Resets
docs/dev_notes/Signal Dereferencer
docs/dev_notes/Validation Needed
docs/dev_notes/template-layers/1-port-declaration
docs/dev_notes/template-layers/1.1.hardware-interface
docs/dev_notes/template-layers/2-CPUIF
docs/dev_notes/template-layers/3-address-decode
docs/dev_notes/template-layers/4-fields
docs/dev_notes/template-layers/5-readback-mux
docs/dev_notes/template-layers/6-output-port-mapping
docs/diagrams/arch.png
docs/diagrams/diagrams.odg
docs/diagrams/rbuf.png
docs/diagrams/readback.png
docs/diagrams/rt-readback-fanin.drawio
docs/diagrams/rt-readback-fanin.png
docs/diagrams/wbuf.png
docs/img/err.svg
docs/img/ok.svg
docs/img/warn.svg
docs/props/addrmap.rst
docs/props/field.rst
docs/props/reg.rst
docs/props/rhs_props.rst
docs/props/signal.rst
docs/rdl_features/external.rst
docs/udps/extended_swacc.rst
docs/udps/fixedpoint.rst
docs/udps/intro.rst
docs/udps/read_buffering.rst
docs/udps/signed.rst
docs/udps/write_buffering.rst
src/peakrdl_regblock_vhdl/__about__.py
src/peakrdl_regblock_vhdl/__init__.py
src/peakrdl_regblock_vhdl/__peakrdl__.py
src/peakrdl_regblock_vhdl/addr_decode.py
src/peakrdl_regblock_vhdl/dereferencer.py
src/peakrdl_regblock_vhdl/exporter.py
src/peakrdl_regblock_vhdl/external_acks.py
src/peakrdl_regblock_vhdl/forloop_generator.py
src/peakrdl_regblock_vhdl/identifier_filter.py
src/peakrdl_regblock_vhdl/module_tmpl.vhd
src/peakrdl_regblock_vhdl/package_tmpl.vhd
src/peakrdl_regblock_vhdl/parity.py
src/peakrdl_regblock_vhdl/scan_design.py
src/peakrdl_regblock_vhdl/struct_generator.py
src/peakrdl_regblock_vhdl/utils.py
src/peakrdl_regblock_vhdl/validate_design.py
src/peakrdl_regblock_vhdl/vhdl_int.py
src/peakrdl_regblock_vhdl.egg-info/PKG-INFO
src/peakrdl_regblock_vhdl.egg-info/SOURCES.txt
src/peakrdl_regblock_vhdl.egg-info/dependency_links.txt
src/peakrdl_regblock_vhdl.egg-info/entry_points.txt
src/peakrdl_regblock_vhdl.egg-info/requires.txt
src/peakrdl_regblock_vhdl.egg-info/top_level.txt
src/peakrdl_regblock_vhdl/cpuif/__init__.py
src/peakrdl_regblock_vhdl/cpuif/base.py
src/peakrdl_regblock_vhdl/cpuif/apb3/__init__.py
src/peakrdl_regblock_vhdl/cpuif/apb3/apb3_tmpl.vhd
src/peakrdl_regblock_vhdl/cpuif/apb4/__init__.py
src/peakrdl_regblock_vhdl/cpuif/apb4/apb4_tmpl.vhd
src/peakrdl_regblock_vhdl/cpuif/avalon/__init__.py
src/peakrdl_regblock_vhdl/cpuif/avalon/avalon_tmpl.vhd
src/peakrdl_regblock_vhdl/cpuif/axi4lite/__init__.py
src/peakrdl_regblock_vhdl/cpuif/axi4lite/axi4lite_tmpl.vhd
src/peakrdl_regblock_vhdl/cpuif/obi/__init__.py
src/peakrdl_regblock_vhdl/cpuif/obi/obi_tmpl.vhd
src/peakrdl_regblock_vhdl/cpuif/passthrough/__init__.py
src/peakrdl_regblock_vhdl/cpuif/passthrough/passthrough_tmpl.vhd
src/peakrdl_regblock_vhdl/cpuif/wishbone/__init__.py
src/peakrdl_regblock_vhdl/cpuif/wishbone/wishbone_tmpl.vhd
src/peakrdl_regblock_vhdl/field_logic/__init__.py
src/peakrdl_regblock_vhdl/field_logic/bases.py
src/peakrdl_regblock_vhdl/field_logic/generators.py
src/peakrdl_regblock_vhdl/field_logic/hw_interrupts.py
src/peakrdl_regblock_vhdl/field_logic/hw_interrupts_with_write.py
src/peakrdl_regblock_vhdl/field_logic/hw_set_clr.py
src/peakrdl_regblock_vhdl/field_logic/hw_write.py
src/peakrdl_regblock_vhdl/field_logic/sw_onread.py
src/peakrdl_regblock_vhdl/field_logic/sw_onwrite.py
src/peakrdl_regblock_vhdl/field_logic/sw_singlepulse.py
src/peakrdl_regblock_vhdl/field_logic/templates/counter_macros_tmpl.vhd
src/peakrdl_regblock_vhdl/field_logic/templates/external_block_tmpl.vhd
src/peakrdl_regblock_vhdl/field_logic/templates/external_reg_tmpl.vhd
src/peakrdl_regblock_vhdl/field_logic/templates/field_storage_tmpl.vhd
src/peakrdl_regblock_vhdl/hdl_src/README.md
src/peakrdl_regblock_vhdl/hdl_src/apb3_intf_pkg.vhd
src/peakrdl_regblock_vhdl/hdl_src/apb4_intf_pkg.vhd
src/peakrdl_regblock_vhdl/hdl_src/avalon_mm_intf_pkg.vhd
src/peakrdl_regblock_vhdl/hdl_src/axi4lite_intf_pkg.vhd
src/peakrdl_regblock_vhdl/hdl_src/obi_intf_pkg.vhd
src/peakrdl_regblock_vhdl/hdl_src/reg_utils.vhd
src/peakrdl_regblock_vhdl/hdl_src/regblock_udps.rdl
src/peakrdl_regblock_vhdl/hdl_src/wishbone_intf_pkg.vhd
src/peakrdl_regblock_vhdl/hwif/__init__.py
src/peakrdl_regblock_vhdl/hwif/generators.py
src/peakrdl_regblock_vhdl/read_buffering/__init__.py
src/peakrdl_regblock_vhdl/read_buffering/implementation_generator.py
src/peakrdl_regblock_vhdl/read_buffering/template.vhd
src/peakrdl_regblock_vhdl/readback/__init__.py
src/peakrdl_regblock_vhdl/readback/readback.py
src/peakrdl_regblock_vhdl/readback/readback_mux_generator.py
src/peakrdl_regblock_vhdl/readback/templates/empty_readback_tmpl.vhd
src/peakrdl_regblock_vhdl/readback/templates/readback_no_rt_tmpl.vhd
src/peakrdl_regblock_vhdl/readback/templates/readback_tmpl.vhd
src/peakrdl_regblock_vhdl/readback/templates/readback_with_rt_tmpl.vhd
src/peakrdl_regblock_vhdl/udps/__init__.py
src/peakrdl_regblock_vhdl/udps/extended_swacc.py
src/peakrdl_regblock_vhdl/udps/fixedpoint.py
src/peakrdl_regblock_vhdl/udps/rw_buffering.py
src/peakrdl_regblock_vhdl/udps/signed.py
src/peakrdl_regblock_vhdl/write_buffering/__init__.py
src/peakrdl_regblock_vhdl/write_buffering/implementation_generator.py
src/peakrdl_regblock_vhdl/write_buffering/storage_generator.py
src/peakrdl_regblock_vhdl/write_buffering/template.vhd