# Allegro ASCII Export
# Generated by Cadence Allegro PCB Designer 17.4
# Date: 2025-06-15

$HEADER
UNITS = mm
VERSION = 17.4-2024
TITLE = "Allegro 4-Layer Test Board"
DESIGN = "Sample Allegro Design"
$END

$STACKUP
# LAYER_NAME TYPE THICKNESS MATERIAL Er LOSS_TAN CU_WEIGHT
TOP signal 0.035 Copper 1.0 0.0 1.0
PREPREG1 dielectric 0.2 FR4 4.5 0.02
GND plane 0.035 Copper 1.0 0.0 1.0
CORE1 dielectric 0.8 FR4 4.3 0.02
PWR plane 0.035 Copper 1.0 0.0 1.0
PREPREG2 dielectric 0.2 FR4 4.5 0.02
BOTTOM signal 0.035 Copper 1.0 0.0 1.0
$END

$NETS
GND; U1.GND U2.GND R1.2 R2.2 C1.2 C2.2 C3.2 J1.GND
VCC; U1.VCC U2.VCC C1.1 C2.1 C3.1 J1.VCC
USB_DP; U1.USB_DP J1.DP
USB_DN; U1.USB_DN J1.DN
CLK; U1.CLK U2.CLK R1.1
DATA0; U1.D0 U2.D0
DATA1; U1.D1 U2.D1
DATA2; U1.D2 U2.D2
DATA3; U1.D3 U2.D3
ADDR0; U1.A0 U2.A0
ADDR1; U1.A1 U2.A1
ADDR2; U1.A2 U2.A2
ADDR3; U1.A3 U2.A3
RESET; U1.RESET R3.1 C3.1
INT; U2.INT U1.INT R4.1
$END

$COMPONENTS
# REF FOOTPRINT X Y ROTATION SIDE VALUE PART_NUMBER
U1 BGA-256 50.0 40.0 0 TOP MCU STM32F407
U2 QFP-64 20.0 30.0 90 TOP FPGA XC7A35T
R1 0402 35.0 15.0 0 TOP 4.7k RC0402
R2 0402 38.0 15.0 0 TOP 10k RC0402
R3 0402 65.0 45.0 90 TOP 100k RC0402
R4 0402 68.0 45.0 90 TOP 1k RC0402
C1 0402 45.0 35.0 0 TOP 100nF CC0402
C2 0402 48.0 35.0 0 TOP 10uF CC0402
C3 0603 52.0 35.0 0 TOP 100uF CC0603
J1 USB-C 5.0 40.0 0 TOP USB-C USB3.1
$END

$PINS
# PIN_REF NET_NAME
U1.GND GND
U1.VCC VCC
U1.USB_DP USB_DP
U1.USB_DN USB_DN
U1.CLK CLK
U1.D0 DATA0
U1.D1 DATA1
U1.D2 DATA2
U1.D3 DATA3
U1.A0 ADDR0
U1.A1 ADDR1
U1.A2 ADDR2
U1.A3 ADDR3
U1.RESET RESET
U1.INT INT
U2.GND GND
U2.VCC VCC
U2.CLK CLK
U2.D0 DATA0
U2.D1 DATA1
U2.D2 DATA2
U2.D3 DATA3
U2.A0 ADDR0
U2.A1 ADDR1
U2.A2 ADDR2
U2.A3 ADDR3
U2.INT INT
R1.1 CLK
R1.2 GND
R2.2 GND
R3.1 RESET
R4.1 INT
C1.1 VCC
C1.2 GND
C2.1 VCC
C2.2 GND
C3.1 VCC
C3.2 GND
J1.GND GND
J1.VCC VCC
J1.DP USB_DP
J1.DN USB_DN
$END

$ROUTES
# LAYER WIDTH X1 Y1 X2 Y2 NET_NAME
TOP 0.15 5.0 41.0 25.0 41.0 USB_DP
TOP 0.15 5.0 39.0 25.0 39.0 USB_DN
TOP 0.15 25.0 41.0 50.0 41.0 USB_DP
TOP 0.15 25.0 39.0 50.0 39.0 USB_DN
TOP 0.2 35.0 15.0 50.0 30.0 CLK
TOP 0.2 20.0 30.0 50.0 30.0 CLK
TOP 0.12 50.0 35.0 20.0 25.0 DATA0
TOP 0.12 50.0 36.0 20.0 26.0 DATA1
TOP 0.12 50.0 37.0 20.0 27.0 DATA2
TOP 0.12 50.0 38.0 20.0 28.0 DATA3
BOTTOM 0.12 50.0 42.0 20.0 32.0 ADDR0
BOTTOM 0.12 50.0 43.0 20.0 33.0 ADDR1
BOTTOM 0.12 50.0 44.0 20.0 34.0 ADDR2
BOTTOM 0.12 50.0 45.0 20.0 35.0 ADDR3
TOP 0.25 45.0 35.0 50.0 40.0 VCC
TOP 0.25 48.0 35.0 50.0 40.0 VCC
BOTTOM 0.25 52.0 35.0 50.0 40.0 VCC
TOP 0.2 65.0 45.0 50.0 40.0 RESET
TOP 0.2 68.0 45.0 50.0 40.0 INT
BOTTOM 0.3 5.0 35.0 95.0 35.0 GND
$END

$VIAS
# X Y DRILL PAD_SIZE START_LAYER END_LAYER NET_NAME
25.0 41.0 0.3 0.6 TOP BOTTOM USB_DP
25.0 39.0 0.3 0.6 TOP BOTTOM USB_DN
50.0 30.0 0.3 0.6 TOP BOTTOM CLK
50.0 40.0 0.25 0.5 TOP GND VCC
50.0 40.5 0.25 0.5 TOP GND GND
52.0 35.0 0.3 0.6 TOP BOTTOM VCC
20.0 30.0 0.2 0.4 TOP BOTTOM GND
68.0 42.0 0.3 0.6 TOP BOTTOM INT
$END

$SHAPES
# Board outline vertices
BOARD_OUTLINE
0.0 0.0
100.0 0.0
100.0 80.0
0.0 80.0
END
$END

$CONSTRAINTS
# Design rules
MIN_TRACE_WIDTH = 0.1
MIN_SPACING = 0.1
MIN_DRILL = 0.2
$END
