Metadata-Version: 2.4
Name: uvm_tb_gen
Version: 0.1.4
Summary: An automation tool that generates complete UVM testbench infrastructure with dynamic configuration for interfaces, agents, environments, and tests.
Author: Vinay Kumar Kadirika
Keywords: UVM,SystemVerilog,Verification,VLSI,EDA,Testbench,Automation
Classifier: Programming Language :: Python :: 3
Classifier: Programming Language :: Python :: 3 :: Only
Classifier: Operating System :: POSIX :: Linux
Classifier: Topic :: Software Development :: Code Generators
Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
Classifier: Intended Audience :: Developers
Classifier: Intended Audience :: Science/Research
Requires-Python: >=3.8
Description-Content-Type: text/markdown

# UVM Testbench Generator (uvm-tb-gen)

`uvm-tb-gen` is a Python-based command-line tool that automates the generation of complete UVM (Universal Verification Methodology) testbench architectures.  
It is designed to reduce repetitive boilerplate work and help verification engineers quickly bootstrap scalable and maintainable UVM environments.

# Features

- Interactive CLI-driven configuration
- Automatic generation of:
  - Interfaces
  - Transactions
  - Sequencers
  - Drivers
  - Monitors
  - Agents
  - Environment (env, scoreboard, subscriber)
  - Tests and sequences
  - Top-level module
- Supports multiple agents and interfaces
- Enforces consistent naming conventions
- Generates simulator-ready `files.f` and Makefile
- Works across Linux environments (bash, csh, HPC systems)

# Installation

```bash
pip install uvm-tb-gen

