KAIROS GENERATE — Create verified RTL from an English specification

USAGE:
  kairos generate "<description>"
  kairos generate spec.txt

WHAT IT DOES:
  Takes a plain-English description of an RTL block and produces
  synthesizable Verilog. Multiple proposals are generated and verified
  through Yosys, so the output is guaranteed to elaborate cleanly.

EXAMPLES:
  kairos generate "4-stage pipelined ALU with forwarding"
  kairos generate "FIFO with configurable depth and width"
  kairos generate spec.txt --module my_alu --proposals 5

COMMON OPTIONS:
  --module NAME       Output module name (auto-derived if omitted)
  --output DIR        Output directory for generated files
  --proposals N       Number of RTL proposals to generate (default 3)

SEE ALSO:
  kairos doctor    Check your setup
  kairos helper    List all topics
