.flake8
.gitignore
LICENSE
README.md
pyproject.toml
.github/dependabot.yml
.github/workflows/lint.yml
.github/workflows/pages.yml
.github/workflows/regression.yml
.github/workflows/wheels.yml
dashboard/README.md
dashboard/build_db.py
dashboard/generate.py
dashboard/templates/dashboard.html.j2
examples/sc/.gitignore
examples/sc/gen_verilog_wrapper.py
examples/sc/make.py
examples/sc/synth_const.xdc
examples/sc/verilog_parsing_utils.py
examples/synthesis/make.py
examples/synthesis/vivado_template.j2
logikbench/__init__.py
logikbench/_version.py
logikbench/benchmark.py
logikbench.egg-info/PKG-INFO
logikbench.egg-info/SOURCES.txt
logikbench.egg-info/dependency_links.txt
logikbench.egg-info/entry_points.txt
logikbench.egg-info/requires.txt
logikbench.egg-info/top_level.txt
logikbench/apps/__init__.py
logikbench/apps/lb.py
logikbench/arithmetic/README.md
logikbench/arithmetic/__init__.py
logikbench/arithmetic/abs/abs.py
logikbench/arithmetic/abs/rtl/abs.v
logikbench/arithmetic/absdiff/absdiff.py
logikbench/arithmetic/absdiff/rtl/absdiff.v
logikbench/arithmetic/absdiffs/absdiffs.py
logikbench/arithmetic/absdiffs/rtl/absdiffs.v
logikbench/arithmetic/add/LICENSE
logikbench/arithmetic/add/README.md
logikbench/arithmetic/add/add.py
logikbench/arithmetic/add/constraint/add.sdc
logikbench/arithmetic/add/rtl/add.v
logikbench/arithmetic/addsub/addsub.py
logikbench/arithmetic/addsub/rtl/addsub.v
logikbench/arithmetic/cmp/cmp.py
logikbench/arithmetic/cmp/rtl/cmp.v
logikbench/arithmetic/counter/counter.py
logikbench/arithmetic/counter/rtl/counter.v
logikbench/arithmetic/csa32/csa32.py
logikbench/arithmetic/csa32/rtl/csa32.v
logikbench/arithmetic/csa42/csa42.py
logikbench/arithmetic/csa42/rtl/csa42.v
logikbench/arithmetic/dec/dec.py
logikbench/arithmetic/dec/rtl/dec.v
logikbench/arithmetic/dotprod/dotprod.py
logikbench/arithmetic/dotprod/rtl/dotprod.v
logikbench/arithmetic/inc/inc.py
logikbench/arithmetic/inc/rtl/inc.v
logikbench/arithmetic/log2/log2.py
logikbench/arithmetic/log2/rtl/log2.v
logikbench/arithmetic/mac/mac.py
logikbench/arithmetic/mac/rtl/mac.v
logikbench/arithmetic/max/max.py
logikbench/arithmetic/max/rtl/max.v
logikbench/arithmetic/min/min.py
logikbench/arithmetic/min/rtl/min.v
logikbench/arithmetic/mul/LICENSE
logikbench/arithmetic/mul/README.md
logikbench/arithmetic/mul/mul.py
logikbench/arithmetic/mul/rtl/mul.v
logikbench/arithmetic/mul/sdc/mul.sdc
logikbench/arithmetic/muladd/LICENSE
logikbench/arithmetic/muladd/README.md
logikbench/arithmetic/muladd/muladd.py
logikbench/arithmetic/muladd/rtl/muladd.v
logikbench/arithmetic/muladd/sdc/muladd.sdc
logikbench/arithmetic/muladdc/muladdc.py
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logikbench/arithmetic/mulc/mulc.py
logikbench/arithmetic/mulc/rtl/mulc.v
logikbench/arithmetic/mulreg/LICENSE
logikbench/arithmetic/mulreg/README.md
logikbench/arithmetic/mulreg/mulreg.py
logikbench/arithmetic/mulreg/rtl/mulreg.v
logikbench/arithmetic/mulreg/sdc/mul.sdc
logikbench/arithmetic/muls/LICENSE
logikbench/arithmetic/muls/README.md
logikbench/arithmetic/muls/muls.py
logikbench/arithmetic/muls/rtl/muls.v
logikbench/arithmetic/muls/sdc/muls.sdc
logikbench/arithmetic/relu/relu.py
logikbench/arithmetic/relu/rtl/relu.v
logikbench/arithmetic/round/round.py
logikbench/arithmetic/round/rtl/round.v
logikbench/arithmetic/shiftar/shiftar.py
logikbench/arithmetic/shiftar/rtl/shiftar.v
logikbench/arithmetic/shiftb/shiftb.py
logikbench/arithmetic/shiftb/rtl/shiftb.v
logikbench/arithmetic/shiftl/shiftl.py
logikbench/arithmetic/shiftl/rtl/shiftl.v
logikbench/arithmetic/shiftr/shiftr.py
logikbench/arithmetic/shiftr/rtl/shiftr.v
logikbench/arithmetic/sine/sine.py
logikbench/arithmetic/sine/rtl/sine.v
logikbench/arithmetic/sine/rtl/sine_table256.vh
logikbench/arithmetic/sqdiff/sqdiff.py
logikbench/arithmetic/sqdiff/rtl/sqdiff.v
logikbench/arithmetic/sqrt/sqrt.py
logikbench/arithmetic/sqrt/rtl/sqrt.v
logikbench/arithmetic/sub/sub.py
logikbench/arithmetic/sub/rtl/sub.v
logikbench/arithmetic/sum/sum.py
logikbench/arithmetic/sum/rtl/sum.v
logikbench/basic/README.md
logikbench/basic/__init__.py
logikbench/basic/arbfix/arbfix.py
logikbench/basic/arbfix/rtl/arbfix.v
logikbench/basic/arbfix/tb/tb.v
logikbench/basic/band/band.py
logikbench/basic/band/rtl/band.v
logikbench/basic/bbuf/bbuf.py
logikbench/basic/bbuf/rtl/bbuf.v
logikbench/basic/bin2gray/bin2gray.py
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logikbench/basic/bin2prio/bin2prio.py
logikbench/basic/bin2prio/rtl/bin2prio.v
logikbench/basic/bin2prio/tb/tb.v
logikbench/basic/binv/binv.py
logikbench/basic/binv/rtl/binv.v
logikbench/basic/bnand/bnand.py
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logikbench/basic/bnor/bnor.py
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logikbench/basic/bor/bor.py
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logikbench/basic/bxnor/bxnor.py
logikbench/basic/bxnor/rtl/bxnor.v
logikbench/basic/bxor/bxor.py
logikbench/basic/bxor/rtl/bxor.v
logikbench/basic/crossbar/crossbar.py
logikbench/basic/crossbar/rtl/crossbar.v
logikbench/basic/crossbar/tb/tb.v
logikbench/basic/dffasync/dffasync.py
logikbench/basic/dffasync/rtl/dffasync.v
logikbench/basic/dffsync/dffsync.py
logikbench/basic/dffsync/rtl/dffsync.v
logikbench/basic/gray2bin/gray2bin.py
logikbench/basic/gray2bin/rtl/gray2bin.v
logikbench/basic/mux/LICENSE
logikbench/basic/mux/mux.py
logikbench/basic/mux/rtl/mux.v
logikbench/basic/muxcase/LICENSE
logikbench/basic/muxcase/muxcase.py
logikbench/basic/muxcase/rtl/muxcase.v
logikbench/basic/muxhot/LICENSE
logikbench/basic/muxhot/README.md
logikbench/basic/muxhot/muxhot.f
logikbench/basic/muxhot/muxhot.py
logikbench/basic/muxhot/rtl/muxhot.v
logikbench/basic/muxhot/sdc/mux.sdc
logikbench/basic/muxpri/LICENSE
logikbench/basic/muxpri/muxpri.py
logikbench/basic/muxpri/rtl/muxpri.v
logikbench/basic/onehot/onehot.py
logikbench/basic/onehot/rtl/onehot.v
logikbench/basic/pipeline/pipeline.py
logikbench/basic/pipeline/rtl/pipeline.v
logikbench/basic/pipeline/tb/tb.v
logikbench/basic/shiftreg/shiftreg.py
logikbench/basic/shiftreg/rtl/shiftreg.v
logikbench/blocks/README.md
logikbench/blocks/__init__.py
logikbench/blocks/aes/LICENSE
logikbench/blocks/aes/README.md
logikbench/blocks/aes/aes.py
logikbench/blocks/aes/rtl/aes.v
logikbench/blocks/aes/rtl/aes_inv_cipher_top.v
logikbench/blocks/aes/rtl/aes_inv_sbox.v
logikbench/blocks/aes/rtl/aes_key_expand_128.v
logikbench/blocks/aes/rtl/aes_rcon.v
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logikbench/blocks/aes/sdc/aes.sdc
logikbench/blocks/apbregs/apbregs.py
logikbench/blocks/apbregs/rtl/apbregs.v
logikbench/blocks/axicrossbar/LICENSE
logikbench/blocks/axicrossbar/README.md
logikbench/blocks/axicrossbar/axicrossbar.py
logikbench/blocks/axicrossbar/rtl/arbiter.v
logikbench/blocks/axicrossbar/rtl/axi_crossbar.v
logikbench/blocks/axicrossbar/rtl/axi_crossbar_addr.v
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logikbench/blocks/axicrossbar/rtl/axi_crossbar_wr.v
logikbench/blocks/axicrossbar/rtl/axi_register_rd.v
logikbench/blocks/axicrossbar/rtl/axi_register_wr.v
logikbench/blocks/axicrossbar/rtl/priority_encoder.v
logikbench/blocks/axidev/rtl/axidev.v
logikbench/blocks/axihost/rtl/axihost.v
logikbench/blocks/conv2d/rtl/conv2d.v
logikbench/blocks/en8b10b/rtl/en8b10b.v
logikbench/blocks/ethmac/LICENSE
logikbench/blocks/ethmac/README.md
logikbench/blocks/ethmac/ethmac.py
logikbench/blocks/ethmac/rtl/axis_gmii_rx.v
logikbench/blocks/ethmac/rtl/axis_gmii_tx.v
logikbench/blocks/ethmac/rtl/eth_lfsr.v
logikbench/blocks/ethmac/rtl/eth_mac_1g.v
logikbench/blocks/ethmac/rtl/ethmac.v
logikbench/blocks/ethmac/sdc/ethmac.sdc
logikbench/blocks/fft/fft.py
logikbench/blocks/fft/rtl/fft.v
logikbench/blocks/fft/testbench/plot_fft.py
logikbench/blocks/firfix/firfix.py
logikbench/blocks/firfix/rtl/firfix.v
logikbench/blocks/firprog/firprog.py
logikbench/blocks/firprog/rtl/firprog.v
logikbench/blocks/fpu32/README
logikbench/blocks/fpu32/fpu32.py
logikbench/blocks/fpu32/rtl/except.v
logikbench/blocks/fpu32/rtl/fpu.v
logikbench/blocks/fpu32/rtl/post_norm.v
logikbench/blocks/fpu32/rtl/pre_norm.v
logikbench/blocks/fpu32/rtl/pre_norm_fmul.v
logikbench/blocks/fpu32/rtl/primitives.v
logikbench/blocks/fpu64/LICENSE
logikbench/blocks/fpu64/README
logikbench/blocks/fpu64/fpu64.py
logikbench/blocks/fpu64/rtl/ct_vfdsu_ctrl.v
logikbench/blocks/fpu64/rtl/ct_vfdsu_double.v
logikbench/blocks/fpu64/rtl/ct_vfdsu_ff1.v
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logikbench/blocks/fpu64/rtl/ct_vfdsu_round.v
logikbench/blocks/fpu64/rtl/ct_vfdsu_scalar_dp.v
logikbench/blocks/fpu64/rtl/ct_vfdsu_srt.v
logikbench/blocks/fpu64/rtl/ct_vfdsu_srt_radix16_bound_table.v
logikbench/blocks/fpu64/rtl/ct_vfdsu_srt_radix16_only_div.v
logikbench/blocks/fpu64/rtl/ct_vfdsu_srt_radix16_with_sqrt.v
logikbench/blocks/fpu64/rtl/ct_vfdsu_top.v
logikbench/blocks/fpu64/rtl/gated_clk_cell.v
logikbench/blocks/hamming/rtl/hamming.v
logikbench/blocks/i2c/README.md
logikbench/blocks/i2c/i2c.py
logikbench/blocks/i2c/rtl/i2c.v
logikbench/blocks/i2c/rtl/i2c_bit_ctrl.v
logikbench/blocks/i2c/rtl/i2c_byte_ctrl.v
logikbench/blocks/i2c/rtl/i2c_defines.vh
logikbench/blocks/i2c/rtl/la_dsync.v
logikbench/blocks/ialu/README.md
logikbench/blocks/ialu/ialu.py
logikbench/blocks/ialu/rtl/ialu.v
logikbench/blocks/ibex/rtl/ibex.v
logikbench/blocks/lfsr/LICENSE
logikbench/blocks/lfsr/README.md
logikbench/blocks/lfsr/lfsr.py
logikbench/blocks/lfsr/rtl/lfsr.v
logikbench/blocks/lfsr/rtl/lfsr_crc.v
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logikbench/blocks/lfsr/rtl/lfsr_scramble.v
logikbench/blocks/matmul/rtl/matmul.v
logikbench/blocks/median3x3/rtl/median3x3.v
logikbench/blocks/nvdla/README.md
logikbench/blocks/nvdla/nvdla.py
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logikbench/blocks/nvdla/include/simulate_x_tick.vh
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logikbench/blocks/nvdla/rtl/cdma/NV_NVDLA_cdma.v
logikbench/blocks/nvdla/rtl/cdp/NV_NVDLA_CDP_DP_INTP_unit.v
logikbench/blocks/nvdla/rtl/cdp/NV_NVDLA_CDP_DP_LUT_CTRL_unit.v
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logikbench/blocks/nvdla/rtl/cdp/NV_NVDLA_CDP_DP_MUL_unit.v
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logikbench/blocks/nvdla/rtl/cdp/NV_NVDLA_CDP_DP_cvtin.v
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logikbench/blocks/nvdla/rtl/cdp/NV_NVDLA_CDP_DP_intp.v
logikbench/blocks/nvdla/rtl/cdp/NV_NVDLA_CDP_DP_lut.v
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logikbench/blocks/nvdla/rtl/cdp/NV_NVDLA_CDP_DP_sum.v
logikbench/blocks/nvdla/rtl/cdp/NV_NVDLA_CDP_DP_syncfifo.v
logikbench/blocks/nvdla/rtl/cdp/NV_NVDLA_CDP_RDMA_REG_dual.v
logikbench/blocks/nvdla/rtl/cdp/NV_NVDLA_CDP_RDMA_REG_single.v
logikbench/blocks/nvdla/rtl/cdp/NV_NVDLA_CDP_RDMA_cq.v
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logikbench/blocks/nvdla/rtl/cdp/NV_NVDLA_CDP_RDMA_ig.v
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logikbench/blocks/nvdla/rtl/cdp/NV_NVDLA_CDP_rdma.v
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logikbench/blocks/nvdla/rtl/cdp/NV_NVDLA_CDP_slcg.v
logikbench/blocks/nvdla/rtl/cdp/NV_NVDLA_CDP_wdma.v
logikbench/blocks/nvdla/rtl/cdp/NV_NVDLA_cdp.v
logikbench/blocks/nvdla/rtl/cdp/fp_format_cvt.v
logikbench/blocks/nvdla/rtl/cdp/fp_sum_block.v
logikbench/blocks/nvdla/rtl/cdp/int_sum_block.v
logikbench/blocks/nvdla/rtl/cmac/NV_NVDLA_CMAC_CORE_MAC_exp.v
logikbench/blocks/nvdla/rtl/cmac/NV_NVDLA_CMAC_CORE_MAC_mul.v
logikbench/blocks/nvdla/rtl/cmac/NV_NVDLA_CMAC_CORE_MAC_nan.v
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logikbench/blocks/nvdla/rtl/cmac/NV_NVDLA_CMAC_CORE_rt_in.v
logikbench/blocks/nvdla/rtl/cmac/NV_NVDLA_CMAC_CORE_rt_out.v
logikbench/blocks/nvdla/rtl/cmac/NV_NVDLA_CMAC_CORE_slcg.v
logikbench/blocks/nvdla/rtl/cmac/NV_NVDLA_CMAC_REG_dual.v
logikbench/blocks/nvdla/rtl/cmac/NV_NVDLA_CMAC_REG_single.v
logikbench/blocks/nvdla/rtl/cmac/NV_NVDLA_CMAC_core.v
logikbench/blocks/nvdla/rtl/cmac/NV_NVDLA_CMAC_reg.v
logikbench/blocks/nvdla/rtl/cmac/NV_NVDLA_cmac.v
logikbench/blocks/nvdla/rtl/csb_master/NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v
logikbench/blocks/nvdla/rtl/csb_master/NV_NVDLA_CSB_MASTER_falcon2csb_fifo.v
logikbench/blocks/nvdla/rtl/csb_master/NV_NVDLA_csb_master.v
logikbench/blocks/nvdla/rtl/csc/NV_NVDLA_CSC_SG_dat_fifo.v
logikbench/blocks/nvdla/rtl/csc/NV_NVDLA_CSC_SG_wt_fifo.v
logikbench/blocks/nvdla/rtl/csc/NV_NVDLA_CSC_WL_dec.v
logikbench/blocks/nvdla/rtl/csc/NV_NVDLA_CSC_dl.v
logikbench/blocks/nvdla/rtl/csc/NV_NVDLA_CSC_dual_reg.v
logikbench/blocks/nvdla/rtl/csc/NV_NVDLA_CSC_pra_cell.v
logikbench/blocks/nvdla/rtl/csc/NV_NVDLA_CSC_regfile.v
logikbench/blocks/nvdla/rtl/csc/NV_NVDLA_CSC_sg.v
logikbench/blocks/nvdla/rtl/csc/NV_NVDLA_CSC_single_reg.v
logikbench/blocks/nvdla/rtl/csc/NV_NVDLA_CSC_slcg.v
logikbench/blocks/nvdla/rtl/csc/NV_NVDLA_CSC_wl.v
logikbench/blocks/nvdla/rtl/csc/NV_NVDLA_csc.v
logikbench/blocks/nvdla/rtl/glb/NV_NVDLA_GLB_CSB_reg.v
logikbench/blocks/nvdla/rtl/glb/NV_NVDLA_GLB_csb.v
logikbench/blocks/nvdla/rtl/glb/NV_NVDLA_GLB_fc.v
logikbench/blocks/nvdla/rtl/glb/NV_NVDLA_GLB_ic.v
logikbench/blocks/nvdla/rtl/glb/NV_NVDLA_glb.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_CVIF_CSB_reg.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_CVIF_READ_IG_arb.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_CVIF_READ_IG_bpt.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_CVIF_READ_IG_cvt.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_CVIF_READ_IG_spt.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_CVIF_READ_cq.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_CVIF_READ_eg.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_CVIF_READ_ig.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_CVIF_WRITE_IG_arb.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_CVIF_WRITE_IG_bpt.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_CVIF_WRITE_IG_cvt.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_CVIF_WRITE_IG_spt.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_CVIF_WRITE_cq.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_CVIF_WRITE_eg.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_CVIF_WRITE_ig.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_CVIF_csb.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_CVIF_read.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_CVIF_write.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_MCIF_CSB_reg.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_MCIF_READ_IG_arb.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_MCIF_READ_IG_bpt.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_MCIF_READ_IG_cvt.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_MCIF_READ_IG_spt.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_MCIF_READ_cq.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_MCIF_READ_eg.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_MCIF_READ_ig.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_MCIF_WRITE_IG_arb.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_MCIF_WRITE_IG_bpt.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_MCIF_WRITE_IG_cvt.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_MCIF_WRITE_IG_spt.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_MCIF_WRITE_cq.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_MCIF_WRITE_eg.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_MCIF_WRITE_ig.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_MCIF_csb.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_MCIF_read.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_MCIF_write.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_XXIF_libs.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_cvif.v
logikbench/blocks/nvdla/rtl/nocif/NV_NVDLA_mcif.v
logikbench/blocks/nvdla/rtl/pdp/NV_NVDLA_PDP_CORE_cal1d.v
logikbench/blocks/nvdla/rtl/pdp/NV_NVDLA_PDP_CORE_cal2d.v
logikbench/blocks/nvdla/rtl/pdp/NV_NVDLA_PDP_CORE_preproc.v
logikbench/blocks/nvdla/rtl/pdp/NV_NVDLA_PDP_CORE_unit1d.v
logikbench/blocks/nvdla/rtl/pdp/NV_NVDLA_PDP_RDMA_REG_dual.v
logikbench/blocks/nvdla/rtl/pdp/NV_NVDLA_PDP_RDMA_REG_single.v
logikbench/blocks/nvdla/rtl/pdp/NV_NVDLA_PDP_RDMA_cq.v
logikbench/blocks/nvdla/rtl/pdp/NV_NVDLA_PDP_RDMA_eg.v
logikbench/blocks/nvdla/rtl/pdp/NV_NVDLA_PDP_RDMA_ig.v
logikbench/blocks/nvdla/rtl/pdp/NV_NVDLA_PDP_RDMA_reg.v
logikbench/blocks/nvdla/rtl/pdp/NV_NVDLA_PDP_REG_dual.v
logikbench/blocks/nvdla/rtl/pdp/NV_NVDLA_PDP_REG_single.v
logikbench/blocks/nvdla/rtl/pdp/NV_NVDLA_PDP_WDMA_cmd.v
logikbench/blocks/nvdla/rtl/pdp/NV_NVDLA_PDP_WDMA_dat.v
logikbench/blocks/nvdla/rtl/pdp/NV_NVDLA_PDP_core.v
logikbench/blocks/nvdla/rtl/pdp/NV_NVDLA_PDP_nan.v
logikbench/blocks/nvdla/rtl/pdp/NV_NVDLA_PDP_rdma.v
logikbench/blocks/nvdla/rtl/pdp/NV_NVDLA_PDP_reg.v
logikbench/blocks/nvdla/rtl/pdp/NV_NVDLA_PDP_slcg.v
logikbench/blocks/nvdla/rtl/pdp/NV_NVDLA_PDP_wdma.v
logikbench/blocks/nvdla/rtl/pdp/NV_NVDLA_pdp.v
logikbench/blocks/nvdla/rtl/pdp/cal1d_fp16_pool_sum.v
logikbench/blocks/nvdla/rtl/pdp/fp16_4add.v
logikbench/blocks/nvdla/rtl/retiming/NV_NVDLA_RT_cacc2glb.v
logikbench/blocks/nvdla/rtl/retiming/NV_NVDLA_RT_cmac_a2cacc.v
logikbench/blocks/nvdla/rtl/retiming/NV_NVDLA_RT_cmac_b2cacc.v
logikbench/blocks/nvdla/rtl/retiming/NV_NVDLA_RT_csb2cacc.v
logikbench/blocks/nvdla/rtl/retiming/NV_NVDLA_RT_csb2cmac.v
logikbench/blocks/nvdla/rtl/retiming/NV_NVDLA_RT_csc2cmac_a.v
logikbench/blocks/nvdla/rtl/retiming/NV_NVDLA_RT_csc2cmac_b.v
logikbench/blocks/nvdla/rtl/retiming/NV_NVDLA_RT_sdp2nocif.v
logikbench/blocks/nvdla/rtl/rubik/NV_NVDLA_RUBIK_dma.v
logikbench/blocks/nvdla/rtl/rubik/NV_NVDLA_RUBIK_dr2drc.v
logikbench/blocks/nvdla/rtl/rubik/NV_NVDLA_RUBIK_dual_reg.v
logikbench/blocks/nvdla/rtl/rubik/NV_NVDLA_RUBIK_fifo.v
logikbench/blocks/nvdla/rtl/rubik/NV_NVDLA_RUBIK_intr.v
logikbench/blocks/nvdla/rtl/rubik/NV_NVDLA_RUBIK_regfile.v
logikbench/blocks/nvdla/rtl/rubik/NV_NVDLA_RUBIK_rf_core.v
logikbench/blocks/nvdla/rtl/rubik/NV_NVDLA_RUBIK_rf_ctrl.v
logikbench/blocks/nvdla/rtl/rubik/NV_NVDLA_RUBIK_rf_rcmd.v
logikbench/blocks/nvdla/rtl/rubik/NV_NVDLA_RUBIK_rf_wcmd.v
logikbench/blocks/nvdla/rtl/rubik/NV_NVDLA_RUBIK_seq_gen.v
logikbench/blocks/nvdla/rtl/rubik/NV_NVDLA_RUBIK_single_reg.v
logikbench/blocks/nvdla/rtl/rubik/NV_NVDLA_RUBIK_slcg.v
logikbench/blocks/nvdla/rtl/rubik/NV_NVDLA_RUBIK_wr_req.v
logikbench/blocks/nvdla/rtl/rubik/NV_NVDLA_RUBIK_wrdma_cmd.v
logikbench/blocks/nvdla/rtl/rubik/NV_NVDLA_RUBIK_wrdma_data.v
logikbench/blocks/nvdla/rtl/rubik/NV_NVDLA_rubik.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_BRDMA_EG_ro.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_BRDMA_cq.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_BRDMA_eg.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_BRDMA_gate.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_BRDMA_ig.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_CORE_Y_core.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_CORE_Y_cvt.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_CORE_Y_dmapack.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_CORE_Y_dppack.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_CORE_Y_dpunpack.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_CORE_Y_idx.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_CORE_Y_inp.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_CORE_Y_lut.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_CORE_c.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_CORE_gate.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_CORE_x.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_CORE_y.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_ERDMA_EG_ro.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_ERDMA_cq.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_ERDMA_eg.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_ERDMA_gate.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_ERDMA_ig.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_MRDMA_EG_cmd.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_MRDMA_EG_din.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_MRDMA_EG_dout.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_MRDMA_cq.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_MRDMA_eg.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_MRDMA_gate.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_MRDMA_ig.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_NRDMA_EG_ro.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_NRDMA_cq.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_NRDMA_eg.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_NRDMA_gate.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_NRDMA_ig.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_RDMA_REG_dual.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_RDMA_REG_single.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_RDMA_reg.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_REG_dual.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_REG_single.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_WDMA_DAT_in.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_WDMA_DAT_out.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_WDMA_cmd.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_WDMA_dat.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_WDMA_dmaif.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_WDMA_gate.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_brdma.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_cmux.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_core.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_erdma.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_mrdma.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_nrdma.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_rdma.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_reg.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_SDP_wdma.v
logikbench/blocks/nvdla/rtl/sdp/NV_NVDLA_sdp.v
logikbench/blocks/nvdla/rtl/top/NV_NVDLA_partition_a.v
logikbench/blocks/nvdla/rtl/top/NV_NVDLA_partition_c.v
logikbench/blocks/nvdla/rtl/top/NV_NVDLA_partition_m.v
logikbench/blocks/nvdla/rtl/top/NV_NVDLA_partition_o.v
logikbench/blocks/nvdla/rtl/top/NV_NVDLA_partition_p.v
logikbench/blocks/nvdla/rtl/top/NV_nvdla.v
logikbench/blocks/ofdm/rtl/ofdm.v
logikbench/blocks/picorv32/LICENSE
logikbench/blocks/picorv32/README.md
logikbench/blocks/picorv32/picorv32.py
logikbench/blocks/picorv32/rtl/picorv32.v
logikbench/blocks/picorv32/sdc/picorv32.sdc
logikbench/blocks/sad8x8/rtl/sad8x8.v
logikbench/blocks/serv/LICENSE
logikbench/blocks/serv/README.md
logikbench/blocks/serv/serv.py
logikbench/blocks/serv/rtl/serv_aligner.v
logikbench/blocks/serv/rtl/serv_alu.v
logikbench/blocks/serv/rtl/serv_bufreg.v
logikbench/blocks/serv/rtl/serv_bufreg2.v
logikbench/blocks/serv/rtl/serv_compdec.v
logikbench/blocks/serv/rtl/serv_csr.v
logikbench/blocks/serv/rtl/serv_ctrl.v
logikbench/blocks/serv/rtl/serv_debug.v
logikbench/blocks/serv/rtl/serv_decode.v
logikbench/blocks/serv/rtl/serv_immdec.v
logikbench/blocks/serv/rtl/serv_mem_if.v
logikbench/blocks/serv/rtl/serv_rf_if.v
logikbench/blocks/serv/rtl/serv_rf_ram.v
logikbench/blocks/serv/rtl/serv_rf_ram_if.v
logikbench/blocks/serv/rtl/serv_rf_top.v
logikbench/blocks/serv/rtl/serv_state.v
logikbench/blocks/serv/rtl/serv_synth_wrapper.v
logikbench/blocks/serv/rtl/serv_top.v
logikbench/blocks/sobel3x3/rtl/sobel3x3.v
logikbench/blocks/spi/rtl/spi.v
logikbench/blocks/uart/README.md
logikbench/blocks/uart/uart.py
logikbench/blocks/uart/rtl/la_dsync.v
logikbench/blocks/uart/rtl/uart.v
logikbench/blocks/uart/rtl/uart_defines.vh
logikbench/blocks/uart/rtl/uart_raminfr.v
logikbench/blocks/uart/rtl/uart_receiver.v
logikbench/blocks/uart/rtl/uart_rfifo.v
logikbench/blocks/uart/rtl/uart_tfifo.v
logikbench/blocks/uart/rtl/uart_transmitter.v
logikbench/blocks/uart/sdc/uart.sdc
logikbench/blocks/umihost/rtl/umihost.v
logikbench/blocks/umiregs/LICENSE
logikbench/blocks/umiregs/umiregs.py
logikbench/blocks/umiregs/rtl/umi_messages.vh
logikbench/blocks/umiregs/rtl/umiregs.v
logikbench/blocks/viterbi/rtl/viterbi.v
logikbench/epfl/LICENSE
logikbench/epfl/README.md
logikbench/epfl/__init__.py
logikbench/epfl/adder/adder.py
logikbench/epfl/adder/rtl/adder.v
logikbench/epfl/arbiter/arbiter.py
logikbench/epfl/arbiter/rtl/arbiter.v
logikbench/epfl/bar/bar.py
logikbench/epfl/bar/rtl/bar.v
logikbench/epfl/cavlc/cavlc.py
logikbench/epfl/cavlc/rtl/cavlc.v
logikbench/epfl/dec/dec.py
logikbench/epfl/dec/rtl/dec.v
logikbench/epfl/div/div.py
logikbench/epfl/div/rtl/div.v
logikbench/epfl/hyp/hyp.py
logikbench/epfl/hyp/rtl/hyp.v
logikbench/epfl/i2c/i2c.py
logikbench/epfl/i2c/rtl/i2c.v
logikbench/epfl/int2float/int2float.py
logikbench/epfl/int2float/rtl/int2float.v
logikbench/epfl/log2/log2.py
logikbench/epfl/log2/rtl/log2.v
logikbench/epfl/max/max.py
logikbench/epfl/max/rtl/max.v
logikbench/epfl/mem_ctrl/mem_ctrl.py
logikbench/epfl/mem_ctrl/rtl/mem_ctrl.v
logikbench/epfl/multiplier/multiplier.py
logikbench/epfl/multiplier/rtl/multiplier.v
logikbench/epfl/priority/priority.py
logikbench/epfl/priority/rtl/priority.v
logikbench/epfl/router/router.py
logikbench/epfl/router/rtl/router.v
logikbench/epfl/sin/sin.py
logikbench/epfl/sin/rtl/sin.v
logikbench/epfl/sqrt/sqrt.py
logikbench/epfl/sqrt/rtl/sqrt.v
logikbench/epfl/square/square.py
logikbench/epfl/square/rtl/square.v
logikbench/epfl/voter/voter.py
logikbench/epfl/voter/rtl/voter.v
logikbench/flows/__init__.py
logikbench/flows/synth.py
logikbench/memory/README.md
logikbench/memory/__init__.py
logikbench/memory/axiram/LICENSE
logikbench/memory/axiram/README.md
logikbench/memory/axiram/axiram.py
logikbench/memory/axiram/rtl/axil_ram.v
logikbench/memory/cache/README.md
logikbench/memory/cache/cache.py
logikbench/memory/cache/rtl/cache.v
logikbench/memory/fifoasync/fifoasync.py
logikbench/memory/fifoasync/rtl/fifoasync.v
logikbench/memory/fifosync/fifosync.py
logikbench/memory/fifosync/rtl/fifosync.v
logikbench/memory/fifosync/rtl/la_syncfifo.v
logikbench/memory/fifosync/tb/tb.v
logikbench/memory/ramasync/ramasync.py
logikbench/memory/ramasync/rtl/ramasync.v
logikbench/memory/rambit/rambit.py
logikbench/memory/rambit/rtl/rambit.v
logikbench/memory/rambyte/rambyte.py
logikbench/memory/rambyte/rtl/rambyte.v
logikbench/memory/ramdp/ramdp.py
logikbench/memory/ramdp/rtl/ramdp.v
logikbench/memory/ramsdp/LICENSE
logikbench/memory/ramsdp/README.md
logikbench/memory/ramsdp/ramsdp.py
logikbench/memory/ramsdp/constraint/ramsdp.sdc
logikbench/memory/ramsdp/rtl/ramsdp.v
logikbench/memory/ramsp/LICENSE
logikbench/memory/ramsp/README.md
logikbench/memory/ramsp/ramsp.py
logikbench/memory/ramsp/constraint/ramsp.sdc
logikbench/memory/ramsp/rtl/ramsp.v
logikbench/memory/ramspnc/LICENSE
logikbench/memory/ramspnc/ramspnc.py
logikbench/memory/ramspnc/rtl/ramspnc.v
logikbench/memory/regfile/LICENSE
logikbench/memory/regfile/README.md
logikbench/memory/regfile/regfile.py
logikbench/memory/regfile/rtl/regfile.v
logikbench/memory/rom/rom.py
logikbench/memory/rom/rtl/rom.v
logikbench/targets/asic/freepdk45/default.sdc
logikbench/targets/asic/freepdk45/synth.tcl
logikbench/targets/asic/freepdk45/timing.tcl
logikbench/tools/__init__.py
logikbench/tools/opensta/__init__.py
logikbench/tools/yosys/__init__.py
logikbench/tools/yosys/yosys.py
logikbench/tools/yosys/scripts/synthesis.tcl
logikbench/tools/yosys/scripts/asic/synthesis_asic.tcl
logikbench/tools/yosys/scripts/fpga/synthesis_fpga.tcl
results/README.md
results/fpga/achronix_speedster_small.json
results/fpga/adi_flex16ffc_small.json
results/fpga/efinix_trion_small.json
results/fpga/fabulous_generic_small.json
results/fpga/gatemate_cologne_small.json
results/fpga/gowin_gw5a_small.json
results/fpga/lattice_ecp5_small.json
results/fpga/lattice_ice40_small.json
results/fpga/microchip_polarfire_small.json
results/fpga/quicklogic_polarpro_small.json
results/fpga/small.json
results/fpga/xilinx_virtex7_small.json
results/fpga/zeroasic_z1010_small.json
results/fpga/zeroasic_z1060_small.json
scripts/gen_classes.py
scripts/gen_readme.py
scripts/template.py.j2
tests/conftest.py
tests/test_lint.py
tests/test_setup.py